AD AD8132ARZ1 Low cost, high speed differential amplifier Datasheet

Low Cost, High Speed
Differential Amplifier
AD8132
Low power differential ADC drivers
Differential gain and differential filtering
Video line drivers
Differential in/out level shifting
Single-ended input to differential output drivers
Active transformers
Automotive driver assistance
Automotive infotainment
GENERAL DESCRIPTION
The AD8132 is a low cost differential or single-ended input to
differential output amplifier with resistor set gain. The AD8132
is a major advancement over op amps for driving differential input
ADCs or for driving signals over long lines. The AD8132 has a
unique internal feedback feature that provides output gain and
phase matching balanced to −68 dB at 10 MHz, suppressing
harmonics and reducing radiated EMI.
Manufactured using the next-generation of Analog Devices, Inc.,
XFCB bipolar process, the AD8132 has a −3 dB bandwidth of
350 MHz and delivers a differential signal with −99 dBc SFDR
at 5 MHz, despite its low cost. The AD8132 eliminates the need for
a transformer with high performance ADCs, preserving the low
frequency and dc information. The common-mode level of the
differential output is adjustable by applying a voltage on the
VOCM pin, easily level shifting the input signals for driving singlesupply ADCs. Fast overload recovery preserves sampling accuracy.
–IN 1
AD8132
8
+IN
VOCM 2
7
NC
V+ 3
6
V–
+OUT 4
5
–OUT
NC = NO CONNECT
Figure 1.
The AD8132 is also used as a differential driver for the transmission of high speed signals over low cost twisted pair or coaxial
cables. The feedback network can be adjusted to boost the high
frequency components of the signal. The AD8132 is used for either
analog or digital video signals or for other high speed data transmission. The AD8132 is capable of driving either a Category 3
or Category 5 twisted pair or coaxial cable with minimal line
attenuation. The AD8132 has considerable cost and performance
improvements over discrete line driver solutions.
Differential signal processing reduces the effects of ground noise
that plagues ground-referenced systems. The AD8132 can be used
for differential signal processing (gain and filtering) throughout a
signal chain, easily simplifying the conversion between differential
and single-ended components.
The AD8132W is the automotive grade version, qualified for
125°C operation per the AEC-Q100. See the Automotive
Products section for more details.
The AD8132 is available in both 8-lead SOIC and 8-lead MSOP
packages for operation over the extended industrial temperature
range of −40°C to +125°C.
6
VS = ±5V
G = +1
VO, dm = 2V p-p
RL, dm = 499Ω
3
0
–3
–6
–9
–12
1
10
100
FREQUENCY (MHz)
1k
01035-002
APPLICATIONS
CONNECTION DIAGRAM
GAIN (dB)
High speed
350 MHz, −3 dB bandwidth
1200 V/μs slew rate
Resistor set gain
Internal common-mode feedback
Improved gain and phase balance: −68 dB @ 10 MHz
Separate input to set the common-mode output voltage
Low distortion: −99 dBc SFDR @ 5 MHz, 800 Ω load
Low power: 10.7 mA @ 5 V
Power supply range: +2.7 V to ±5.5 V
Fully AEC-Q100 qualified (AD8132W)
01035-001
FEATURES
Figure 2. Large Signal Frequency Response
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.
AD8132* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
Tools and Simulations
View a parametric search of comparable parts
• ADI DiffAmpCalc™
• AD8132 SPICE Macro-Model
Evaluation Kits
• Universal Evaluation Board for Single Differential
Amplifiers
Documentation
Application Notes
• AN-0990: Terminating a Differential Amplifier in SingleEnded Input Applications
• AN-0992: Active Filter Evaluation Board for Differential
Amplifiers
• AN-1026: High Speed Differential ADC Driver Design
Considerations
• AN-1363: Meeting Biasing Requirements of Externally
Biased RF/Microwave Amplifiers with Active Bias
Controllers
• AN-282: Fundamentals of Sampled Data Systems
• AN-584: Using the AD813X Differential Amplifier
• AN-589: Ways to Optimize the Performance of a
Difference Amplifier
• AN-649: Using the Analog Devices Active Filter Design
Tool
Data Sheet
• AD8132: Low-Cost, High Speed Differential Amplifier
Data Sheet
User Guides
• UG-474: Evaluation Board for Differential Amplifiers
Offered in 8-Lead SOIC Packages
• UG-888: Evaluation Board for Differential Amplifiers
Offered in 8-Lead MSOP Packages
Reference Materials
Product Selection Guide
• Amplifiers for Video Distribution
• High Speed Amplifiers Selection Table
Tutorials
• MT-075: Differential Drivers for High Speed ADCs
Overview
• MT-076: Differential Driver Analysis
• MT-218: Multiple Feedback Band-Pass Design Example
Design Resources
•
•
•
•
AD8132 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
Discussions
View all AD8132 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
AD8132
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Differential Amplifier Without Resistors (High Input
Impedance Inverting Amplifier) .............................................. 22
General Description ......................................................................... 1
Other β2 = 1 Circuits ................................................................. 23
Connection Diagram ....................................................................... 1
Varying β2 ................................................................................... 23
Revision History ........................................................................... 3
β1 = 0............................................................................................ 23
Specifications..................................................................................... 4
Estimating the Output Noise Voltage ...................................... 23
±DIN to ±OUT Specifications...................................................... 4
Calculating Input Impedance of the Application Circuit ..... 24
VOCM to ±OUT Specifications ..................................................... 5
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 24
±DIN to ±OUT Specifications...................................................... 6
VOCM to ±OUT Specifications ..................................................... 7
±DIN to ±OUT Specifications...................................................... 8
VOCM to ±OUT Specifications ..................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
Maximum Power Dissipation ..................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
Test Circuits ..................................................................................... 20
Operational Description ................................................................ 21
Definition of Terms .................................................................... 21
Basic Circuit Operation ............................................................. 21
Theory of Operation ...................................................................... 22
General Usage of the AD8132 .................................................. 22
Setting the Output Common-Mode Voltage .......................... 24
Driving a Capacitive Load......................................................... 24
Open-Loop Gain and Phase ..................................................... 24
Layout, Grounding, and Bypassing .............................................. 25
Circuits......................................................................................... 25
Applications Information .............................................................. 26
Analog-to-Digital Driver .......................................................... 26
Balanced Cable Driver ............................................................... 26
Transmit Equalizer ..................................................................... 27
Low-Pass Differential Filter ...................................................... 27
High Common-Mode Output Impedance Amplifier ........... 28
Full-Wave Rectifier .................................................................... 29
Automotive Products ................................................................. 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
Rev. I | Page 2 of 32
AD8132
REVISION HISTORY
9/09—Rev. H to Rev. I
11/05—Rev. D to Rev. E
Changes to Figure 64 Caption ......................................................21
Changes to Table 7, Thermal Resistance Section, Maximum
Power Dissipation Section, and Figure 3 ...................................... 8
5/09—Rev. G to Rev. H
Changes to Features Section, Applications Section, and General
Description Section .......................................................................... 1
Changes to Ordering Guide .......................................................... 29
Changes to Table 1 ........................................................................... 4
Changes to General Description .................................................... 1
Changes to Table 2 ........................................................................... 5
Changes to Specifications ............................................................... 2
Changes to Table 3 ........................................................................... 6
Changes to Absolute Maximum Ratings....................................... 8
Changes to Table 4 ........................................................................... 7
Updated Outline Dimensions....................................................... 29
Added Automotive Products Section ..........................................29
Changes to Ordering Guide .......................................................... 29
Changes to Ordering Guide ..........................................................30
2/03—Rev. B to Rev. C
1/09—Rev. F to Rev. G
Changes to Specifications ............................................................... 2
Changes to Figure 77 .....................................................................26
Addition to Estimating the Output Noise Voltage Section ...... 15
Updated Outline Dimensions .......................................................29
Updated Outline Dimensions....................................................... 21
11/06—Rev. E to Rev. F
1/02—Rev. A to Rev. B
Updated Format................................................................. Universal
Edits to Transmitter Equalizer Section ....................................... 18
12/04—Rev. C to Rev. D
Changes to Table 1 ........................................................................... 3
Changes to Table 4 ........................................................................... 6
Changes to Table 5 ........................................................................... 7
Changes to Ordering Guide ..........................................................29
Rev. I | Page 3 of 32
AD8132
SPECIFICATIONS
±DIN TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = ±5 V, VOCM = 0 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
IP3
Input Voltage Noise (RTI)
Input Current Noise
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Offset Voltage (RTI)
Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Balance Error
Conditions
Min
Typ
VOUT = 2 V p-p
AD8132W only, TMIN to TMAX
VOUT = 2 V p-p, G = +2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = +2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = +2
VOUT = 2 V p-p
AD8132W only, TMIN to TMAX
0.1%, VOUT = 2 V p-p
VIN = 5 V to 0 V step, G = +2
300
280
350
Max
Unit
15
5
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/μs
V/μs
ns
ns
VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
20 MHz, RL, dm = 800 Ω
20 MHz, RL, dm = 800 Ω
f = 0.1 MHz to 100 MHz
f = 0.1 MHz to 100 MHz
NTSC, G = +2, RL, dm = 150 Ω
NTSC, G = +2, RL, dm = 150 Ω
−96
−83
−73
−102
−98
−67
−76
40
8
1.8
0.01
0.10
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
%
Degrees
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 0 V
AD8132W only, TMIN to TMAX
TMIN to TMAX variation
TA = 25°C
AD8132W only, TMIN to TMAX
Differential
Common mode
±1.0
ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±1 V; resistors matched to 0.01%
AD8132W only, TMIN to TMAX
Maximum ΔVOUT; single-ended output
ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V
Rev. I | Page 4 of 32
1000
950
190
360
160
90
50
1200
10
3
12
3.5
1
−4.7 to +3.0
−70
−3.6 to +3.6
+70
−70
±3.5
±6
7
8
−60
−60
mV
mV
μV/°C
μA
μA
MΩ
MΩ
pF
V
dB
dB
V
mA
dB
AD8132
VOCM TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = ±5 V, VOCM = 0 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
Conditions
Min
ΔVOCM = 600 mV p-p
ΔVOCM = −1 V to +1 V
f = 0.1 MHz to 100 MHz
VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 0 V
AD8132W only, TMIN to TMAX
ΔVOUT, dm/ΔVOCM; ΔVOCM = ±1 V; resistors matched to 0.01%
ΔVOUT, cm/ΔVOCM; ΔVOCM = ±1 V
AD8132W only, TMIN to TMAX
VDIN+ = VDIN− = VOCM = 0 V
AD8132W only, TMIN to TMAX
TMIN to TMAX variation
ΔVOUT, dm/ΔVS; ΔVS = ±1 V
AD8132W only, TMIN to TMAX
OPERATING TEMPERATURE RANGE
0.985
0.985
±1.35
11
9
Max
Unit
210
400
12
MHz
V/μs
nV/√Hz
±3.6
50
±1.5
V
kΩ
mV
mV
μA
dB
V/V
V/V
0.5
−68
1
12
16
−70
−40
Rev. I | Page 5 of 32
Typ
±7
±9
1.015
1.015
±5.5
13
14.5
−60
−60
+125
V
mA
mA
μA/°C
dB
dB
°C
AD8132
±DIN TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
IP3
Input Voltage Noise (RTI)
Input Current Noise
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Offset Voltage (RTI)
Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Balance Error
Conditions
Min
Typ
VOUT = 2 V p-p
AD8132W only, TMIN to TMAX
VOUT = 2 V p-p, G = +2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = +2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = +2
VOUT = 2 V p-p
AD8132W only, TMIN to TMAX
0.1%, VOUT = 2 V p-p
VIN = 2.5 V to 0 V step, G = +2
250
240
300
Max
Unit
20
5
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/μs
V/μs
ns
ns
VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
20 MHz, RL, dm = 800 Ω
20 MHz, RL, dm = 800 Ω
f = 0.1 MHz to 100 MHz
f = 0.1 MHz to 100 MHz
NTSC, G = +2, RL, dm = 150 Ω
NTSC, G = +2, RL, dm = 150 Ω
−97
−100
−74
−100
−99
−67
−76
40
8
1.8
0.025
0.15
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
%
Degrees
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 2.5 V
AD8132W only, TMIN to TMAX
TMIN to TMAX variation
TA = 25°C
±1.0
Differential AD8132W only, TMIN to TMAX
Common-mode
ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±1 V; resistors matched to 0.01%
AD8132W only, TMIN to TMAX
AD8132W only, TMIN to TMAX
Maximum ΔVOUT; single-ended output
ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V
Rev. I | Page 6 of 32
800
750
180
360
155
65
50
1000
6
3
10
3
1
0.3 to 3.0
−70
1.0 to 4.0
50
−68
±3.5
±6
7
8
−60
−60
mV
mV
μV/°C
μA
μA
MΩ
MΩ
pF
V
dB
dB
V
mA
dB
AD8132
VOCM TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 4.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
Conditions
Min
ΔVOCM = 600 mV p-p
ΔVOCM = 1.5 V to 3.5 V
f = 0.1 MHz to 100 MHz
VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 2.5 V
AD8132W only, TMIN to TMAX
ΔVOUT, dm/ΔVOCM; ΔVOCM = 2.5 V ±1 V; resistors matched to 0.01%
ΔVOUT, cm/ΔVOCM; ΔVOCM = 2.5 V ±1 V
AD8132W only, TMIN to TMAX
VDIN+ = VDIN− = VOCM = 2.5 V
AD8132W only, TMIN to TMAX
TMIN to TMAX variation
ΔVOUT, dm/ΔVS; ΔVS = ±1 V
AD8132W only, TMIN to TMAX
OPERATING TEMPERATURE RANGE
0.985
0.985
2.7
9.4
6
Max
Unit
210
340
12
MHz
V/μs
nV/√Hz
1.0 to 3.7
30
±5
V
kΩ
mV
mV
μA
dB
V/V
V/V
0.5
−66
1
10.7
10
−70
−40
Rev. I | Page 7 of 32
Typ
±11
±13
1.015
1.015
11
12
13
−60
−60
+125
V
mA
mA
μA/°C
dB
dB
°C
AD8132
±DIN TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = 3 V, VOCM = 1.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 5.
Parameter
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
INPUT CHARACTERISTICS
Offset Voltage (RTI)
Input Bias Current
Input Common-Mode Voltage
CMRR
Conditions
Min
Typ
Max
Unit
VOUT = 1 V p-p
VOUT = 1 V p-p, G = +2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = +2
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p, G = +2
350
165
350
150
45
50
MHz
MHz
MHz
MHz
MHz
MHz
VOUT = 1 V p-p, 1 MHz, RL, dm = 800 Ω
VOUT = 1 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 1 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 1 V p-p, 1 MHz, RL, dm = 800 Ω
VOUT = 1 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 1 V p-p, 20 MHz, RL, dm = 800 Ω
−100
−94
−77
−90
−85
−66
dBc
dBc
dBc
dBc
dBc
dBc
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 1.5 V
±10
3
0.3 to 1.0
−60
mV
μA
V
dB
ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±0.5 V; resistors matched to 0.01%
VOCM TO ±OUT SPECIFICATIONS
At TA = 25°C, VS = 3 V, VOCM = 1.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω,
RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and
differential outputs, unless otherwise noted.
Table 6.
Parameter
DC PERFORMANCE
Input Offset Voltage
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
Conditions
Min
VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 1.5 V
ΔVOUT, cm/ΔVOCM; ΔVOCM = ±0.5 V
Typ
±7
1
2.7
VDIN+ = VDIN− = VOCM = 0 V
ΔVOUT, dm/ΔVS; ΔVS = ±0.5 V
Unit
mV
V/V
11
7.25
−70
−40
Rev. I | Page 8 of 32
Max
+125
V
mA
dB
°C
AD8132
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
Supply Voltage
VOCM
Internal Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
±5.5 V
±VS
250 mW
−40°C to +125°C
−65°C to +150°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of the differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. Consider rms voltages and
currents when dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces through holes, ground,
and power planes reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(θJA = 121°C/W) and 8-lead MSOP (θJA = 142°C/W) packages
on a JEDEC standard 4-layer board. θJA values are approximations.
1.75
Table 8.
Unit
°C/W
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8132 packages
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the AD8132. Exceeding a junction temperature of 150°C for
an extended period can result in changes in the silicon devices,
potentially causing failure.
1.50
1.25
1.00
SOIC
0.75
MSOP
0.50
0.25
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. I | Page 9 of 32
01035-082
θJA
121
142
MAXIMUM POWER DISSIPATION (W)
Package Type
8-Lead SOIC, 4-Layer
8-Lead MSOP, 4-Layer
AD8132
–IN 1
AD8132
8
+IN
VOCM 2
7
NC
V+ 3
6
V–
+OUT 4
5
–OUT
NC = NO CONNECT
01035-004
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1
2
Mnemonic
−IN
VOCM
3
4
5
6
7
8
V+
+OUT
−OUT
V−
NC
+IN
Description
Negative Input.
Voltage applied to this pin sets the common-mode output voltage with a ratio of 1:1. For example, 1 V dc on
VOCM sets the dc bias level on +OUT and −OUT to 1 V.
Positive Supply Voltage.
Positive Output. Note that the voltage at −DIN is inverted at +OUT (see Figure 64).
Negative Output. Note that the voltage at +DIN is inverted at −OUT (see Figure 64).
Negative Supply Voltage.
No Connect.
Positive Input.
Rev. I | Page 10 of 32
AD8132
TYPICAL PERFORMANCE CHARACTERISTICS
2
3
VS = +3V
1
VS = +5V
VS = +5V
1
0
GAIN (dB)
VS = ±5V
–1
–2
G = +1
VO, dm = 0.2V p-p
RL, dm = 499Ω
–4
G = +1
VO, dm = 2V p-p FOR VS = ±5V, +5V
VO, dm = 1V p-p FOR VS = +3V
RL, dm = 499Ω
–4
1k
–5
1
Figure 5. Small Signal Frequency Response (See Figure 56)
1k
2
G = +1
VO, dm = 0.2V p-p
RL, dm = 499Ω
0.3
VS = +3V
1
VS = +5V
0.2
VS = +5V
0
GAIN (dB)
0.1
0
–0.1
VS = +3V
VS = ±5V
–0.2
VS = ±5V
–1
–2
G = +1
VO, dm = 2V p-p FOR VS = ±5V, +5V
VO, dm = 1V p-p FOR VS = +3V
RL, dm = 499Ω
–3
–0.3
–4
–0.4
1
10
100
FREQUENCY (MHz)
1k
–5
01035-007
–0.5
Figure 6. 0.1 dB Flatness vs. Frequency; CF = 0 pF (See Figure 56)
1
Figure 9. Large Signal Frequency Response; CF = 0.5 pF (See Figure 56)
0.2
3
VS = +3V
0.1
1k
10
100
FREQUENCY (MHz)
01035-010
0.4
+85°C
+25°C
2
VS = +5V
1
VS = ±5V
–0.1
–0.2
–0.3
1k
Figure 7. 0.1 dB Flatness vs. Frequency; CF = 0.5 pF (See Figure 56)
–5
01035-008
10
100
FREQUENCY (MHz)
–2
VS = ±5V
G = +1
VO, dm = 2V p-p
RL, dm = 499Ω
–4
–0.5
1
–40°C
–1
–3
G = +1
VO, dm = 0.2V p-p
RL, dm = 499Ω
–0.4
0
1
10
100
FREQUENCY (MHz)
1k
01035-011
GAIN (dB)
0
GAIN (dB)
10
100
FREQUENCY (MHz)
Figure 8. Large Signal Frequency Response; CF = 0 pF (See Figure 56)
0.5
GAIN (dB)
–2
–3
10
100
FREQUENCY (MHz)
1
–1
01035-009
–3
01035-006
GAIN (dB)
0
–5
VS = ±5V
VS = +3V
2
Figure 10. Large Signal Frequency Response at Various Temperatures
(See Figure 56)
Rev. I | Page 11 of 32
AD8132
6.1
3
RF = 499Ω
2
6.0
RF = 348Ω
1
GAIN (dB)
RF = 249Ω
–1
–2
5.7
–5
1
1k
10
100
FREQUENCY (MHz)
5.5
01035-012
–4
VS = +3V, +5V, ±5V
G = +2
VO, dm = 0.2V p-p
RL, dm = 200Ω
5.6
1
10
100
FREQUENCY (MHz)
1k
01035-016
VS = ±5V
G = +1
VO, dm = 2V p-p
RL, dm = 499Ω
–3
5.8
1k
01035-017
GAIN (dB)
5.9
0
Figure 14. 0.1 dB Flatness vs. Frequency (See Figure 57)
Figure 11. Large Signal Frequency Response vs. RF (See Figure 56)
7
100
VS = +5V, ±5V
6
GAIN (dB)
IMPEDANCE (Ω)
VS = +3V
5
10
4
G = +2
VO, dm = 2V p-p FOR
VS = ±5V, +5V
VO, dm = 1V p-p FOR
VS = +3V
RL, dm = 200Ω
3
1
VS = +5V
2
VS = ±5V
1
10
FREQUENCY (MHz)
100
1
01035-013
1
Figure 12. Closed-Loop Single-Ended ZOUT vs. Frequency; G = +1 (See Figure 56)
Figure 15. Large Signal Frequency Response (See Figure 57)
7
7
5
RF = 1.0kΩ
5
GAIN (dB)
VS = ±5V, +5V
4
VS = +3V
3
RF = 499Ω
4
VS = ±5V
G = +2
VO, dm = 0.2V p-p
RL, dm = 200Ω
3
G = +2
VO, dm = 0.2V p-p
RL, dm = 200Ω
2
1
10
100
FREQUENCY (MHz)
2
1k
1
01035-015
GAIN (dB)
RF = 1.5kΩ
6
6
1
10
100
FREQUENCY (MHz)
1
10
100
FREQUENCY (MHz)
1k
Figure 16. Small Signal Frequency Response vs. RF (See Figure 57)
Figure 13. Small Signal Frequency Response (See Figure 57)
Rev. I | Page 12 of 32
01035-018
0.1
AD8132
–30
25
G = +10, RF = 4.99kΩ
G = +5, RF = 2.49kΩ
DISTORTION (dBc)
10
G = +2, RF = 1kΩ
5
G = +1, RF = 499Ω
0
VS = ±5V
VO, dm = 2V p-p
RL, dm = 200Ω
RG = 499Ω
–5
–10
–15
1
HD3 (V S = ±5V)
–70
HD2 (VS = +5V)
–80
–100
1k
10
100
FREQUENCY (MHz)
–110
0
–40
VS = ±5V
ΔVO, dm = 2V p-p
ΔVO, cm/ΔVO, dm
–35
20
30
40
FREQUENCY (MHz)
VS = 3V
RL, dm = 800Ω
–50
–60
DISTORTION (dBc)
–40
–45
10
50
60
70
Figure 20. Harmonic Distortion vs. Frequency, G = 1 (See Figure 62)
–25
RTI BALANCE ERROR (dB)
HD2 (V S = ±5V)
–60
–90
Figure 17. Large Signal Frequency Response for Various Gains
(See Figure 58)
–30
HD3 (V S = +5V)
–50
01035-020
GAIN (dB)
15
RL, dm = 800Ω
VO, dm = 2V p-p
–40
01035-025
20
G=1
–50
–55
–60
HD3 (f = 20MHz)
HD2 (f = 20MHz)
–70
–80
–90
G=2
–65
HD3 (f = 5MHz)
–100
–70
10
100
FREQUENCY (MHz)
1k
–110
0.25
1.75
Figure 21. Harmonic Distortion vs.
Differential Output Voltage, G = 1 (See Figure 62)
Figure 18. RTI Output Balance Error vs. Frequency (See Figure 59)
–40
–40
RL, dm = 800Ω
VO, dm = 1V p-p
–50
VS = 5V
RL, dm = 800Ω
–50
HD3 (VS = 3V)
HD3 (f = 20MHz)
–60
DISTORTION (dBc)
–60
DISTORTION (dBc)
1.50
0.50
0.75
1.00
1.25
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
01035-026
1
01035-022
–75
HD2 (f = 5MHz)
HD2 (VS = 3V)
–70
–80
HD2 (VS = 5V)
–70
HD2 (f = 20MHz)
–80
HD2 (f = 5MHz)
–90
–90
–100
–100
HD3 (f = 5MHz)
0
10
20
30
40
FREQUENCY (MHz)
50
60
70
–110
0
1
2
3
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
Figure 22. Harmonic Distortion vs.
Differential Output Voltage, G = +1 (See Figure 62)
Figure 19. Harmonic Distortion vs. Frequency, G = +1 (See Figure 62)
Rev. I | Page 13 of 32
4
01035-027
–110
01035-024
HD3 (V S = 5V)
AD8132
–50
–40
VS = ±5V
RL, dm = 800Ω
–50
HD3 (f = 20MHz)
–60
DISTORTION (dBc)
HD2 (f = 20MHz)
–60
–70
–80
HD2 (f = 5MHz)
–90
–70
HD2 (f = 20MHz)
–80
HD2 (f = 5MHz)
–90
–100
–100
6
01035-028
1
2
3
4
5
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
0
–110
200
HD3 (f = 20MHz)
DISTORTION (dBc)
HD2 (f = 20MHz)
–80
–90
HD3 (f = 5MHz)
900
1000
HD2 (VS = 5V)
–80
HD2 (VS = 3V)
HD3 (V S = 5V)
700
600
RLOAD (Ω)
800
900
1000
01035-029
500
–70
–110
0
10
20
40
30
FREQUENCY (MHz)
–20
VS = 5V
VO, dm = 2V p-p
DISTORTION (dBc)
HD2 (f = 20MHz)
HD2 (f = 5MHz)
–90
70
HD2 (VS = +5V)
–40
–70
–80
60
HD3 (VS = +5V)
RL, dm = 800Ω
VO, dm = 4V p-p
–30
HD3 (f = 20MHz)
–60
50
Figure 27. Harmonic Distortion vs. Frequency, G = +2 (See Figure 63)
Figure 24. Harmonic Distortion vs. RLOAD, G = +1 (See Figure 62)
–50
HD3 (VS = ±5V)
–60
–70
–80
HD2 (VS = ±5V)
HD3 (f = 5MHz)
–90
–110
200
300
400
500
600
700
RLOAD (Ω)
800
900
1000
01035-030
DISTORTION (dBc)
800
–100
HD2 (f = 5MHz)
–100
700
HD3 (VS = 3V)
–90
–100
–50
RLOAD (Ω)
–100
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
80
01035-034
DISTORTION (dBc)
–70
400
600
RL, dm = 800Ω
VO, dm = 1V p-p
–50
–60
300
500
–40
VS = 3V
VO, dm = 1V p-p
–60
–110
200
400
Figure 26. Harmonic Distortion vs. RLOAD, G = +1 (See Figure 62)
Figure 23. Harmonic Distortion vs.
Differential Output Voltage, G = +1 (See Figure 62)
–50
300
01035-031
HD3 (f = 5MHz)
HD3 (f = 5MHz)
–110
01035-033
DISTORTION (dBc)
VS = ±5V
VO, dm = 2V p-p
HD3 (f = 20MHz)
Figure 28. Harmonic Distortion vs. Frequency, G = +2 (See Figure 63)
Figure 25. Harmonic Distortion vs. RLOAD, G = +1 (See Figure 62)
Rev. I | Page 14 of 32
AD8132
–40
–50
VS = 5V
RL, dm = 800Ω
–50
VS = ±5V
VO, dm = 2V p-p
HD3 (f = 20MHz)
–60
–60
HD2 (f = 20MHz)
DISTORTION (dBc)
DISTORTION (dBc)
HD3 (f = 20MHz)
–70
HD2 (f = 20MHz)
–80
–90
HD2 (f = 5MHz)
–70
–80
HD2 (f = 5MHz)
–90
–100
–100
–110
HD3 (f = 5MHz)
2
1
3
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
0
4
–110
200
01035-035
–40
600
700
RLOAD (Ω)
800
900
1000
fC = 20MHz
VS = ±5V
RL, dm = 800Ω
0
–10
POUT (dBm [Re: 50Ω])
HD2 (f = 20MHz)
–70
–80
–90
HD3 (f = 5MHz)
–100
–30
–40
–50
–60
–70
HD2 (f = 5MHz)
–80
6
–90
19.5
01035-036
2
5
4
1
3
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
0
–20
Figure 30. Harmonic Distortion vs.
Differential Output Voltage, G = +2 (See Figure 63)
20.0
FREQUENCY (MHz)
20.5
01035-039
–60
DISTORTION (dBc)
500
10
HD3 (f = 20MHz)
VS = 5V
RL, dm = 800Ω
–50
70
Figure 33. Intermodulation Distortion, G = +1
–50
45
VS = 5V
VO, dm = 2V p-p
VS = ±5V, +5V
RL, dm = 800Ω
HD3 (f = 20MHz)
–60
INTERCEPT (dBm [Re: 50Ω])
40
–70
HD2 (f = 20MHz)
–80
HD2 (f = 5MHz)
–90
–100
35
30
25
20
HD3 (f = 5MHz)
–110
200
300
400
500
600
700
RLOAD (Ω)
800
900
1000
01035-037
DISTORTION (dBc)
400
Figure 32. Harmonic Distortion vs. RLOAD, G = +2 (See Figure 63)
Figure 29. Harmonic Distortion vs.
Differential Output Voltage, G = +2 (See Figure 63)
–110
300
01035-040
–120
01035-038
HD3 (f = 5MHz)
15
0
10
20
30
40
FREQUENCY (MHz)
50
60
Figure 34. Third-Order Intercept vs. Frequency, G = +1
Figure 31. Harmonic Distortion vs. RLOAD, G = +2 (See Figure 63)
Rev. I | Page 15 of 32
AD8132
CF = 0pF
VS = ±5V, +5V, +3V
VS = ±5V
VO, dm = 2V p-p
5ns
400mV
Figure 35. Small Signal Transient Response, G = +1
5ns
01035-044
40mV
01035-041
CF = 0.5pF
Figure 38. Large Signal Transient Response, G = +1
VS = 3V
VO, dm = 1.5V p-p
CF = 0pF
VO, dm
CF = 0.5pF
V–OUT
V+OUT
5ns
1V
Figure 36. Large Signal Transient Response, G = +1
CF = 0pF
5ns
01035-045
300mV
01035-042
V+DIN
Figure 39. Large Signal Transient Response, G = +1
VS = ±5V, +5V, +3V
VS = 5V
VO, dm = 2V p-p
5ns
40mV
Figure 37. Large Signal Transient Response, G = +1
5ns
Figure 40. Small Signal Transient Response, G = +2
Rev. I | Page 16 of 32
01035-046
400mV
01035-043
CF = 0.5pF
AD8132
VS = ±5V
G = +1
VO, dm = 2V p-p
RL, dm = 499Ω
5ns
2mV
0
5
Figure 41. Large Signal Transient Response, G = +2
10
5ns
15
20
25
5ns/DIV
30
35
01035-050
300mV
01035-047
0.1%/DIV
VS = 3V
40
Figure 44. 0.1% Settling Time
CL = 0pF
VS = +5V, ±5V
CL = 5pF
5ns
5ns
400mV
Figure 42. Large Signal Transient Response, G = +2
01035-052
400mV
01035-048
CL = 20pF
Figure 45. Large Signal Transient Response
for Various Capacitor Loads (See Figure 60)
0
VS = ±5V
–10
ΔVO, dm
–PSRR
ΔVS
–20
VO, dm
–30
PSRR (dB)
V–OUT
V+OUT
+PSRR (VS = ±5V, +5V)
–PSRR (VS = ±5V)
+PSRR
–40
–50
–60
–70
V+DIN
5ns
–90
0.1
Figure 43. Large Signal Transient Response, G = +2
1
10
FREQUENCY (MHz)
100
Figure 46. PSRR vs. Frequency
Rev. I | Page 17 of 32
1k
01035-053
1V
01035-049
–80
AD8132
–20
–10
VS = ±5V
VIN, cm = 2V p-p
–30
ΔVOCM = 600mV p-p
ΔVO, dm
ΔVOCM
–20
–30
ΔVO, cm
VOCM CMRR (dB)
ΔVIN, cm
–50
–60
ΔVOCM = 2V p-p
–40
–50
–60
ΔVO, dm
ΔVIN, cm
–70
1
10
100
FREQUENCY (MHz)
1000
–80
01035-055
–80
1
10
100
FREQUENCY (MHz)
Figure 50. VOCM CMRR vs. Frequency
Figure 47. CMRR vs. Frequency (See Figure 61)
6
ΔVO, cm
1k
VS = ±5V
ΔVOCM
3
INPUT VOLTAGE NOISE (nV/√Hz)
ΔVOCM = 600mV p-p
0
ΔVOCM = 2V p-p
–3
–6
–9
100
8nV/√Hz
10
1
10
100
FREQUENCY (MHz)
1000
1
01035-056
–15
10
Figure 48. VOCM Gain Response
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
01035-059
–12
100M
Figure 51. Input Voltage Noise vs. Frequency
1k
INPUT CURRENT NOISE (pA/√Hz)
VS = ±5V
VOCM = –1V TO +1V
VO, cm
400mV
5ns
01035-057
VOCM GAIN (dB)
1000
01035-058
–70
01035-060
CMRR (dB)
–40
100
10
1.8pA/√Hz
1
Figure 49. VOCM Transient Response
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 52. Input Current Noise vs. Frequency
Rev. I | Page 18 of 32
AD8132
0
VIN, sm (1V/DIV)
01035-061
VS = 5V
VIN = 2.5V STEP
G = +2
RF = 1kΩ
RL, dm = 200Ω
5ns
VS = ±5V
11
VS = +5V
9
7
–30
–10
10
30
TEMPERATURE (°C)
50
70
90
01035-062
SUPPLY CURRENT (mA)
13
–50
VS = ±5V
–1.5
–2.0
–20
0
20
40
TEMPERATURE (°C)
60
80
100
Figure 55. Differential Output Offset Voltage vs. Temperature
15
5
–1.0
–2.5
–40
Figure 53. Overdrive Recovery
VS = +5V
–0.5
Figure 54. Supply Current vs. Temperature
Rev. I | Page 19 of 32
01035-063
DIFFERENTIAL OUTPUT OFFSET (mV)
VO, dm (0.5V/DIV)
AD8132
TEST CIRCUITS
CF
RF
348Ω
RG
348Ω
49.9Ω
0.1µF
49.9Ω
499Ω
RL
0.1µF
RL
RF
01035-005
348Ω
CF
G = +1: RF = RG = 348Ω, RL = 249Ω (RL, dm = 498Ω)
G = +2: RF = 1000Ω, RG = 499Ω, RL = 100Ω (RL, dm = 200Ω)
Figure 59. Test Circuit for Output Balance
Figure 56. Basic Test Circuit, G = +1
348Ω
1000Ω
348Ω
499Ω
49.9Ω
0.1µF
200Ω
499Ω
1000Ω
348Ω
24.9Ω
24.9Ω
Figure 60. Test Circuit for Capacitor Load Drive
RF
348Ω
348Ω
499Ω
0.1µF
249Ω
VO, dm
200Ω
49.9Ω
RF
348Ω
NOTES
RESISTORS MATCHED TO 0.01%.
Figure 58. Test Circuit for Various Gains
Figure 61. CMRR Test Circuit
348Ω
LPF
49.9Ω
24.9Ω
2:1 TRANSFORMER
300Ω
348Ω
HPF
ZIN = 50Ω
0.1µF
348Ω
300Ω
348Ω
Figure 62. Harmonic Distortion Test Circuit, G = +1, RL, dm = 800 Ω
1000Ω
49.9Ω
24.9Ω
HPF
ZIN = 50Ω
0.1µF
499Ω
300Ω
1000Ω
Figure 63. Harmonic Distortion Test Circuit, G = +2, RL, dm = 800 Ω
Rev. I | Page 20 of 32
01035-032
LPF
2:1 TRANSFORMER
300Ω
499Ω
VO, cm
249Ω
01035-023
499Ω
348Ω
01035-019
24.9Ω
453Ω
348Ω
Figure 57. Basic Test Circuit, G = +2
49.9Ω
CL
01035-051
24.9Ω
0.1µF
01035-014
49.9Ω
24.9Ω
01035-021
RG
24.9Ω
01035-054
24.9Ω
348Ω
AD8132
OPERATIONAL DESCRIPTION
Table 10. Differential and Common-Mode Gains
DEFINITION OF TERMS
Differential Voltage
It is the difference between two node voltages. For example, the
output differential voltage (or equivalently output differential
mode voltage) is defined as
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Common-Mode Voltage
It is the average of two node voltages. The output commonmode voltage is defined as
CF
RF
AD8132
RG
–IN
RF
RL, dm
VOUT, dm
The gain from VIN, cm to VOUT, dm directly depends on the matching
of the feedback networks. The analogous term for this transfer
function (used in conventional op amps) is common-mode
rejection ratio (CMRR). Therefore, if it has a high CMRR, the
feedback ratios must be well matched.
+OUT
CF
01035-064
VOCM
–DIN
–OUT
+IN
Figure 64. Circuit Definitions
BASIC CIRCUIT OPERATION
One of the more useful and easy to understand ways to use the
AD8132 is to provide two equal ratio feedback networks. To
match the effect of parasitics, comprise these networks of two
equal value feedback resistors (RF) and two equal value gain
resistors (RG). This circuit is shown in Figure 64.
Like a conventional op amp, the AD8132 has two differential
inputs that can be driven with both differential mode input
voltage (VIN, dm) and common-mode input voltage (VIN, cm).
There is another input to consider (VOCM) on the AD8132 that
is not present on conventional op amps. VOCM is completely
separate from the previous inputs.
There are two complementary outputs whose response can be
defined by a differential mode output (VOUT, dm) and a commonmode output (VOUT, cm).
Table 10 shows the gain from any type of input to either type
of output.
VOUT, cm
0 (by design)
0 (by design)
1 (by design)
The gain from VIN, dm to VOUT, cm is 0, and first-order, does not
depend on the ratio matching of the feedback networks. The
common-mode feedback loop within the AD8132 provides a
corrective action to keep this gain term minimized. The term
balance error describes the degree that this gain term differs
from 0.
VOUT, cm = (V+OUT + V−OUT)/2
RG
VOUT, dm
RF/RG
0
0
As listed in Table 10, the differential output (VOUT, dm) is equal to
the differential input voltage (VIN, dm) times RF/RG. In this case, it
does not matter if both differential inputs are driven, or only one
output is driven and the other is tied to a reference voltage, such
as ground. As seen from the two zero entries in the VOUT, dm column,
neither of the common-mode inputs has any effect on this gain.
VOUT, dm = (V+OUT − V−OUT)
+DIN
Input
VIN, dm
VIN, cm
VOCM
The gain from VIN, cm to VOUT, cm is ideally 0 and is first-order
independent of the feedback ratio matching. As in the case of
VIN, dm to VOUT, cm, the common-mode feedback loop keeps this
term minimized.
The gain from VOCM to VOUT, dm is ideally 0 when the feedback ratios
are matched only. The amount of differential output signal that is
created by varying VOCM is related to the degree of mismatch in the
feedback networks.
VOCM controls the output common-mode voltage VOUT, cm with a
unity-gain transfer function. With equal ratio feedback networks
(as previously assumed), its effect on each output is the same,
that is the gain from VOCM to VOUT, dm is 0. If not driven, the
output common-mode voltage is set with an internal voltage
divider to a level that is nominally midsupply. It is recommended
that a 0.1 μF bypass capacitor be connected to VOCM.
When unequal feedback ratios are used, the two gains associated
with VOUT, dm become nonzero. This significantly complicates the
mathematical analysis along with any intuitive understanding of
how the part operates.
Rev. I | Page 21 of 32
AD8132
THEORY OF OPERATION
The AD8132 differs from conventional op amps by the external
presence of an additional input and output. The additional
input, VOCM, controls the output common-mode voltage. The
additional output is the analog complement of the single output
of a conventional op amp. For its operation, the AD8132 uses two
feedback loops as compared to the single loop of conventional
op amps. Although this provides significant freedom to create
various novel circuits, basic op amp theory can still be used to
analyze the operation.
One of the feedback loops controls the output common-mode
voltage, VOUT, cm. Its input is VOCM (Pin 2) and the output is the
common mode, or average voltage, of the two differential outputs
(+OUT and −OUT). The gain of this circuit is internally set to
unity. When the AD8132 is operating in its linear region, this
establishes one of the operational constraints: VOUT, cm = VOCM.
The second feedback loop controls the differential operation.
Similar to an op amp, the gain and gain shaping of the transfer
function can be controlled by adding passive feedback networks.
However, only one feedback network is required to close the
loop and fully constrain the operation, but depending on the
function desired, two feedback networks can be used. This is
possible because there are two outputs that are each inverted
with respect to the differential inputs.
GENERAL USAGE OF THE AD8132
Several assumptions are made here for a first-order analysis; they
are the typical assumptions used for the analysis of op amps.
•
The input bias currents are sufficiently small so they can be
neglected.
•
The output impedances are arbitrarily low.
•
The open-loop gain is arbitrarily large and drives the
amplifier to a state where the input differential voltage is
effectively 0.
•
Offset voltages are assumed to be 0.
For each feedback network, a feedback factor can be defined as
the fraction of the output signal that is fed back to the opposite
sign input. These terms are
β1 = RG1/(RG1 + RF1)
β2 = RG2/(RG2 + RF2)
The feedback factor, β1, is for the side that is driven, and the
feedback factor, β2, is for the side that is tied to a reference
voltage (ground). Note that each feedback factor can vary
anywhere between 0 and 1.
A single-ended-to-differential gain equation can be derived
(this is true for all values of β1 and β2) from
G=
2 (1 − β1)
(β1 + β2 )
This expression is not very intuitive, but some further examples
can provide better understanding of its implications. One
observation that can be made immediately is that a tolerance
error in β1 does not have the same effect on gain as the same
tolerance error in β2.
DIFFERENTIAL AMPLIFIER WITHOUT RESISTORS
(HIGH INPUT IMPEDANCE INVERTING AMPLIFIER)
The simplest closed-loop circuit that can be made does not
require any resistors and is shown in Figure 70. In this circuit,
β1 is equal to 0, and β2 is equal to 1. The gain is equal to 2.
A more intuitive method to figure the gain is by simple inspection.
+OUT is connected to −IN, whose voltage is equal to the voltage at
+IN under equilibrium conditions. Therefore, +VOUT is equal to
VIN, and there is unity gain in this path. Because −OUT has to
swing in the opposite direction from +OUT due to the commonmode constraint, its effect doubles the output signal and
produces a gain of 2.
One useful function that this circuit provides is a high input
impedance inverter. If +OUT is ignored, there is a unity-gain,
high input impedance amplifier formed from +IN to −OUT.
Most traditional op amp inverters have relatively low input
impedances, unless they are buffered with another amplifier.
Though it is possible to operate the AD8132 with a purely
differential input, many of its applications call for a circuit
that has a single-ended input with a differential output.
For a single-ended-to-differential circuit, the RG of the input that
is not driven is tied to a reference voltage or to ground. Additional
conditions are discussed in the following sections. In addition,
the voltage at VOCM, and therefore VOUT, cm, is assumed to be ground.
Figure 67 shows a generalized schematic of such a circuit using an
AD8132 with two feedback paths.
VOCM is assumed to be at midsupply. Because there is still the
constraint that +VOUT must equal VIN, changing the VOCM voltage
does not change +VOUT (equal to VIN). Therefore, the effect of
changing VOCM must show up at −OUT.
For example, if VOCM is raised by 1 V, then −VOUT must increase
by 2 V. This makes VOUT, cm also increase by 1 V because it is defined
as the average of the two differential output voltages. This means
that the gain from VOCM to the differential output is 2.
Rev. I | Page 22 of 32
AD8132
OTHER β2 = 1 CIRCUITS
The preceding simple configuration with β2 = 1 and its gain of 2
is the highest gain circuit that can be made under this condition.
Because β1 was equal to 0, only higher β1 values are possible.
The circuits with higher values of β1 have gains lower than 2.
However, circuits with β1 equal to 1 are not practical because
they have no effective input and result in a gain of 0.
To increase β1 from 0, it is necessary to add two resistors in a feedback network. A generalized circuit that has β1 with a value higher
than 0 is shown in Figure 69. A couple of different convenient
gains that can be created are a gain of 1, when β1 is equal to 1/3,
and a gain of 0.5, when β1 equals 0.6.
With β2 equal to 1 in these circuits, VOCM serves as the reference voltage that measures the input voltage and the individual
output voltages. In general, when VOCM is varied in circuits with
unmatched feedback networks, a differential output signal is
generated that is proportional to the applied VOCM voltage.
VARYING β2
Though the β2 = 1 circuit sets β2 to 1, another class of simple
circuits can be made that sets β2 equal to 0. This means that
there is no feedback from +OUT to −IN. This class of circuits
is very similar to a conventional inverting op amp. However,
the AD8132 circuits have an additional output and commonmode input that can be analyzed separately (see Figure 71).
With −IN connected to ground, +IN becomes a virtual ground
in the sense that the term is used for conventional op amps. Both
inputs must maintain the same voltage for equilibrium operation;
therefore, if one is set to ground, the other is driven to ground.
The input impedance can also be seen to be equal to RG, just as
in a conventional op amp.
In this case, however, the positive input and negative output are
used for the feedback network. Because a conventional op amp
does not have a negative output, only its inverting input can be
used for the feedback network. The AD8132 is symmetrical,
therefore, the feedback network on either side can be used to
produce the same results.
Because +IN is a summing junction, by an analogy to conventional op amps, the gain from VIN to −OUT is −RF/RG. This holds
true regardless of the voltage on VOCM, and because +OUT
moves the same amount in the opposite direction from −OUT,
the overall gain is −2(RF/RG).
VOCM still governs VOUT, cm; therefore, +OUT must be the only
output that moves when VOCM is varied. Because VOUT, cm is the
average of the two outputs, +OUT must move twice as far, and in
the same direction as VOCM, to create the proper VOUT, cm. Therefore,
the gain from VOCM to +OUT must be 2.
With β2 equal to 0 in these circuits, the gain can theoretically be
set to any value from close to 0 to infinity, just as it can with a
conventional op amp in the inverting mode. However, practical
real-world limitations and parasitics limit the range of acceptable
gain to more modest values.
β1 = 0
There is yet another class of circuits where there is no feedback
from −OUT to +IN. This is the case where β1 = 0. The differential
amplifier without a resistor described in the Differential Amplifier
Without Resistors (High Input Impedance Inverting Amplifier)
section meets this condition, but it was presented only with the
condition that β2 = 1. Recall that this circuit had a gain equal to 2.
If β2 decreases in this circuit from unity, a smaller part of +VOUT
is fed back to −IN and the gain increases (see Figure 68). This
circuit is very similar to a noninverting op amp configuration,
except for the presence of the additional complementary output.
Therefore, the overall gain is twice that of a noninverting op
amp or 2 × (1 + RF2/RG2) or 2 × (1/β2).
Once again, varying VOCM does not affect both outputs in the
same way; therefore, in addition to varying VOUT, cm with unity
gain, there is also an effect on VOUT, dm by changing VOCM.
ESTIMATING THE OUTPUT NOISE VOLTAGE
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input-referred terms, at +IN and −IN, by the
circuit noise gain. The noise gain is defined as
⎛R
GN = 1 + ⎜⎜ F
⎝ RG
⎞
⎟
⎟
⎠
To compute the total output-referred noise for the circuit of
Figure 64, consideration must be given to the contribution of
resistors, RF and RG. See Table 11 for estimated output noise
voltage densities at various closed-loop gains.
Table 11. Recommended Resistor Values and Noise
Performance for Specific Gains
Gain
1
2
5
10
Rev. I | Page 23 of 32
RG (Ω)
499
499
499
499
RF (Ω)
499
1.0 k
2.49 k
4.99 k
Bandwidth
−3 dB (MHz)
360
160
65
20
Output
Noise
AD8132
Only
(nV/√Hz)
16
24.1
48.4
88.9
Output
Noise
AD8132
+ RG , RF
(nV/√Hz)
17
26.1
53.3
98.6
AD8132
When using the AD8132 in gain configurations where β1 ≠ β2,
differential output noise appears due to input-referred voltage
noise in the VOCM circuitry according to the following formula:
⎡ β1 − β2 ⎤
VOND = 2 VNOCM ⎢
⎥
⎢⎣ β1 + β2 ⎥⎦
In cases where more accurate control of the output common-mode
level is required, it is a best practice that an external source or
resistor divider (with RSOURCE < 10 kΩ) be used. The output
common-mode offset values in the Specifications section assume
the VOCM input is driven by a low impedance voltage source.
DRIVING A CAPACITIVE LOAD
where:
VOND is the output differential noise.
VNOCM is the input-referred voltage noise on VOCM.
CALCULATING INPUT IMPEDANCE OF THE
APPLICATION CIRCUIT
The effective input impedance of a circuit, such as that in Figure 64,
at +DIN and −DIN, depends on whether the amplifier is being
driven by a single-ended or differential signal source. For balanced
differential input signals, the input impedance (RIN, dm) between
the inputs (+DIN and −DIN) is simply
A purely capacitive load can react with the pin and bond wire
inductance of the AD8132, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to place a
small capacitor across each of the feedback resistors. The added
capacitance must be small to avoid destabilizing the amplifier. An
alternative technique is to place a small resistor in series with
the amplifier outputs, as shown in Figure 60.
OPEN-LOOP GAIN AND PHASE
Open-loop gain and phase plots are shown in Figure 65 and
Figure 66.
RIN, dm = 2 × RG
60
The circuit input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor, RG.
40
30
20
10
0
–20
0.1
1
10
100
1000
FREQUENCY (MHz)
01035-083
–10
Figure 65. Open-Loop Gain vs. Frequency
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
40
20
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the AD8132 is internally biased at a voltage
approximately equal to the midsupply point (average value of the
voltage on V+ and V−). Relying on this internal bias results in an
output common-mode voltage that is within approximately
100 mV of the expected value.
OPEN-LOOP PHASE (Degrees)
The AD8132 is optimized for level-shifting, ground-referenced
input signals. For a single-ended input, this implies that the voltage
at −DIN in Figure 64 is 0 V when the negative power supply
voltage (at V−) of the amplifier is also set to 0 V.
RL, dm = 2kΩ
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
0.1
1
10
100
FREQUENCY (MHz)
Figure 66. Open-Loop Phase vs. Frequency
Rev. I | Page 24 of 32
1000
01035-084
RIN,dm
⎛
⎞
⎜
⎟
R
G
⎜
⎟
=
RF
⎜
⎟
1
−
⎜
2
×
(RG + RF ) ⎟⎠
⎝
RL, dm = 2kΩ
50
OPEN-LOOP GAIN (dB)
In the case of a single-ended input signal (for example, if −DIN
is grounded and the input signal is applied to +DIN), the input
impedance becomes
AD8132
LAYOUT, GROUNDING, AND BYPASSING
CIRCUITS
Keep the signal routing short and direct to avoid parasitic effects.
Wherever there are complementary signals, a symmetrical
layout with matched lengths must be provided to the extent
possible to maximize the balance performance. When running
differential signals over a long distance, place the traces on
the PCB close together or twist together any differential wiring
to minimize the area of the loop that is formed. This reduces
the radiated energy and makes the circuit less susceptible to
interference.
01035-065
RG2
RF2
Figure 67. Typical Four-Resistor Feedback Circuit
+
VIN
RG2
RF2
01035-066
Bypass the power supply pins as close as possible to the device
to the nearby ground plane and use good high frequency ceramic
chip capacitors. Do this bypassing with a capacitance value
of 0.01 μF to 0.1 μF for each supply. Farther away, provide low
frequency bypassing with 10 μF tantalum capacitors from each
supply to ground.
+
Figure 68. Typical Circuit with β1 = 0
RF1
RG1
+
01035-067
The first requirement is a good solid ground plane that covers as
much of the board area around the AD8132 as possible. The only
exception to this is that the two input pins (Pin 1 and Pin 8) are
kept a few millimeters from the ground plane and that ground
be removed from inner layers and the opposite side of the board
under the input pins. This minimizes the stray capacitance on
these nodes and helps preserve the gain flatness vs. the frequency.
RF1
RG1
Figure 69. Typical Circuit with β2 = 1
VIN
+
01035-068
As a high speed part, the AD8132 is sensitive to the printed
circuit board (PCB) environment in which it operates. Realizing
its superior specifications requires attention to various details of
good high speed PCB design.
Figure 70. G = +2 Circuit with β1 = 0, Without Resistors
RF1
+
01035-069
VIN
RG1
Figure 71. Typical Circuit with β2 = 0
Rev. I | Page 25 of 32
AD8132
APPLICATIONS INFORMATION
10
ANALOG-TO-DIGITAL DRIVER
fS = 40MHz
fIN = 2.5MHz
FUND
0
Many of the newer high speed ADCs are single supply and have
differential inputs. Thus, the driver for these devices is able to
convert from a single-ended signal to a differential signal and
provide output common-mode level shifting in addition to
having low distortion and noise. The AD8132 conveniently
performs these functions when driving the AD9203, a 10-bit,
40 MSPS ADC.
–10
–20
OUTPUT (dBc)
–30
–40
–50
–60
–70
2ND
5TH
–80
3RD
–90
In Figure 73, a 1 V p-p signal drives the input of an AD8132
configured for unity gain. Both the AD8132 and the AD9203 are
powered from a single 3 V supply. A voltage divider biases VOCM
at midsupply and in turn drives VOUT, cm to half of the supply
voltage. This is within the common-mode range of the AD9203.
6TH
4TH
9TH 8TH
7TH
–100
0
2.5
5.0
7.5
10.0
12.5
15.0
INPUT FREQUENCY (MHz)
17.5
20.0
01035-071
–110
–120
Figure 72. FTT Response for AD8132 Driving AD9203
Between the ADC and the driver is a 1-pole, differential filter that
helps to filter some of the noise and assists the switched-capacitor
inputs of the ADC. Each of the ADC inputs is driven by a 0.5 V p-p
signal that ranges from 1.25 V dc to 1.75 V dc. Figure 72 is an
FFT plot of the performance of the circuit when running at a
clock rate of 40 MSPS and an input frequency of 2.5 MHz.
BALANCED CABLE DRIVER
When driving a twisted pair cable, it is desirable to drive only
a pure differential signal onto the line. If the signal is purely
differential (that is, fully balanced), and the transmission line is
twisted and balanced, there is minimum radiation of any signal.
The complementary electrical fields are confined mostly to
the space between the two twisted conductors and does not
significantly radiate out from the cable. The current in the cable
creates magnetic fields that radiate to some degree. However, the
amount of radiation is mitigated by the twists, because for
each twist, the two adjacent twists have an opposite polarity
magnetic field. If the twist pitch is tight enough, these small
magnetic field loops contain most of the magnetic flux, and
the magnetic farfield strength is negligible.
3V
3V
10kΩ
0.1µF
1V p-p
10µF
348Ω
10kΩ
60.4Ω
25
3
8
20pF
5
49.9Ω
0.1µF
2
4
348Ω
6
28
2
AVDD
DRVDD
AINN
DIGITAL
OUTPUTS
AD9203
AD8132
1
0.1µF
0.1µF
348Ω
24.9Ω
+
20pF
60.4Ω
348Ω
AINP
26
AVSS
DRVSS
27
1
Figure 73. AD8132 Driving AD9203, a 10-Bit, 40 MSPS ADC
Rev. I | Page 26 of 32
01035-070
3V
AD8132
+5V
0.1µF
+
+5V
10µF
1kΩ
499Ω
1
AD8132
0.1µF
100Ω
49.9Ω
523Ω
+
AD830
2
TWISTED
PAIR
7
3
VOUT
4
1kΩ
10µF
10µF
0.1µF
5
–5V
10µF
0.1µF
+
01035-072
50Ω
SOURCE
49.9Ω
49.9Ω
+
0.1µF
–5V
Figure 74. Balanced Line Driver and Receiver Using AD8132 and AD830
10
0
–10
–60
–70
–80
LOW-PASS DIFFERENTIAL FILTER
Similar to an op amp, various types of active filters can be
created with the AD8132. These can have single-ended inputs
and differential outputs that can provide an antialias function
when driving a differential ADC.
2.15kΩ
2kΩ
VIN
VOUT
01035-073
499Ω
33pF
549Ω
200pF
953Ω
2kΩ
VOUT
200pF
33pF
549Ω
Figure 77. 1 MHz, 3-Pole Differential Output,
Low-Pass, Multiple Feedback Filter
49.9Ω
24.9Ω
100pF
100pF
953Ω
2.15kΩ
49.9Ω
100Ω
49.9Ω
24.9Ω
499Ω
249Ω
249Ω
10pF
1000
10
100
FREQUENCY (MHz)
1
01035-075
By lowering the impedance of the RG component of the feedback
network at a higher frequency, the gain can be increased at a
high frequency. Figure 75 shows the gain of a two-line driver
that has its RG resistors shunted by 10 pF capacitors. The effect
of this is shown in the frequency response plot of Figure 76.
49.9Ω
–40
Figure 76. Frequency Response for Transmit Boost Circuit
Any length of transmission line attenuates the signals it carries.
This effect is worse at higher frequencies than at lower frequencies.
One way to compensate for this is to provide an equalizer circuit
that boosts the higher frequencies in the transmitter circuit, so
that at the receive end of the cable, the attenuation effects are
diminished.
VIN
–30
–50
TRANSMIT EQUALIZER
10pF
–20
01035-074
The common-mode feedback loop in the AD8132 helps to
minimize the amount of common-mode voltage at the output
and can, therefore, be used to create a well-balanced differential
line driver. Figure 74 shows an application that uses an AD8132
as a balanced line driver and an AD830 as a differential receiver
configured for unity gain. This circuit was operated with 10 meters
of Category 5 cable.
20
VOUT/VIN (dB)
Any imbalance in the differential drive signal appears as a
common-mode signal on the cable. This is the equivalent of
a single wire that is driven with the common-mode signal. In
this case, the wire acts as an antenna and radiates. Therefore, to
minimize radiation when driving differential twisted pair cables,
make sure the differential drive signal is well balanced.
Figure 77 is a schematic of a low-pass, multiple feedback filter.
The active section contains two poles, and an additional pole
is added at the output. The filter was designed to have a −3 dB
frequency of 1 MHz.
Figure 75. Frequency Boost Circuit
Rev. I | Page 27 of 32
AD8132
The actual −3 dB frequency was measured to be 1.12 MHz, as
shown in Figure 78.
10
0
–10
VOUT/VIN (dB)
–20
If the receive end common-mode voltage is set to ground, it is
well defined at the receive end. Any common-mode signal that
is picked up over the cable length due to noise appears at the
transmit end and must be absorbed by the transmitter. Thus, it is
important that the transmitter have adequate common-mode
output range to absorb the full amplitude of the common-mode
signal coupled onto the cable and therefore prevent clipping.
–30
Another way to look at this is that the circuit performs what is
sometimes called a transformer action. One main difference is
that the AD8132 passes dc while transformers do not.
–40
–50
–60
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 78. Frequency Response of 1 MHz Low-Pass Filter
HIGH COMMON-MODE OUTPUT IMPEDANCE
AMPLIFIER
Changing the connection to VOCM (Pin 2) can change the commonmode from low impedance to high impedance. If VOCM is actively
set to a particular voltage, the AD8132 tries to force VOUT, cm to
the same voltage with a relatively low output impedance. All the
previous analysis assumed that this output impedance is arbitrarily
low enough to drive the load condition in the circuit.
However, some applications benefit from high common-mode
output impedance. This is accomplished with the circuit shown
in Figure 79.
RF
348Ω
RG
348Ω
VOCM
Figure 80. Transformer with Low Output Impedance Secondary Set at VOCM
If the center tap of the secondary of a transformer is allowed to
float as shown in Figure 81 (or if there is no center tap), the
transformer has high common-mode output impedance. This
means that the common mode of the secondary is determined
by what it is connected to and not by anything to do with the
transformer itself.
10Ω
RG
348Ω
NC
1kΩ
49.9Ω
1kΩ
49.9Ω
VDIFF
01035-078
–90
10k
01035-076
–80
A transformer can also be easily configured to have either a high or
low common-mode output impedance. If the transformers center
tap is connected to a solid voltage reference, it sets the commonmode voltage on the secondary side of the transformer. In this case,
if one of the differential outputs is grounded, the other output has
half of the differential output signal. This keeps the common-mode
voltage at ground, where it is required to be due to the center tap
connection. This is analogous to the AD8132 operating with a low
output impedance common mode (see Figure 80).
VDIFF
01035-079
–70
Figure 81. Transformer with High Output Impedance Secondary
10Ω
01035-077
RF
348Ω
Figure 79. High Common-Mode, Output Impedance, Differential Amplifier
VOCM is driven by a resistor divider that measures the output
common-mode voltage. Thus, the common-mode output voltage
takes on the value that is set by the driven circuit. In this case,
it comes from the center point of the termination at the receive
end of a 10 meter length of Category 5 twisted pair cable.
If one of the differential ends of the transformer is grounded,
the other end swings with the full output voltage. This means
that the common mode of the output voltage is one-half of the
differential output voltage. However, this shows that the common
mode is not forced via low impedance to a given voltage. The
common-mode output voltage can be easily changed to any voltage
through its other output terminals.
The AD8132 can exhibit the same performance when one of
the outputs in Figure 79 is grounded. The other output swings
at the full differential output voltage. The common-mode signal
is measured by the voltage divider across the outputs and input
to VOCM. This, then, drives VOUT, cm to the same level. At higher
frequencies, it is important to minimize the capacitance on
the VOCM node; otherwise, phase shifts can compromise the
performance. The voltage divider resistances can also be lowered
for better frequency response.
Rev. I | Page 28 of 32
AD8132
FULL-WAVE RECTIFIER
The balanced outputs of the AD8132, along with a couple of
Schottky diodes, can create a very high speed, full-wave rectifier.
Such circuits are useful for measuring ac voltages and other
computational tasks.
If there is not enough forward bias (VOUT, cm too low), the lower
sharp cusps of the full-wave rectified output waveform are rounded
off. In addition, as the frequency increases, there tends to be some
rounding of the lower cusps. The forward bias can be increased
to yield sharper cusps at higher frequencies.
Figure 82 shows the configuration of such a circuit. Each of the
AD8132 outputs drives the anode of an HP2835 Schottky diode.
These Schottky diodes were chosen for their high speed operation.
At lower frequencies (approximately lower than 10 MHz), a silicon
signal diode, such as a 1N4148, can be used. The cathodes of the
two diodes are connected together, and this output node is
connected to ground by a 100 Ω resistor.
There is not a reliable, entirely quantifiable, means to measure
the performance of a full-wave rectifier. Because the ideal
waveform has periodic sharp discontinuities, it has (mostly
even) harmonics that have no upper bound on the frequency.
However, for a practical circuit, as the frequency increases, the
higher harmonics become attenuated and the sharp cusps that
are present at low frequencies become significantly rounded.
+5V
RG1
348Ω
RT1
49.9Ω
RT2
24.9Ω
RG2
348Ω
+5V
10kΩ
HP2835
RF2
348Ω
RL
100Ω
–5V
CR1
Sometimes a second harmonic generator is useful for creating a
clock to oversample a DAC by a factor of two. If the output of
this circuit is run through a low-pass filter, it can be used as a
second harmonic generator.
VOUT
01035-080
VIN
When running the circuit at a frequency up to 300 MHz, though it
stays functional, the major harmonic that remains in the output
is the second. This looks like a sine wave at 600 MHz. Figure 83 is
an oscilloscope plot of the output when driven by a 100 MHz,
2.5 V p-p input.
RF1
348Ω
Figure 82. Full-Wave Rectifier
1V
One advantage of this circuit is that the feedback loop is never
momentarily opened while the diodes reverse their polarity within
the loop. This scheme is sometimes used for full-wave rectifiers
that use conventional op amps. These conventional circuits do
not work well at frequencies above approximately 1 MHz.
100mV
2ns
01035-081
Operate the diodes such that they are slightly forward-biased
when the differential output voltage is zero. For the Schottky
diodes, this is approximately 400 mV. The forward biasing is
conveniently adjusted by CR1, which, in this circuit, raises and
lowers VOUT, cm without creating a differential output voltage.
Figure 83. Full-Wave Rectifier Response with 100 MHz Input
AUTOMOTIVE PRODUCTS
The AD8132W is qualified per the AEC-Q100 for use in
automotive applications. Custom variants of this product may
be available to meet stringent automotive performance and
quality requirements.
Rev. I | Page 29 of 32
AD8132
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 84. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
3.20
3.00
2.80
8
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.70
0.55
0.40
0.23
0.13
COMPLIANT TO JEDEC STANDARDS MO-187-AA
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 85. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8132AR
AD8132AR-REEL
AD8132AR-REEL7
AD8132ARZ 1
AD8132ARZ-RL1
AD8132ARZ-R71
AD8132ARM
AD8132ARM-REEL
AD8132ARM-REEL7
AD8132ARMZ1
AD8132ARMZ-REEL1
AD8132ARMZ-REEL71
AD8132WARMZ-R71, 2
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.
Automotive qualified product.
Rev. I | Page 30 of 32
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
Ordering Quantity
2,500
1,000
2,500
1,000
HMA
HMA
HMA
HMA#
HMA#
HMA#
H14
3,000
1,000
3,000
1,000
1,000
AD8132
NOTES
Rev. I | Page 31 of 32
AD8132
NOTES
©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01035–0–9/09(I)
Rev. I | Page 32 of 32