PRELIMINARY Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER GENERAL DESCRIPTION FEATURES The ICS889874 is a high speed 1:2 Differentialto-LVPECL Buffer/Divider and is a member of HiPerClockS™ the HiPerClockS ™ family of high performance clock solutions from ICS. The ICS889874 has a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output divider, which allows the device to be used as either a 1:2 fanout buffer or frequency divider. The clock input has internal termination resistors, allowing it to interface with several differential signal types while minimizing the number of required external components. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards. • 2 LVPECL outputs ICS • Frequency divide select options: ÷ 1, ÷ 2, ÷4, ÷8, ÷16 • IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML • Output frequency: > 2.5GHz • Output skew: 5ps (typical) • Part-to-part skew: TBD • Additive jitter, RMS: <0.03ps (design target) • Supply voltage range: (LVPECL), 2.375V to 3.465V Supply voltage range: (ECL), -3.465V to -2.375V • -40°C to 85°C ambient operating temperature • Pin compatible with SY89874U S2 0 nQ0 1 IN 00 01 10 11 VT nIN Q1 ÷2 ÷4 ÷8 ÷16 nQ1 VEE VCC IN nQ0 2 11 VT Q1 3 10 VREF_AC nQ1 4 9 5 6 7 8 nRESET Q0 16 15 14 13 12 VCC Enable MUX 1 nc Enable FF Q0 S2 nRESET S1 PIN ASSIGNMENT S0 BLOCK DIAGRAM nIN ICS889874 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View S0 Decoder S1 VREF_AC The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 889874AK www.icst.com/products/hiperclocks.html 1 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVPECL / ECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL / ECL interface levels. 5, 15, 16 S2, S1, S0 Input Pullup Select pins. LVCMOS/LVTTL interface levels. Pullup Positive supply pins. Synchronizing enable/disable pin. When LOW, resets the divider. When HIGH, unconnected. Input threshold is VCC/2V. Includes a 37kΩ pull-up resistor. LVTTL / LVCMOS interface levels. Inver ting differential LVPECL clock input. 6 nc Unused 7, 14 VCC Power No connect. 8 nRESET Input 9 nIN Input 10 VREF_AC Output 11 VT Input Termination input. 12 IN Input Non-inver ting LVPECL differential clock input. Reference voltage for AC-coupled applications. Power Negative supply pin. 13 VEE NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLUP Input Pullup Resistor 889874AK Test Conditions Minimum Typical 37 www.icst.com/products/hiperclocks.html 2 Maximum Units KΩ REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs nRESET Selected Source Q0, Q1 nQ0, nQ1 0 IN, nIN Disabled; LOW Disabled; HIGH 1 IN, nIN Enabled Enabled NOTE: After nRESET switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. VCC/2 nRESET tRR IN VIN nIN tPD nQ VOUT Swing Q FIGURE 1. nRESET TIMING DIAGRAM (WHEN S2 = 1) TABLE 3B. TRUTH TABLE Inputs Outputs nRESET S2 S1 S0 1 0 X X 1 1 0 0 Reference Clock ÷2 1 1 0 1 Reference Clock ÷4 Reference Clock ÷8 1 1 1 0 1 1 1 1 Reference Clock (pass through) Reference Clock ÷16 Q = LOW, nQ = HIGH 0 1 X X Clock Disable; (NOTE 1) Q = LOW, nQ = HIGH 0 0 X X Clock Disable; (NOTE 1) NOTE 1: Reset/Disable function is asser ted on the next clock input (IN/nIN) high-to-low transition. 889874AK www.icst.com/products/hiperclocks.html 3 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC -0.5V to +4.0V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those 50mA 100mA Input Current IN, nIN ±50mA VT Current, IVT ±100mA VREF_AC Sink/Source, IVREF_AC ± 0.5mA listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 51.5°C/W (0 lfpm) (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±10% OR 2.5V±5%; TA = -40°C TO 85°C Symbol Parameter VCC Positive Supply Voltage I EE Power Supply Current Test Conditions Minimum Typical Maximum Units 2.375 3.3 3.63 V 50 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V±10% OR 2.5V±5%; TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage Test Conditions VIL Input Low Voltage IIH Input High Current VCC = VIN = 3.63V IIL Input Low Current VCC = 3.63V, VIN = 0V Minimum Typical Maximum Units 2 VCC + 0.3 V 0 0.8 V -125 20 µA -300 µA TABLE 4C. DC CHARACTERISTICS, VCC = 3.3V±10% OR 2.5V±5%; TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum RIN Differential Input Resistance (IN, nIN) VIH Input High Voltage (IN, nIN) VIL Input Low Voltage (IN, nIN) VIN Input Voltage Swing VDIFF_IN Differential Input Voltage Swing 0.3 IIN Input Current VREF_AC Bias Voltage 889874AK Typical Maximum Ω 10 0 1.2 VCC V 0 VCC - 0.15 V 0.15 2.8 V V (IN, nIN) 45 VCC - 1.35 www.icst.com/products/hiperclocks.html 4 Units mA V REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±10% OR 2.5V±5%; TA = -40°C TO 85°C Symbol Parameter Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC - 1.005 mV VOL Output Low Voltage; NOTE 1 VCC - 1.78 mV VOUT Output Voltage Swing 800 mV VDIFF_OUT Differential Output Voltage Swing 1.60 V Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±10% OR 2.5V±5%; TA = -40°C TO 85°C Symbol fMAX Parameter Maximum Output Frequency Maximum Input Frequency Minimum 2 Typical Maximum Units GHz ÷ 2, ÷4, ÷8, ÷16 2 GHz Input Swing: < 400mV 725 ps Input Swing: ≥ 400mV 725 ps 5 ps TBD ps <0.03 ps TBD ps 180 ps EN to IN, nIN TBD ps EN to IN, nIN TBD ps t PD Propagation Delay, (Differential); NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(pp) tRR Par t-to-Par t Skew; NOTE 3, 4 Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Reset Recover y Time tR/tF Output Rise/Fall Time tS Clock Enable Setup Time tH Clock Enable Hold Time tjit Condition Output Swing ≥ 450mV 20% to 80% All parameters characterized at ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 889874AK www.icst.com/products/hiperclocks.html 5 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER PARAMETER MEASUREMENT INFORMATION 2V VCC Qx VCC SCOPE nIN LVPECL V Cross Points IN V IH IN nQx VEE V IL V EE -0.375V to -1.63V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nIN 80% 80% IN VSW I N G Clock Outputs 20% 20% nQ0, nQ1 tF tR Q0, Q1 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nIN IN nRESET t HOLD VDIFF_IN, VDIFF_OUT 1600mV (typical) t SET-UP SETUP & HOLD TIME 889874AK VIN, VOUT 800mV (typical) SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING www.icst.com/products/hiperclocks.html 6 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER APPLICATION INFORMATION TERMINATION FOR 3.3V LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o VCC - 2V Zo = 50Ω RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 889874AK FIN 50Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V VCC=2.5V 2.5V 2.5V VCC=2.5V Zo = 50 Ohm R1 250 R3 250 + Zo = 50 Ohm Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er - R1 50 2,5V LVPECL Driv er R2 62.5 R2 50 R4 62.5 R3 18 FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm - 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE 889874AK www.icst.com/products/hiperclocks.html 8 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. 2.5V LVPECL INPUT WITH ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Ω TERMINATIONS INTERFACE BUILT-IN 50Ω The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both V SWING and V OH must meet the V PP and V CMR input requirements.Figures 4A to 4D show interface examples for the HiPerClockS IN/nIN input with built-in 50Ω terminations driven 3.3V or 2.5V by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm VT Zo = 50 Ohm nIN LVDS nIN Receiver With Built-In 50 Ohm R1 18 FIGURE 4A. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVDS DRIVER BUILT-IN 50Ω FIGURE 4B. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVPECL DRIVER BUILT-IN 50Ω 2.5V 2.5V Receiver With Built-In 50 Ohm 2.5V LVPECL 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN CML - Open Collector Zo = 50 Ohm VT nIN Receiver With Built-In 50 Ohm CML - Built-in 50 Ohm Pull-up FIGURE 4C. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN OPEN COLLECTOR BUILT-IN 50Ω CML DRIVER Receiver With Built-In 50 Ohm FIGURE 4D. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY A CML DRIVER BUILT-IN 50Ω Ω PULLUP WITH BUILT-IN 50Ω 2.5V 2.5V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm VT nIN R2 SSTL 25 Receiver With Built-In 50Ω FIGURE 4E. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN SSTL DRIVER BUILT-IN 50Ω 889874AK www.icst.com/products/hiperclocks.html 9 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. 3.3V LVPECL INPUT WITH ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER BUILT-IN 50Ω Ω TERMINATIONS INTERFACE The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS IN/nIN input with built-in 50Ω terminations driven 3.3V by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V Zo = 50 Ohm Zo = 50 Ohm IN IN Zo = 50 Ohm VT nIN LVDS nIN Receiver With Built-In 50 Ohm R1 50 FIGURE 5B. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVPECL DRIVER BUILT-IN 50Ω 3.3V 3.3V 3.3V Zo = 50 Ohm Zo = 50 Ohm IN Zo = 50 Ohm Receiver With Built-In 50 Ohm LVPECL FIGURE 5A. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVDS DRIVER BUILT-IN 50Ω 3.3V VT Zo = 50 Ohm IN VT Zo = 50 Ohm nIN nIN Receiver With Built-In 50 Ohm CML- Open Collector CML- Built-in 50 Ohm Pull-Up Receiver With Built-In 50 Ohm FIGURE 5D. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY A CML DRIVER BUILT-IN 50Ω Ω PULLUP WITH BUILT-IN 50Ω FIGURE 5C. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY A CML DRIVER BUILT-IN 50Ω WITH OPEN COLLECTOR 3.3V VT 3.3V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm VT nIN SSTL R2 25 Receiver With Built-In 50 Ohm FIGURE 5E. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN SSTL DRIVER BUILT-IN 50Ω 889874AK www.icst.com/products/hiperclocks.html 10 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. 3.3V DIFFERENTIAL INPUT WITH ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER Ω TERMINATION UNUSED INPUT HANDLING BUILT-IN 50Ω To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 6. 3.3V 3.3V R1 1K IN VT nIN Receiver with Built-In 50 Ohm R2 1K FIGURE 6. UNUSED INPUT HANDLING 2.5V DIFFERENTIAL INPUT WITH BUILT-IN 50Ω Ω TERMINATION UNUSED INPUT HANDLING To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 7. 2.5V 2.5V R1 680 IN VT nIN Receiver with Built-In 50 Ohm R2 680 FIGURE 7. UNUSED INPUT HANDLING 889874AK www.icst.com/products/hiperclocks.html 11 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN θJA 0 Air Flow (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W TRANSISTOR COUNT The transistor count for ICS889874 is: 326 889874AK www.icst.com/products/hiperclocks.html 12 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - K SUFFIX FOR ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER 16 LEAD VFQFN TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 16 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 4 NE 4 3.0 D D2 0.25 1.25 3.0 E E2 0.25 1.25 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 889874AK www.icst.com/products/hiperclocks.html 13 REV. A MAY 19, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS889874 1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS889874AK 874A 16 Lead VFQFN 120 per tube -40°C to 85°C ICS889874AKT 874A 16 Lead VFQFN on Tape and Reel 3500 -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 889874AK www.icst.com/products/hiperclocks.html 14 REV. A MAY 19, 2004