NSC ADC16061 Self-calibrating 16-bit, 2.5 msps, 390 mw a/d converter Datasheet

ADC16061
Self-Calibrating 16-Bit, 2.5 MSPS, 390 mW A/D Converter
General Description
Features
The ADC16061 is a self-calibrating 16-bit, 2.5 Megasample
per second analog to digital converter. It operates on a single
+5V supply, consuming just 390mW (typical).
The ADC16061 provides an easy and affordable upgrade
from 12 bit and 14 bit converters. The ADC16061 may also
be used to replace many hybrid converters with a resultant
saving of space, power and cost.
The ADC16061 operates with excellent dynamic performance at input frequencies up to 1⁄2 the clock frequency. The
calibration feature of the ADC16061 can be used to get more
consistent and repeatable results over the entire operating
temperature range. On-command self-calibration reduces
many of the effects of temperature-induced drift, resulting in
more repeatable conversions.
The Power Down feature reduces power consumption to
less than 2mW.
The ADC16061 comes in a TQFP and is designed to operate
over the commercial temperature range of 0˚C to +70˚C.
n Single +5V Operation
n Self Calibration
n Power Down Mode
Key Specifications
n Resolution
16 Bits
n Conversion Rate
n DNL
2.5 Msps (min)
1.0 LSB (typ)
n SNR (fIN = 500 kHz)
n Supply Voltage
n Power Consumption
80 dB (typ)
+5V ± 5%
390mW (typ)
Applications
n
n
n
n
n
n
PC-Based Data Acquisition
Document Scanners
Digital Copiers
Film Scanners
Blood Analyzers
Sonar/Radar
Connection Diagram
DS100889-1
Ordering Information
Commercial
(0˚C ≤ TA ≤ +70˚C)
Package
ADC16061CCVT
VEG52A 52 Pin Thin Quad Flat Pack
© 2000 National Semiconductor Corporation
DS100889
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ADC16061 Self-Calibrating 16-Bit, 2.5 MSPS, 390 mW A/D Converter
January 2000
ADC16061
Block Diagram
DS100889-2
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2
ADC16061
Pin Descriptions and Equivalent Circuits
Pin
No.
Symbol
Equivalent Circuit
Description
Analog I/O
1
4
48
47
50
VIN+
Non-Inverting analog signal Input. With a 2.0V reference voltage
and a 2.0V common mode voltage, VCM, the input signal voltage
range is from 1.0 volt to 3.0 Volts.
VIN−
Inverting analog signal Input. With a 2.0V reference voltage and a
2.0V common mode voltage, VCM, the input signal voltage range is
from 1.0 Volt to 3.0 Volts. The input signal should be balanced for
best performance.
VREF+
VREF−
VREF+
IN
IN
OUT
49
VREF−
52
VREF (MID)
51
OUT
VCM
Positive reference input. This pin should be bypassed to AGND
with a 0.1 µF monolithic capacitor.
VREF+ minus VREF− IN should be a minimum of 1.8V and a
maximum of 2.2V. The full-scale input voltage is equal to VREF+
minus VREF− IN.
IN
Negative reference input. In most applications this pin should be
connected to AGND and the full reference voltage applied to
VREF+ IN. If the application requires that VREF−IN be offset from
AGND, this pin should be bypassed to AGND with a 0.1 µF
monolithic capacitor. VREF+ IN minus VREF− IN should be a
minimum of 1.8V and a maximum of 2.2V. The full-scale input
voltage is equal to VREF+ IN minus VREF− IN .
Output of the high impedance positive reference buffer. With a
2.0V reference input, and with a VCM of 2.0V, this pin will have a
3.0V output voltage. This pin should be bypassed to AGND with a
0.1 µF monolithic capacitor in parallel with a 10 µF capacitor.
The output of the negative reference buffer. With a 2.0V reference
and a VCM of 2.0V, this pin will have a 1.0V output voltage. This
pin should be bypassed to AGND with a 0.1 µF monolithic
capacitor in parallel with a 10 µF capacitor.
Output of the reference mid-point, nominally equal to 0.4 VA
(2.0V). This pin should be bypassed to AGND with a 0.1 µF
monolithic capacitor. This voltage is derived from VCM.
Input to the common mode buffer, nominally equal to 40% of the
supply voltage (2.0V). This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. Best performance is obtained if this
pin is driven with a low impedance source of 2.0V.
3
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ADC16061
Pin Descriptions and Equivalent Circuits
(Continued)
Digital I/O
10
11
CLOCK
Digital clock input. The input voltage is captured tAD after the fall of
the clock signal. The range of frequencies for this input is 300 kHz
to 2.5 MHz. The clock frequency should not be changed or
interrupted during conversion or while reading data output.
CAL
CAL is a level-sensitive digital input that, when pulsed high for at
least two clock cycles, puts the ADC into the CALIBRATE mode.
Calibration should be performed upon ADC power-up (after
asserting a reset) and each time the temperature changes by more
than 50˚C since the ADC16061 was last calibrated. See Section
2.3 for more information.
40
RESET
RESET is a level-sensitive digital input that, when pulsed high for
at least 2 CLOCK cycles, results in the resetting of the ADC. This
reset pulse must be applied after ADC power-up, before
calibration.
18
RD
RD is the (READ) digital input that, when low, enables the output
data buffers. When this input pin is high, the output data bus is in
a high impedance state.
44
PD
PD is the Power Down input that, when low, puts the converter
into the power down mode. When this pin is high, the converter is
in the active mode.
17
EOC
EOC is a digital output that, when low, indicates the availability of
new conversion results at the data output pins.
21-32
35-38
D00-15
Digital data outputs that make up the 16-bit TRI-STATE conversion
results. D00 is the LSB, while D15 is the MSB (SIGN bit) of the
two’s complement output word.
Analog Power
6, 7,
45
VA
Positive analog supply pins. These pins should be connected to a
clean, quiet +5V source and bypassed to AGND with 0.1 µF
monolithic capacitors in parallel with 10 µF capacitors, both located
within 1 cm of these power pins.
5, 8,
46
AGND
The ground return for the analog supply. AGND and DGND should
be connected together directly beneath the ADC16061 package.
See Section 5 (Layout and grounding) for more details).
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(Continued)
Digital Power
20
12,
13,
14,
19,
41,
42, 43
34
33
VD
DGND
Positive digital supply pin. This pin should be connected to the
same clean, quiet +5V source as is VA and bypassed to DGND
with a 0.1 µF monolithic capacitor in parallel with a 10µF capacitor,
both located within 1 cm of the power pin.
The ground return for the digital supply. AGND and DGND should
be connected together directly beneath the ADC16061 package.
See Section 5 (Layout and Grounding) for more details.
VD I/O
Positive digital supply pin for the ADC16061’s output drivers. This
pin should be connected to a +3V to +5V source and bypassed to
DGND I/O with a 0.1 µF monolithic capacitor. If the supply for this
pin is different from the supply used for VA and VD, it should also
be bypassed with a 10 µF capacitor. All bypass capacitors should
be located within 1 cm of the supply pin.
DGND I/O
The ground return for the digital supply for the ADC16061’s output
drivers. This pin should be connected to the system digital ground,
but not be connected in close proximity to the ADC16061’s DGND
or AGND pins. See Section 5.0 (Layout and Grounding) for more
details.
NC
2, 3,
9, 15,
16, 39
NC
All pins marked NC (no connect) should be left floating. Do not
connect the NC pins to ground, power supplies, or any other
potential or signal. These pins are used for test in the
manufacturing process.
5
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ADC16061
Pin Descriptions and Equivalent Circuits
ADC16061
Absolute Maximum Ratings (Note 1)
Storage Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings(Notes 1, 2)
Operating Temperature
Range
0˚C ≤ TA ≤ +70˚C
−0.3V to V+ +0.3V
VA, VD
+4.75V to +5.25V
± 25mA
± 50mA
VD I/O
VREF − IN
1.0V to 3.0V
(Note 4)
VREF− IN
AGND to 0.1V
Supply Voltage (VA, VD, VD I/O)
Voltage on Any I/O Pin
−65˚C to +150˚C
6.5V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at TA = 25˚C
ESD Susceptibility (Note 5)
2.7V to VD
Digital Inputs
Human Body Model
1500V
Machine Model
200V
Soldering Temp., Infrared, 10 sec. (Note 6)
−0.05V to VD + 0.05V
≤ 100 mV
|VA − VD|
|AGND - DGND |
0V to 100 mV
300˚C
Converter Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, V+ = VA = VD = +5.0V, VD I/O = 3.0V or 5.0V,
PD = +5V, VREF+ IN = +2.0V, VREF− IN = AGND, fCLK = 2.5 MHz, CL = 50 pF/pin. After Auto-Cal. Boldface limits apply for
TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C(Notes 7, 8, 9)
Symbol
Parameter
Typical
(Note 10)
Conditions
Limits
(Note 11)
Units
15
Bits(min)
Static Converter Characteristics
Resolution with No
Missing Codes
INL
DNL
Integral Non Linearity
Differential Non Linearity
±3
At 16 Bits
±1
At 16 Bits
±9
LSB(max)
+3
LSB(max)
−2
LSB(min)
Full-Scale Error
± 0.6
3.0
% FS(max)
Zero Offset Error
+0.1
± 0.7
% FS(max)
2.0
1.8
2.2
V(min)
V(max)
Reference and Analog Input Characteristics
VIN
CIN
VREF
Input Voltage Range
(VIN+ − VIN− )
Input Capacitance
VIN = 1.0V + 0.7Vrms
(CLK
LOW)
12
pF
(CLK
HIGH)
28
pF
Reference Voltage
Range [( VREF+ IN) −
(VREF −IN)] (Note 14)
2.00
Reference Input
Resistance
3.5
KΩ
1.8
V(min)
2.2
V(max)
Dynamic Converter Characteristics
BW
Full Power Bandwidth
8
MHz
SNR
Signal-to-Noise Ratio
fIN = 500 kHz
80
dB
SINAD
Signal-to-Noise &
Distortion
fIN = 500 kHz
79
dB
THD
Total Harmonic
Distortion
fIN = 500 kHz
−88
dB
SFDR
Spurious Free Dynamic
Range
fIN = 500 kHz
91
dB
IMD
Intermodulation
Distortion
fIN1 = 95 kHz
fIN2 = 105 kHz
−97
dB
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The following specifications apply for AGND = DGND = DGND I/O = 0V, V+ = VA = VD = +5.0V, VD I/O = 3.0V or 5.0V,
PD = +5V, VREF+ = +2.0V, VREF IN = AGND, fCLK = 2.5 MHz, RS = 25Ω, CL = 50 pF/pin. After Auto-Cal. Boldface limits
apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C(Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
CLOCK, RD, PD Digital Input Characteristics
VIN(1)
Logical ″1″ Input Voltage
V+ = 5.25V
VIN(0)
Logical ″0″ Input Voltage
V+ = 4.75V
IIN(1)
Logical ″1″ Input Current
IIN(0)
Logical ″0″ Input Current
CIN
VIN Input Capacitance
VIN = 5.0V
VIN = 0V
Limits
(Note 11)
Units
2.0
V(min)
0.8
V(max)
5
µA
−5
µA
5
pF
CAL, RESET Digital Input Characteristics
VIN(1)
Logical ″1″ Input Voltage
VIN(0)
Logical ″0″ Input Voltage
IIN(1)
Logical ″1″ Input Current
V+ = 5.25V
V+ = 4.75V
VIN = 5.0V
IIN(0)
Logical ″0″ Input Current
VIN = 0V
CIN
Input Capacitance
3.5
V(min)
1.0
V(max)
5
µA
−5
µA
5
pF
D00 - D13 Digital Output Characteristics
VOUT(1)
Logical ″1″ Output
Voltage
VD I/O = 4.75V, IOUT = −360 µA
4.5
V(min)
VOUT(1)
Logical ″1″ Output
Voltage
VD I/O = 2.7V, IOUT = −360 µA
2.5
V(min)
VOUT(0)
Logical ″0″ Output
Voltage
0.4
V(max)
0.4
V(max)
IOZ
TRI-STATE Output
Current
VD I/O = 5.25V, IOUT = 1.6 mA
VD I/O = 3.3V, IOUT = 1.6 mA
VOUT = 3V or 5V
100
nA
VOUT = 0V
−100
nA
+ISC
Output Short Circuit
Source Current
VOUT = 0V, VD I/O = 3V
−10
mA
−ISC
Output Short Circuit Sink
Current
VOUT = VD I/O = 3V
12
mA
PD = VD I/O
PD = VD I/O
70
85
mA(max)
7
8
mA(max)
Power Supply Characteristics
IA
Analog Supply Current
ID
Digital Supply Current
ID I/O
Output Bus Supply
Current
PD = VD I/O
1
2
mA(max)
Total Power
Consumption
PD = VD I/O
PD = DGND
390
475
mW(max)
PSRR
Power Supply Rejection
Ratio
<2
mW
Change in Full Scale as VA goes from
4.25V to 5.25V
68
dB
100 mVPP 100 kHz riding on VA
54
dB
AC Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, V+ = VA = VD = +5.0V, VD I/O = 3.0V or 5.0V,
PD = +5V, VREF+ = +2.0V, VREF IN = AGND, fCLK = 2.5 MHz, RS = 25Ω, CL = 50 pF/pin. After Auto-Cal. Boldface limits
apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C(Notes 7, 8, 9)
Symbol
fCLK
Parameter
Conditions
Conversion Clock (CLOCK)
Frequency
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
2.5
MHz(max)
300
3
kHz(min)
Conversion Clock Duty Cycle
45
55
%(min)
%(max)
tCONV
Conversion Latency
13
Clock Cycles
tAD
Aperture Delay
9
ns
7
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ADC16061
DC and Logic Electrical Characteristics
ADC16061
AC Electrical Characteristics
(Continued)
The following specifications apply for AGND = DGND = DGND I/O = 0V, V+ = VA = VD = +5.0V, VD I/O = 3.0V or 5.0V,
PD = +5V, VREF+ = +2.0V, VREF IN = AGND, fCLK = 2.5 MHz, RS = 25Ω, CL = 50 pF/pin. After Auto-Cal. Boldface limits
apply for TA = TJ = TMIN to TMAX: all other limits TA = TJ = 25˚C(Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
tOD
Falling edge of CLK to Data
Valid
50
tEOCL
Falling edge of CLK to falling
edge of EOC
1/(4fCLK)
90
130
ns(min)
ns(max)
tDATA_VALID
Falling edge of CLOCK to Data
Valid
1/(8fCLK)
38
95
ns(min)
ns(max)
tAD
Aperture Delay
9
tON
RD low to data valid on D00
-D15
23
33
ns(max)
tOFF
RD high to D00 -D15 in
TRI-STATE
25
33
ns(max)
tCAL
Calibration Time
110
ns
ns
ms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND I/O = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be limited to 25 mA.
The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA)/θJA. In the 52-pin
TQFP, θJA is 70˚C/W, so PDMAX = 1,785 mW at 25˚C and 1,142 mW at the maximum operating ambient temperature of 70˚C. Note that the power dissipation of this
device under normal operation will typically be about 416 mW (390 mW quiescent power + 26 mW due to 1 TTL load on each digital output. The values for maximum
power dissipation listed above will be reached only when the ADC16061 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pF discharged through ZERO Ω.
Note 6: See AN450, ″Surface Mounting Methods and Their Effect on Product Reliability″, or the section entitled ″Surface Mount″ found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltages above VA or below GND will not damage this device, provided current is limited per Note 3. However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 4.75 VDC, the full-scale input
voltage must be ≤4.85VDC to ensure accurate conversions
DS100889-12
DS100889-11
ESD Protection Scheme for Analog Input and Digital
Output pins
ESD Protection Scheme for Digital Input pins
Note 8: To guarantee accuracy, it is required that VA and VD be connected together and to the same power supply with separate bypass capacitors at each V+ pin.
Note 9: With the test condition for VREF = (VREF+) − (VREF−) given as +2.0V, the 16-bit LSB is 30 µV.
Note 10: Typical figures are at TA = TJ = 25˚C, and represent most likely parametric norms.
Note 11: Tested limits are guaranteed to Nationsl’s AOQL (Average Outgoing Quality Level) with 50% duty cycle clock.
Note 12: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and
negative full-scale.
Note 13: Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
Note 14: Optimum SNR performance will be obtained by keeping the reference voltage in the 1.8V to 2.2V range. The LM4041CIM3-ADJ (SOT-23 package), or the
LM4041CIZ-ADJ (TO-92 package), bandgap voltage reference is recommended for this application.
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ADC16061
Electrical Characteristics (continued)
DS100889-13
FIGURE 1. Transfer Characteristics
DS100889-14
FIGURE 2. Errors removed by Auto-Cal cycle
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ADC16061
Typical Performance Characteristics
INL vs Temperature
DNL vs Temperature
DS100889-25
INL vs VREF and Temperature
DS100889-26
DNL vs VREF
DS100889-27
THD vs Temperaure
DS100889-35
SINAD & ENOB vs Temperature
SNR vs Temperature
DS100889-28
DS100889-34
SINAD & ENOB vs Clock Duty
Cycle
SFDR vs Temperature
DS100889-29
DS100889-30
IMD
Spectral Response
DS100889-32
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DS100889-33
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DS100889-31
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (1⁄2 LSB below the first code transition) through
positive full scale (the last code transition). The deviation of
any given code from this straight line is measured from the
center of that code value.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is presented to the output stage. Data for any given sample is
available the Pipeline Delay plus the Output Delay after that
sample is taken. New data is available at every clock cycle,
but the data lags the conversion by the pipeline delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD)) is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first six harmonic
components, to the rms value of the input signal.
APERTURE DELAY is the time required after the falling
edge of the clock for the sampling switch to open. In other
words, for the Track/Hold circuit to go from ’track’ mode into
the ’hold’ mode. The Track/Hold circuit affectively stops capturing the input signal and goes into the ’hold’ mode tAD after
the fall of the clock.
OFFSET ERROR is the difference between the ideal LSB
transition to the actual transition point. The LSB transition
should occur when VIN+ = VIN−.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD
−1.76) / 6.02.
FULL SCALE ERROR is the difference between the input
voltage [(VIN+) − (VIN−)] just causing a transition to positive
full scale and VREF − 1.5 LSB, where VREF is ( VREF+ IN) −
(VREF−IN).
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input. The test
is performed with fIN equal to 100 kHz plus integral multiples
of fCLK. The input frequency at which the output is −3 dB
relative to the low frequency input signal is the full power
bandwidth.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
Timing Diagrams
DS100889-15
TIMING DIAGRAM 1. Output Timing
11
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ADC16061
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dB.
Specification Definitions
ADC16061
Timing Diagrams
(Continued)
DS100889-16
TIMING DIAGRAM 2. Reset and Calibration Timing
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Operating on a single +5V supply, the ADC16061 uses a
pipelined architecture and has error correction circuitry and a
calibration mode to help ensure maximum performance at all
times.
VREF (MID) is the reference mid-point and is derived from
VCM. This point is brought out only to be by passed. Bypass
this pin with 0.1µF capacitor to ground. Do not load this pin.
It is very important that all grounds associated with the reference voltage make connection to the analog ground plane at
a single point to minimize the effects of noise currents in the
ground path.
1.3 Signal Inputs
The signal inputs are VIN+ and VIN −. The signal input, VIN,
is defined as
VIN = (VIN+) − (VIN−).
Balanced analog signals with a peak-to-peak voltage equal
to the input reference voltage, VREF, and centered around
the common mode input voltage, VCM, are digitized to 16 bits
(15 bits plus sign). Neglecting offsets, positive input signal
voltages (VIN+ − VIN− ≥ 0) produce positive digital output
data and negative input signal voltages (VIN+ − VIN− < 0)
produce negative output data. The input signal can be digitized at any clock rate between 300 Ksps and 2.5 Msps.
Input voltages below the negative full scale value will cause
the output word to take on the negative full scale value of
1000,0000,0000,0000. Input voltage above the positive full
scale value will cause the output word to take on the positive
full scale value of 0111,1111,1111,1111.
The output word rate is the same as the clock frequency. The
analog input voltage is acquired at the falling edge of the
clock and the digital data for that sample is delayed by the
pipeline for 13 clock cycles plus tDATA_VALID. The digital output is undefined if the chip is being reset or is in the calibration mode. The output signal may be inhibited by the RD pin
while the converter is in one of these modes.
The RD pin must be low to enable the digital outputs. A logic
low on the power down (PD) pin reduces the converter
power consumption to less than two milliwatts.
Figure 3 indicates the relationship between the input voltage
and the reference voltages. Figure 4 shows the expected input signal range.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC16061:
DS100889-17
FIGURE 3. Typical Input to Reference Relationship.
4.75V ≤ VA ≤ 5.25V
5.25V ≤ VD ≤ 5.25V
3.0V ≤ VD I/O ≤ VD
0.3MHz ≤ fCLK ≤ 2.5 MHz
VCM = 2.0V (forced)
VREF IN+ = 2.0V
VREF IN− = AGND
1.1 The Analog Inputs
The ADC16061 has two analog signal inputs, VIN+ and VIN−.
These two pins form a balanced input. There are two reference pins, VREF+ IN and VREF− IN. These pins form a differential input reference.
1.2 Reference Inputs
VREF+ IN should always be more positive than VREF− IN. The
effective reference voltage, VREF, is the difference between
these two voltages:
VREF = (VREF+ IN) − (VREF− IN).
DS100889-18
FIGURE 4. Expected Input Signal Range.
The ADC16061 performs best with a balanced input centered around VCM. The peak-to-peak voltage swing at either
VIN+ or VIN− should be less than the reference voltage and
each signal input pin should be centered on the VCM voltage.
The two VCM-centered input signals should be exactly 180˚
out of phase from each other. As a simple check to ensure
this, be certain that the average voltage at the ADC input
pins is equal to VCM. Drive the analog inputs with a source
impedance less than 100 Ohms.
The operational voltage range of VREF+ IN is +1.8 Volts to
+3.0 Volts. The operational voltage range of VREF− IN is
ground to 1.0V. For best performance, the difference between VREF+ IN and VREF− IN should remain within the range
of 1.8V to 2.2V. Reducing the reference voltage below 1.8V
will decrease the signal-to-noise ratio (SNR) of the
ADC16061. Increasing the reference voltage (and, consequently, the input signal swing) above 2.2V will increase
THD.
13
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ADC16061
Functional Description
ADC16061
Applications Information
Note that the buffer used for this purpose should be a slow,
low noise amplifier. The LMC660, LMC662, LMC272 and
LMC7101 are good choices for driving the VCM pin of the
ADC16061.
(Continued)
The sign bit of the output word will be a logic low when VIN+
is greater than VIN− . When VIN+ is less than VIN−, the sign
bit of the output word will be a logic high.
If it is desired to use a multiplexer at the analog input, that
multiplexer should be switched at the rising edge of the clock
signal.
For single ended operation, one of the analog inputs should
be connected to VCM. However, SNR and SINAD are reduced by about 12dB with a single ended input as compared
with differential inputs.
An input voltage of VIN = (VIN+) − (VIN−) = 0 will be interpreted as mid-scale and will thus be converted to
0000,0000,0000,0000, plus any offset error.
The VIN+ and the VIN− inputs of the ADC16061 consist of an
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 12 pF when the clock is low,
and 28 pF when the clock is high. It is recommended that the
ADC16061 be driven with a low impedance source of 100
Ohms or less.
Since a dynamic capacitance is more difficult to drive than is
a fixed capacitance, choose driving amplifiers carefully. The
CLC440, LM6152, LM6154, LM6172, LM6181 and LM6182
are good amplifiers for driving the ADC16061.
A simple application circuit is shown in Figure 6 and Figure 7.
Here we use two LM6172 dual amplifiers to provide a balanced input to the ADC16061. Note that better noise performance is achieved when VREF+ IN voltage is forced with a
well-bypassed resistive divider. The resulting offset and offset drift is minimal.
1.4 VCM Analog Inputs
2.0 DIGITAL INPUTS
Digital Inputs consist of CLOCK, RESET, CAL, RD and PD.
All digital input pins should remain stable from the fall of the
clock until 30ns after the fall of the clock to minimize digital
noise corruption of the input signal on the die.
2.1 The CLOCK signal drives an internal phase delay loop to
create timing for the ADC. Drive the clock input with a stable,
low phase jitter clock signal in the range of 300 kHz to 2.5
MHz. The trace carrying the clock signal should be as short
as possible. This trace should not cross any other signal line,
analog or digital, not even at 90˚.
The CLOCK signal also drives the internal state machine. If
the clock is interrupted, the data within the pipeline could become corrupted.
A 100 Ohm damping resistor should be placed in series with
the CLOCK pin to prevent signal undershoot at that input.
2.2 The RESET input is level sensitive and must be pulsed
high for at least two clock cycles to reset the ADC after
power-up and before calibration (See Timing Diagram 2).
2.3 The CAL input is level sensitive and must be pulsed high
for at least two clock cycles to begin ADC calibration (See
Timing Diagram 2). Reset the ADC16061 before calibrating.
Re-calibrate after the temperature has changed by more
than 50˚C since the last calibration was performed and after
return from power down.
During calibration, use the same clock frequency that will be
used for conversions to avoid excessive offset errors.
Calibration takes 272,800 clock cycles. Irrelevant data may
appear at the data outputs during RESET or CAL and for 13
clock cycles thereafter. Calibration should not be started until
the reference outputs have settled (100ms with 1µF capacitors on these outputs) after power up or coming out of the
power down mode.
2.4 RD pin is used to READ the conversion data. When the
RD pin is low, the output buffers go into the active state.
When the RD input is high, the output buffers are in the high
impedance state.
2.5 The PD pin, when low, holds the ADC16061 in a
power-down mode where power consumption is typically
less than 2mW to conserve power when the converter is not
being used. Power consumption during shut-down is not affected by the clock frequency, or by whether there is a clock
signal present. The data in the pipeline is corrupted while in
the power down mode. The ADC16061 should be reset and
calibrated upon returning to normal operation after a power
down.
The VCM input of the ADC16061 is internally biased to 40%
of the VA supply with on-chip resistors, as shown in Figure 5.
The VCM pin must be bypassed to prevent any power supply
noise from modulating this voltage. Modulation of the VCM
potential will result in the introduction of noise into the input
signal. The advantage of simply bypassing VCM (without
driving it) is the circuit simplicity. On the other hand, if the VA
supply can vary for any reason, VCM will also vary at a rate
and amplitude related to the RC filter created by the bypass
capacitor and the internal divider resistors. However, performance of this approach will be adequate for many
applications.
DS100889-21
FIGURE 5. VCM input to the ADC16061 VCM is set to
40% of VA with on-chip resistors. Performance is
improved when VCM is driven with a stable, low
impedance source
3.0 OUTPUTS
The ADC16061 has four analog outputs: VREF+ OUT,
VREF− OUT, VREF (MID) and VCM . There are 17 digital outputs: EOC (End of Conversion) and 16 Data Output pins.
By forcing VCM to a fixed potential, you can avoid the problems mentioned above. One such approach is to buffer the
2.0 Volt reference voltage to drive the VCM input, holding it at
a constant potential as shown in Figure 6 and Figure 8. If the
reference voltage is different from the desired VCM, that desired VCM voltage may be derived from the reference or from
another stable source.
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3.1 The reference output voltages are made available only
for the purpose of bypassing with capacitors. These pins
should not be loaded with more than 10 µA DC. These output
voltages are described as
VREF+ OUT = VCM + 1⁄2VREF
14
VREF−
Each power supply pin should be bypassed with a parallel
combination of a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor. The chip capacitors should be within 1⁄2 centimeter
of the power pins. Leadless chip capacitors are preferred because they provide low lead inductance.
= VCM − 1⁄2VREF
= (VREF+ IN) − (VREF+ IN)
OUT
where VREF
(MID) = (VREF+
VREF
4.0 POWER SUPPLY CONSIDERATIONS
(Continued)
OUT
+ VREF−
OUT)
/ 2.
While a single 5V source is used for the analog and digital
supplies of the ADC16061, these supply pins should be well
isolated from each other to prevent any digital noise from being coupled to the analog power pins. Supply isolation with
ferrite beads is shown in Figure 6 and Figure 8.
As is the case with all high-speed converters, the ADC16061
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be kept below 15 mVP-P.
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even during power up or power
down.
The VD I/O provides power for the output drivers and may be
operated from a supply in the range of 2.7V to the VD supply
(nominal 5V). This can simplify interfacing to 3.0 Volt devices
and systems. Powering VD I/O from 3 Volts will also reduce
power consumption and noise generation due to output
switching. DO NOT operate the VD I/O at a voltage higher
than VD or VA.
To avoid signal clipping and distortion, VREF+ OUT should not
exceed 3.3V, VREF− OUT should not be below 750 mV and
VCM should be held in the range of 1.8V to 2.2V.
3.2 The EOC output goes low to indicate the presence of
valid data at the output data lines. Valid data is present the
entire time that this signal is low, except during reset. Corrupt
or irrelevant data may appear at the data outputs when the
RESET pin or the CAL pin is high.
3.3 The Data Outputs are TTL/CMOS compatible. The output data format is two’s complement. Valid data is present at
these outputs while the EOC pin is low. While the tEOCL time
and the tDATA_VALID time provide information about output
timing, a simple way to capture a valid output is to latch the
data on the rising edge of the CLOCK (pin 10).
Also helpful in minimizing noise due to output switching is to
minimize the load currents at the digital outputs. This can be
done by connecting buffers between the ADC outputs and
any other circuitry. Only one input should be connected to
each output pin. Additionally, inserting series resistors of 47
or 56 Ohms at the digital outputs, close to the ADC pins, will
isolate the outputs from other circuitry and limit output currents. (See Figure 6).
DS100889-19
FIGURE 6. Simple application circuit with single-ended to differential buffer.
15
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ADC16061
Applications Information
ADC16061
Applications Information
(Continued)
DS100889-20
FIGURE 7. Differential drive circuit of Figure 6. All 5k resistors are 0.1%. Tolerance of the other resistors is not
critical.
DS100889-22
FIGURE 8. Driving the signal inputs with a transformer.
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16
rest of the ground plane. A typical width is 3/16 inch (4 to 5
mm).This narrowing beneath the converter provides a fairly
high impedance to the high frequency components of the
digital switching currents, directing them away from the analog pins. The relatively lower frequency analog ground currents see a relatively low impedance across this narrow
ground connection.
(Continued)
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Separate analog and
digital ground planes that are connected beneath the
ADC16061 are required to achieve specified performance.
The analog and digital grounds may be in the same layer, but
should be separated from each other and should never overlap each other. Separation should be at least 1⁄8 inch, where
possible.
The ground return for the digital supply (DGND I/O ) carries
the ground current for the output drivers. This output current
can exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DGND
I/O pin should NOT be connected in close proximity to any of
the ADC16061’s other ground pins.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and
remedy. The solution is to keep the analog circuitry separated from the digital circuitry and from the digital ground
plane.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is very narrow compared with the
Generally, analog and digital lines should cross each other at
90 degrees to avoid getting digital noise into the analog path.
To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep any clock lines isolated from
ALL other lines, including other digital lines. Even the generally accepted 90 degree crossing should be avoided as even
a little coupling can cause problems at high frequencies.
This is because other lines can introduce phase noise (jitter)
into the clock line, which can lead to degradation of SNR.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, not even with just a small part of their bodies beside
each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input and ground should be connected
to a very clean point in the analog ground plane.
Figure 9 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be placed over the digital
ground plane.
All ground connections should have a low inductance path to
ground.
17
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ADC16061
Applications Information
ADC16061
Applications Information
(Continued)
DS100889-23
FIGURE 9. Example at a suitable layout.
mV below the ground pins or 100 mV above the supply pins).
Exceeding these limits on even a transient basis may cause
faulty or erratic operation. It is not uncommon for high speed
digital circuits (e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A resistor of
about 50 to 100Ω in series with the offending digital input will
eliminate the problem.
Do not allow input voltages to exceed the supply voltage during power up.
Be careful not to overdrive the inputs of the ADC16061 with
a device that is powered from supplies outside the range of
the ADC16061 supply. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through VD I/O and DGND I/O. These large charging
current spikes can couple into the analog circuitry of the
ADC16061, degrading dynamic performance. Adequate bypassing and maintaining separate analog and digital ground
planes will reduce this problem. The digital data outputs
should be buffered (with 74ACQ541, for example). Dynamic
performance can also be improved by adding series resistors at each digital output, close to the ADC16061, which reduces the energy coupled back into the converter output
pins by limiting the output current. A reasonable value for
these resistors is 47Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the input alternates between 12 pF and 28 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade perfor-
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance with the
ADC16061, the clock source driving the CLK input must be
free of jitter. For best ac performance, isolate the ADC clock
from any digital circuitry with buffers, as with the clock tree
shown in Figure 10.
As mentioned in section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce phase
noise (jitter) into the clock signal, which can lead to increased distortion. Even lines with 90˚ crossings have capacitive coupling, so try to avoid even these 90˚ crossings of
the clock line.
DS100889-24
FIGURE 10. Isolating the ADC clock from other
circuitry with a clock tree.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than 100
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18
with VREF− IN ≤ 1.0V. Operating outside of these limits could
lead to excessive distortion or noise.
(Continued)
mance. Amplifiers that have been used successfully to drive
the analog inputs of the ADC16061 include the CLC427,
CLC440, LM6152, LM6154, LM6181 and the LM6182. A
small series reistor at each amplifier output and a capacitor
across the analog inputs (as shown in Figure 7) will often improve performance.
Operating with the reference pins outside of the specified range. As mentioned in section 1.2, VREF should be in
the range of
1.8V ≤ VREF ≤ 2.2V
Using a clock source with excessive jitter, using an excessively long clock signal trace, or having other signals coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR performance.
Connecting pins marked ″NC″ to any potential. Some of
these pins are used for factory testing. They should all be left
floating. Connecting them to ground, power supply, or some
other voltage could result in a non-functional device.
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ADC16061
Applications Information
ADC16061 Self-Calibrating 16-Bit, 2.5 MSPS, 390 mW A/D Converter
Physical Dimensions
inches (millimeters) unless otherwise noted
52-Lead Thin Quad Flat Pack
Ordering Number ADC16061CCVT
NS Package Number VEG52A
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