Elpida HM5165405F 64 m edo dram (16-mword ã 4-bit) 8 k refresh/4 k refresh Datasheet

EO
HM5164405F Series
HM5165405F Series
64 M EDO DRAM (16-Mword × 4-bit)
8 k Refresh/4 k Refresh
L
Description
E0097H10 (1st edition)
(Previous ADE-203-1056C (Z))
Jan. 31, 2001
Features
Pr
The HM5164405F S erie s, HM5165405F S erie s ar e 64M-bit dynamic R AMs orga nized as 16, 777,216-w ord
× 4-bit. The y have re alize d high per forma nce and low powe r by employing C MOS proc ess tec hnology.
HM5164405F S erie s, HM5165405F S erie s off er Extende d Da ta Out (ED O) P age Mode as a high spee d
ac ce ss mode. The y have the pac kage var iation of standa rd 32-pin plastic S OJ and standa rd 32-pin plastic
TSOPII.
This product became EOL in December, 2006.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
t
uc
od
• Single 3.3 V supply: 3.3 V ± 0.3 V
• Access time: 50 ns/60 ns (max)
• Power dissipation
 Active: 396 mW/360 mW (max) (HM5164405F Series)
: 468 mW/396 mW (max) (HM5165405F Series)
 Standby : 1.8 mW (max) (CMOS interface)
: 1.1 mW (max) (L-version)
• EDO page mode capability
• Refresh cycles
 RAS-only refresh
8192 cycles /64 ms (HM5164405F, HM5164405FL)
4096 cycles /64 ms (HM5165405F, HM5165405FL)
 CBR/Hidden refresh
4096 cycles /64 ms (HM5164405F, HM5164405FL, HM5165405F, HM5165405FL)
HM5164405F Series, HM5165405F Series
EO
• 4 variations of refresh
 RAS-only refresh
 CAS-before-RAS refresh
 Hidden refresh
 Self refresh (L-version)
• Battery backup operation (L-version)
Ordering Information
Access time
Package
HM5164405FJ-5
HM5164405FJ-6
50 ns
60 ns
400-mil 32-pin plastic SOJ
(CP-32DC)
HM5164405FLJ-5
HM5164405FLJ-6
HM5165405FJ-5
HM5165405FJ-6
HM5164405FTT-5
HM5164405FTT-6
HM5164405FLTT-5
HM5164405FLTT-6
HM5165405FTT-5
HM5165405FTT-6
50 ns
60 ns
50 ns
60 ns
50 ns
60 ns
400-mil 32-pin plastic TSOP II
(TTP-32DC)
50 ns
60 ns
50 ns
60 ns
50 ns
60 ns
t
uc
od
HM5165405FLTT-5
HM5165405FLTT-6
50 ns
60 ns
Pr
HM5165405FLJ-5
HM5165405FLJ-6
L
Type No.
Data Sheet E0097H10
2
HM5164405F Series, HM5165405F Series
Pin Arrangement (HM5164405F Series)
EO
32-pin SOJ
32-pin TSOP
1
32
V SS
VCC
1
32
V SS
I/O0
2
31
I/O3
I/O0
2
31
I/O3
I/O1
3
30
I/O2
I/O1
3
30
I/O2
NC
4
29
NC
NC
4
29
NC
NC
5
28
NC
NC
5
28
NC
NC
6
27
NC
L
NC
6
27
NC
7
26
CAS
NC
7
26
CAS
8
25
OE
WE
8
25
OE
9
24
A12
RAS
9
24
A12
A0
10
23
A11
A0
10
23
A11
A1
11
22
A10
A1
11
22
A10
A2
12
21
A9
A2
12
21
A9
A3
13
20
A8
A3
13
20
A8
A4
14
19
A7
A4
14
19
A7
A5
15
18
A6
A5
15
18
A6
VCC
16
17
V SS
VCC
16
17
V SS
NC
WE
RAS
(Top view)
uc
od
Pr
VCC
(Top view)
Pin Description
Function
A0 to A12
Address input
— Row/Refresh address A0 to A12
— Column address
A0 to A10
I/O0 to I/O3
Data input/output
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
t
Pin name
Data Sheet E0097H10
3
HM5164405F Series, HM5165405F Series
Pin Arrangement (HM5165405F Series)
EO
32-pin SOJ
32-pin TSOP
VCC
1
32
V SS
VCC
1
32
V SS
I/O0
2
31
I/O3
I/O0
2
31
I/O3
I/O1
3
30
I/O2
I/O1
3
30
I/O2
NC
4
29
NC
NC
4
29
NC
NC
5
28
NC
NC
5
28
NC
NC
L
27
NC
NC
6
27
NC
7
26
CAS
NC
7
26
CAS
8
25
OE
WE
8
25
OE
9
24
NC
RAS
9
24
NC
A0
10
23
A11
A0
10
23
A11
A1
11
22
A10
A1
11
22
A10
A2
12
21
A9
A2
12
21
A9
A3
13
20
A8
A3
13
20
A8
A4
14
19
A7
A4
14
19
A7
A5
15
18
A6
A5
15
18
A6
VCC
16
17
V SS
VCC
16
17
V SS
NC
WE
RAS
(Top view)
uc
od
Pr
6
(Top view)
Pin Description
Function
A0 to A11
Address input
— Row/Refresh address A0 to A11
— Column address
A0 to A11
I/O0 to I/O3
Data input/output
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
t
Pin name
Data Sheet E0097H10
4
HM5164405F Series, HM5165405F Series
Block Diagram (HM5164405F Series)
EO
RAS
CAS
Column
buffers
Row
address
buffers
16M array
16M array
I/O buffers
I/O0
to
I/O3
16M array
t
uc
od
A12
16M array
Pr
•
•
•
address
Row decoder
•
•
•
A10
A11
Column decoder
L
to
OE
Timing and control
A0
A1
WE
Data Sheet E0097H10
5
HM5164405F Series, HM5165405F Series
Block Diagram (HM5165405F Series)
EO
RAS
CAS
OE
Timing and control
Column decoder
A0
A11
16M array
buffers
Row
address
buffers
16M array
Pr
•
•
•
address
Row decoder
•
•
•
L
Column
A1
to
WE
16M array
I/O buffers
I/O0
to
I/O3
16M array
t
uc
od
Data Sheet E0097H10
6
HM5164405F Series, HM5165405F Series
Operation Table
EO
RAS
CAS
WE
OE
I/O 0 to I/O 3
Operation
H
×
×
×
High-Z
Standby
L
L
H
L
L
L
Dout
Read cycle
L*
2
×
Din
Early write cycle
2
H
Din
Delayed write cycle
L
L*
L
L
H to L
L to H
Dout/Din
Read-modify-write cycle
L
H
×
×
High-Z
RAS-only refresh cycle
H to L
L
H
×
High-Z
CAS-before-RAS refresh cycle or
Self refresh cycle (L-version)
L
L
High-Z
Read cycle (Output disabled)
L
L
H
H
Notes: 1. H: VIH (inactive), L: VIL (active), ×: VIH or VIL
2. t WCS ≥ 0 ns: Early write cycle
t WCS < 0 ns: Delayed write cycle
Parameter
Pr
Absolute Maximum Ratings
Symbol
Value
Unit
Terminal voltage on any pin relative to VSS
VT
–0.5 to VCC + 0.5 (≤ 4.6 V (max))
V
Power supply voltage relative to VSS
VCC
–0.5 to +4.6
V
Iout
50
mA
Short circuit output current
PT
Storage temperature
Tstg
DC Operating Conditions
Parameter
Symbol
Supply voltage
VCC
VSS
Input high voltage
VIH
Input low voltage
VIL
Ambient temperature range
Ta
uc
od
Power dissipation
1.0
W
–55 to +125
°C
Min
Typ
Max
Unit
Notes
3.0
3.3
3.6
V
1, 2
0
0
0
V
2
2.0
—
VCC + 0.3
V
1
–0.3
—
0.8
V
1
0
—
70
˚C
Notes: 1. All voltage referred to VSS .
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins
must be on the same level.
t
Data Sheet E0097H10
7
HM5164405F Series, HM5165405F Series
DC Characteristics (HM5164405F Series)
EO
Parameter
1,
Operating current* *
2
Standby current
-5
RAS-only refresh current* 2
1
-6
Symbol Min
Max
Min
Max
Unit
Test conditions
I CC1
—
110
—
100
mA
t RC = min
I CC2
—
2
—
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
0.5
—
0.5
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
L
Standby current
(L-version)
Standby current*
HM5164405F
—
300
—
300
µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
I CC3
—
110
—
100
mA
t RC = min
I CC5
—
5
—
5
mA
RAS = VIH, CAS = VIL
Dout = enable
CAS-before-RAS refresh
current
I CC6
EDO page mode current* 1, * 3
I CC7
Battery backup current* 4
(Standby with CBR refresh)
(L-version)
I CC10
Self refresh mode current
(L-version)
Pr
I CC2
110
—
100
mA
t RC = min
—
110
—
100
mA
RAS = VIL , CAS cycle,
t HPC = t HPC min
—
1.2
—
1.2
mA
CMOS interface
Dout = High-Z
CBR refresh: t RC = 15.6 µs
t RAS ≤ 0.3 µs
I CC11
—
500
Input leakage current
I LI
–5
5
Output leakage current
I LO
–5
5
Output high voltage
VOH
2.4
VCC
Output low voltage
VOL
0
0.4
uc
od
—
—
500
µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
–5
5
µA
0 V ≤ Vin ≤ VCC + 0.3 V
–5
5
µA
0 V ≤ Vout ≤ VCC
Dout = disable
2.4
VCC
V
High Iout = –2 mA
0
0.4
V
Low Iout = 2 mA
Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, t HPC .
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
t
Data Sheet E0097H10
8
HM5164405F Series, HM5165405F Series
DC Characteristics (HM5165405F Series)
EO
Parameter
1,
Operating current* *
2
Standby current
-5
RAS-only refresh current* 2
1
-6
Symbol Min
Max
Min
Max
Unit
Test conditions
I CC1
—
130
—
110
mA
t RC = min
I CC2
—
2
—
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
0.5
—
0.5
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
L
Standby current
(L-version)
Standby current*
HM5165405F
I CC2
—
300
—
300
µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
I CC3
—
130
—
110
mA
t RC = min
I CC5
—
5
—
5
mA
RAS = VIH, CAS = VIL
Dout = enable
I CC6
EDO page mode current* 1, * 3
I CC7
Battery backup current* 4
(Standby with CBR refresh)
(L-version)
I CC10
Self refresh mode current
(L-version)
Pr
CAS-before-RAS refresh
current
130
—
110
mA
t RC = min
—
110
—
100
mA
RAS = VIL , CAS cycle,
t HPC = t HPC min
—
1.2
—
1.2
mA
CMOS interface
Dout = High-Z
CBR refresh: t RC = 15.6 µs
t RAS ≤ 0.3 µs
I CC11
—
500
Input leakage current
I LI
–5
5
Output leakage current
I LO
–5
5
Output high voltage
VOH
2.4
VCC
Output low voltage
VOL
0
0.4
uc
od
—
—
500
µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
–5
5
µA
0 V ≤ Vin ≤ VCC + 0.3 V
–5
5
µA
0 V ≤ Vout ≤ VCC
Dout = disable
2.4
VCC
V
High Iout = –2 mA
0
0.4
V
Low Iout = 2 mA
Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, t HPC .
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
t
Data Sheet E0097H10
9
HM5164405F Series, HM5165405F Series
Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.3 V)
EO
Parameter
Symbol
Typ
Max
Unit
Notes
Input capacitance (Address)
CI1
—
5
pF
1
Input capacitance (Clocks)
CI2
—
7
pF
1
Output capacitance (Data-in, Data-out)
CI/O
—
7
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS and CAS = VIH to disable Dout.
L
t
uc
od
Pr
Data Sheet E0097H10
10
HM5164405F Series, HM5165405F Series
AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *19
EO
Test Conditions
•
•
•
•
•
Input rise and fall time: 2 ns
Input pulse levels: VIL = 0 V, VIH = 3.0 V
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Random read or write cycle time
RAS precharge time
HM5164405F/HM5165405F
-5
-6
Symbol
Min
Max
Min
Max
Unit
t RC
84
—
104
—
ns
Pr
Parameter
L
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
Notes
30
—
40
—
ns
t CP
8
—
10
—
ns
t RAS
50
10000
60
10000
ns
t CAS
8
10000
10
10000
ns
t ASR
0
—
0
—
ns
t RAH
8
—
10
—
ns
t ASC
0
—
0
—
ns
Column address hold time
t CAH
8
—
10
—
ns
RAS to CAS delay time
t RCD
12
37
14
45
ns
3
RAS to column address delay time
t RAD
10
25
12
30
ns
4
RAS hold time
t RSH
13
—
15
—
ns
CAS hold time
t CSH
38
—
40
—
ns
CAS to RAS precharge time
t CRP
5
—
5
—
ns
OE to Din delay time
t OED
13
—
15
—
ns
5
OE delay time from Din
t DZO
0
—
0
—
ns
6
CAS delay time from Din
t DZC
0
—
0
—
ns
6
Transition time (rise and fall)
tT
2
50
2
50
ns
7
CAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
t
uc
od
t RP
Data Sheet E0097H10
11
HM5164405F Series, HM5165405F Series
Read Cycle
EO
HM5164405F/HM5165405F
-5
-6
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Access time from RAS
t RAC
—
50
—
60
ns
8, 9
Access time from CAS
t CAC
—
13
—
15
ns
9, 10, 17
Access time from address
t AA
—
25
—
30
ns
9, 11, 17
Access time from OE
t OEA
—
13
—
15
ns
9
Read command setup time
t RCS
0
—
0
—
ns
L
Read command hold time to CAS
t RCH
0
—
0
—
ns
Read command hold time from RAS
t RCHR
50
—
60
—
ns
Read command hold time to RAS
t RRH
0
—
0
—
ns
Column address to RAS lead time
t RAL
25
—
30
—
ns
Column address to CAS lead time
t CAL
15
—
18
—
ns
Pr
CAS to output in low-Z
12
12
t CLZ
0
—
0
—
ns
t OH
3
—
3
—
ns
t OHO
3
—
3
—
ns
t OFF
—
13
—
15
ns
13, 21
t OEZ
—
13
—
15
ns
13
t CDD
13
—
15
—
ns
5
t OHR
3
—
3
—
ns
21
Output buffer turn-off to RAS
t OFR
—
13
—
15
ns
13, 21
Output buffer turn-off to WE
t WEZ
—
13
—
15
ns
13
WE to Din delay time
t WED
13
—
15
—
ns
RAS to Din delay time
t RDD
13
—
15
—
ns
Output data hold time
Output data hold time from OE
Output buffer turn-off time
Output buffer turn-off to OE
CAS to Din delay time
t
uc
od
Output data hold time from RAS
21
Data Sheet E0097H10
12
HM5164405F Series, HM5165405F Series
Write Cycle
EO
HM5164405F/HM5165405F
-5
-6
Symbol
Min
Max
Min
Max
Unit
Notes
Write command setup time
t WCS
0
—
0
—
ns
14
Write command hold time
t WCH
8
—
10
—
ns
Write command pulse width
t WP
8
—
10
—
ns
Write command to RAS lead time
t RWL
13
—
15
—
ns
Write command to CAS lead time
t CWL
8
—
10
—
ns
t DS
0
—
0
—
ns
15
t DH
8
—
10
—
ns
15
Notes
Data-in setup time
Data-in hold time
L
Parameter
Read-Modify-Write Cycle
Pr
HM5164405F/HM5165405F
-5
Parameter
-6
Min
Max
Min
Max
Unit
t RWC
116
—
140
—
ns
t RWD
67
—
79
—
ns
14
t CWD
30
—
34
—
ns
14
Column address to WE delay time
t AWD
42
OE hold time from WE
t OEH
13
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
Refresh Cycle
uc
od
Symbol
—
49
—
ns
—
15
—
ns
14
HM5164405F/HM5165405F
-5
-6
Parameter
Symbol
Min
Max
Min
Max
Unit
CAS setup time (CBR refresh cycle)
t CSR
5
—
5
—
ns
CAS hold time (CBR refresh cycle)
t CHR
8
—
10
—
ns
WE setup time (CBR refresh cycle)
t WRP
0
—
0
—
ns
WE hold time (CBR refresh cycle)
t WRH
8
—
10
—
ns
RAS precharge to CAS hold time
t RPC
5
—
5
—
ns
Notes
t
Data Sheet E0097H10
13
HM5164405F Series, HM5165405F Series
EDO Page Mode Cycle
EO
HM5164405F/HM5165405F
-5
-6
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
EDO page mode cycle time
t HPC
20
—
25
—
ns
20
EDO page mode RAS pulse width
t RASP
—
100000 —
100000 ns
16
Access time from CAS precharge
t CPA
—
28
—
35
ns
9, 17
RAS hold time from CAS precharge
t CPRH
28
—
35
—
ns
Output data hold time from CAS low
t DOH
3
—
3
—
ns
L
CAS hold time referred OE
t COL
8
—
10
—
ns
CAS to OE setup time
t COP
5
—
5
—
ns
Read command hold time from
CAS precharge
t RCHC
28
—
35
—
ns
Write pulse width during CAS precharge t WPE
8
—
10
—
ns
OE precharge time
8
—
10
—
ns
Pr
t OEP
9, 22
EDO Page Mode Read-Modify-Write Cycle
HM5164405F/HM5165405F
-5
Symbol
Min
Max
Min
Max
Unit
EDO page mode read-modify-write
cycle time
t HPRWC
57
—
68
—
ns
WE delay time from CAS precharge
t CPW
45
—
54
—
ns
Refresh (HM5164405F Series)
Parameter
Symbol
Refresh period
t REF
Refresh (HM5165405F Series)
Parameter
Symbol
Refresh period
t REF
Notes
uc
od
Parameter
-6
14
Max
Unit
Notes
64
ms
8192 cycles
Max
Unit
Notes
64
ms
4096 cycles
t
Data Sheet E0097H10
14
HM5164405F Series, HM5165405F Series
Self Refresh Mode (L-version)
EO
HM5164405FL/HM5165405FL
-5
-6
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
RAS pulse width (self refresh)
t RASS
100
—
100
—
µs
25
RAS precharge time (self refresh)
t RPS
90
—
110
—
ns
25
CAS hold time (self refresh)
t CHS
–50
—
–50
—
ns
L
Notes: 1. AC measurements assume t T = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a
reference point only; if t RCD is greater than the specified t RCD (max) limit, than the access time is
controlled exclusively by t CAC .
4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a
reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is
controlled exclusively by t AA .
5. Either t OED or t CDD must be satisfied.
6. Either t DZO or t DZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that t RCD ≤ t RCD (max) and t RAD ≤ t RAD (max). If t RCD or t RAD is greater than the maximum
recommended value shown in this table, t RAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t RCD ≥ t RCD (max) and t RCD + t CAC (max) ≥ t RAD + t AA (max).
11. Assumes that t RAD ≥ t RAD (max) and t RCD + t CAC (max) ≤ t RAD + t AA (max).
12. Either t RCH or t RRH must be satisfied for a read cycles.
13. t OFF (max), t OEZ (max), t WEZ (max) and t OFR (max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if t WCS ≥ t WCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ t RWD (min),
t CWD ≥ t CWD (min), and t AWD ≥ t AWD (min), or t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t CPW (min), the
cycle is a read-modify-write and the data output will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
15. t DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed
write or read-modify-write cycles.
16. t RASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among t AA , t CAC and t CPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
19. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes large
VCC/V SS line noise, which causes to degrade VIH min/VIL max level.
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Data Sheet E0097H10
15
HM5164405F Series, HM5165405F Series
L
EO
20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page
mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the
specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO
page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold
time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS
between t OHR and t OH and between t OFR and t OFF.
22. t DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms
period on the condition a and b below.
a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6µs after exiting from self refresh mode.
24. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and after
self refresh mode according as note 23.
25 At t RASS > 100 µs, self refresh mode is activated, and not activated at t RASS < 10 µs. It is undefined
within the range of 10 µs ≤ t RASS ≤ 100 µs. For t RASS ≥ 10 µs, it is necessary to satisfy t RPS.
26. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL.
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Data Sheet E0097H10
16
HM5164405F Series, HM5165405F Series
Timing Waveforms*26
EO
Read Cycle
tRC
tRAS
tRP
RAS
tCSH
tRSH
L
tT
CAS
tRAD
tASR
Row
tRAH
tASC
tCAS
tRAL
tCAL
tCAH
Pr
Address
tCRP
tRCD
Column
tRRH
tRCHR
tRCS
WE
tRCH
uc
od
tDZC
tCDD
tWED
tRDD
High-Z
;
Din
tDZO
tOEA
OE
tOED
tOEZ
tOHO
tOFF
tOH
tOFR
tOHR
tCAC
tAA
tRAC
tCLZ
tWEZ
t
Dout
Dout
Data Sheet E0097H10
17
HM5164405F Series, HM5165405F Series
Early Write Cycle
EO
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
L
CAS
tASR
Row
tASC
tCAH
Pr
Address
tRAH
Column
tWCS
tDS
Din
Dout
uc
od
WE
tWCH
tDH
Din
High-Z*
* t WCS
t WCS (min)
t
Data Sheet E0097H10
18
HM5164405F Series, HM5165405F Series
Delayed Write Cycle*18
EO
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
L
CAS
tASR
Row
tASC
tCAH
Column
Pr
Address
tRAH
tCWL
tRWL
tWP
tRCS
WE
High-Z
tDH
Din
;
Din
uc
od
tDS
tDZC
tOED
tDZO
tOEH
tOEP
OE
tOEZ
tCLZ
Dout
High-Z
t
Invalid Dout
Data Sheet E0097H10
19
HM5164405F Series, HM5165405F Series
Read-Modify-Write Cycle*18
EO
tRWC
tRAS
tRP
RAS
tT
tCAS
L
CAS
tRCD
tCRP
tRAD
tASR
Row
tCAH
Column
Pr
Address
tASC
tRAH
tCWL
tCWD
tRCS
tRWL
tWP
tAWD
tRWD
WE
uc
od
tDZC
tDS
High-Z
Din
;
Din
tDH
tDZO
tOED
tOEH
tOEA
OE
tCAC
tAA
tRAC
Dout
tOEZ
tOHO
Dout
Data Sheet E0097H10
High-Z
t
tCLZ
20
tOEP
HM5164405F Series, HM5165405F Series
RAS-Only Refresh Cycle
EO
tRC
tRAS
tRP
RAS
tT
tRPC
tCRP
tCRP
CAS
L
tASR
Address
tRAH
Row
tOFR
High-Z
t
uc
od
;
Dout
Pr
tOFF
Data Sheet E0097H10
21
HM5164405F Series, HM5165405F Series
CAS-Before-RAS Refresh Cycle
EO
tRC
tRP
tRC
tRP
tRAS
tRAS
tRP
RAS
tT
tRPC
tCP
tCHR
tCP
L
CAS
tRPC
tCSR
tWRP
Address
tOFR
High-Z
Data Sheet E0097H10
t
;
Dout
22
tWRH
uc
od
tOFF
tWRP
tCHR
Pr
WE
tWRH
tCRP
tCSR
HM5164405F Series, HM5165405F Series
Hidden Refresh Cycle
EO
tRC
tRAS
tRC
tRAS
tRP
tRC
tRP
tRAS
tRP
RAS
tT
tRSH
tCHR
tCRP
tRCD
L
CAS
tRAD
tASR
Address
tRAH
tRAL
tASC
Row
tCAH
Column
WE
tRRH
tRCH
tWED
uc
od
tDZC
Pr
tRCS
tCDD
tRDD
High-Z
Din
tDZO
tOED
tOEA
OE
tCAC
tAA
tRAC
tOFF
;
tCLZ
Dout
tOEZ
tWEZ
tOHO
tOH
Dout
tOFR
t
tOHR
Data Sheet E0097H10
23
HM5164405F Series, HM5165405F Series
EDO Page Mode Read Cycle (1)
EO
t RP
RAS
tT
t CSH
t HPC
t CP
t CAS
CAS
t RCHR
t RCS
t HPC
t RASP
t CP
t HPC
t CPRH
t CP
t
t CRP
RSH
t CAS
tCAS
tCAS
t RCHC
t RCH t RCS
t RRH
t RCH
WE
Address
L
tASR
tRAH tASC
Row
tCAH
Column 1
t WPE
t ASC t CAH
t ASC t CAH
Column 2
Column 3
t CAL
t CAL
t RAL
t CAH
tASC
t WED
Column 4
t CAL
t CAL
tRDD
tCDD
tDZC
Pr
High-Z
Din
tCOL
tDZO
t OEP
OE
tOEA
tOED
tCPA
tAA
tCAC
tOEZ
tOHO
tOFR
tOHR
tOEZ
tCPA
tAA
tOEZ
;
tCAC
tAA
tCPA
tAA
tCAC
tCOP
tOEP
tRAC
Dout
tOEA
tDOH
Dout 1
tOHO
tOFF
tOH
uc
od
tWEZ
tCAC
Dout 2
Dout 2
tOHO
Dout 3
tOEA
Dout 4
t
Data Sheet E0097H10
24
HM5164405F Series, HM5165405F Series
EDO Page Mode Read Cycle (2)
EO
t RP
t RASP
RAS
tT
t CSH
t HPC
t CP
t CAS
CAS
tHPC
t CP
t HPC
t CP
t CAS
t CAS
t CRP
tRSH
tCAS
t RCHC
t RRH
t RCH
t RCS
WE
Address
L
tASR
tRAH tASC
Row
tCAH
Column 1
t ASC t CAH
t ASC t CAH
Column 2
t CAL
t RAL
t CAH
tASC
Column 3
t CAL
t WED
Column 4
t CAL
tRDD
t CAL
tDZC
tCDD
Pr
High-Z
Din
tCOL
tDZO
t OEP
OE
tOEA
tOED
tOEZ
tOFR
tOHR
tOEZ
tCPA
tAA
;
tCAC
tAA
tCPA
tAA
tCAC
tCPA
tAA
tCAC
tCOP
tOEP
Dout
tOEZ
uc
od
tDOH
tRAC
tOHO
tOEA
tDOH
tOHO
Dout 1
Dout 2
Dout 2
Dout 3
tCAC
tOHO
tOFF
tOH
tOEA
Dout 4
t
Data Sheet E0097H10
25
HM5164405F Series, HM5165405F Series
EDO Page Mode Early Write Cycle
EO
tRASP
tRP
RAS
tT
tCSH
tASR
Row
tRAH
tASC
Column 1
tWCS
WE
Dout
tRSH
tCAS
tASC
tCAH
Column 2
tCP
tCAS
tASC
tWCH
tDH
Din 1
tWCS
tWCH
tCRP
tCAH
Column N
tWCS
tWCH
uc
od
tDS
Din
tCAH
tCP
Pr
Address
L
CAS
tHPC
tCAS
tRCD
tDS
tDH
Din 2
tDS
tDH
Din N
High-Z*
* t WCS
t WCS (min)
t
Data Sheet E0097H10
26
HM5164405F Series, HM5165405F Series
EDO Page Mode Delayed Write Cycle*18
EO
tRASP
tRP
RAS
tT
tCP
tRCD
tHPC
tCAS
tCAS
L
CAS
tCRP
tCP
tCSH
tRSH
tCAS
tRAD
tASR
tASC
tCAH
tASC
tCAH
Column 1
Column 2
tRAH
Address
Row
tASC
tCAH
Column N
Pr
tCWL
tCWL
tRCS
tRCS
WE
tWP
tDZC tDS
tDH
uc
od
tDZO tOED
tWP
tDZC tDS
tDH
Din
1
Din
tRWL
tRCS
tWP
tDZC tDS
tDH
tCWL
Din
2
tDZO
tOED
tOEP
tOEH
tDZO
tOED
tOEP
tOEH
;
tOEP
tOEH
Din
N
OE
tCLZ
tCLZ
tOEZ
Dout
Invalid Dout
tCLZ
tOEZ
Invalid Dout
tOEZ
High-Z
Invalid Dout
t
Data Sheet E0097H10
27
HM5164405F Series, HM5165405F Series
EDO Page Mode Read-Modify-Write Cycle*18
EO
t RASP
t RP
RAS
tT
t RCD
t RSH
t CP
t CAS
t CAS
L
CAS
t HPRWC
t CP
t CRP
t CAS
t RAD
t ASR
Address
t ASC
t RAH
Row
t ASC
t CAH
t CAH
Column 1
Column 2
t CWL
t AWD
t CPW
t OEP
t OEH
t CWL
t AWD
t RWL
t CWD
t WP
t
t DZC DS
t DH
Din
1
t OED
t CPW
uc
od
t WP
t
t DZC DS
t DH
t DZO
t RCS
t CWD
t WP
t
t DZC DS
Din
t CWL
t AWD
t RCS
t CWD
t RCS
Column N
Pr
t RWD
WE
t ASC
t CAH
t DH
Din
2
t OED
t DZO
t OEP
t OEH
OE
t OED
t DZO
t OEP
t OEH
t OHO
t OHO
;
;
t OHO
Din
N
t OEA
t CAC
t OEA
t CAC
t AA
t AA
t CPA
t RAC
t OEZ
t CLZ
t CLZ
t OEA
t CAC
t AA
t CPA
t OEZ
t OEZ
t CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
t
Data Sheet E0097H10
28
HM5164405F Series, HM5165405F Series
EDO Page Mode Mix Cycle (1)* 20
EO
t RP
t RASP
RAS
tT
t CAS
CAS
t CRP
t CP
t CP
t CP
t CAS
tCAS
tCAS
t CSH
tCWL
tRSH
t RCD
t WCS
t ASC
tRAH
tASR
Address
Row
tCAH
Column 1
t RRH
t RCH
t RCS
t RCS
tCPW
tAWD
L
WE
t WCH
t ASC t CAH
tASC t CAH
Column 2
Column 3
tWP
tASC
t RAL
t CAH
Column 4
t CAL
Din
Din 1
tRDD
tCDD
t CAL
Pr
t DS
t DH
t DS
High-Z
t DH
Din 3
;
tOED
tOEP
OE
tCAC
Dout
tCPA
t OEZ
tOFR
tWEZ
tCPA
tAA
tOEZ
uc
od
tCPA
tAA
tOEA
tWED
tAA
t DOH
Dout 2
tCAC t OHO
Dout 3
tCAC
tOHO
tOEA
tOFF
tOH
Dout 4
t
Data Sheet E0097H10
29
HM5164405F Series, HM5165405F Series
EDO Page Mode Mix Cycle (2) *20
EO
t RP
t RASP
RAS
tT
t CSH
t CAS
CAS
t RCD
Address
Row
t RCH
tWCS t WCH
tCAH
Column 1
tCAS
tCWL
t ASC t CAH
Column 2
Column 3
t RRH
t RCH
tWP
tCPW
t ASC t CAH
tRSH
t RCS
t RCS
L
t ASC
tRAH
tASR
tCAS
t RCHR
t RCS
WE
t CAS
t CRP
t CP
t CP
t CP
t RAL
t CAH
tASC
Column 4
t CAL
t CAL
t DS
Pr
t DS
High-Z
Din
t DH
Din 2
tRDD
tCDD
t DH
Din 3
t OEP
t OEP
tOED
tOED
tCOP
tWED
tCOL
OE
t OEA
tOEA
tCAC
tOEZ
t OHO
Dout
tCPA
tAA
tCAC
tRAC
Dout 1
tOFR
tWEZ
tCPA
uc
od
tAA
tOEZ
t OHO
Dout 3
tAA
tCAC
tOEZ
tOEA
tOFF
tOH
tOHO
Dout 4
t
Data Sheet E0097H10
30
HM5164405F Series, HM5165405F Series
Self Refresh Cycle (L-version)* 23, 24, 25
EO
tRASS
tRP
tRPS
RAS
tT
;
;
tRPC
tCP
L
CAS
tCRP
tCHS
tCSR
tWRP
tWRH
WE
;
Pr
tOFR
tOFF
Dout
High-Z
t
uc
od
Data Sheet E0097H10
31
HM5164405F Series, HM5165405F Series
Package Dimensions
EO
HM5164405FJ/FLJ Series
HM5165405FJ/FLJ Series (CP-32DC)
*0.43 ± 0.10
0.41 ± 0.08
2.55 ± 0.12
Pr
1.165 Max
16
3.50 ± 0.26
0.74
11.18 ± 0.13
L
1
17
0.90 ± 0.26
20.95
21.38 Max
10.16 ± 0.13
32
Unit: mm
9.40 ± 0.25
1.27
0.10
CP-32DC
—
Conforms
1.2 g
t
uc
od
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
Data Sheet E0097H10
32
HM5164405F Series, HM5165405F Series
EO
HM5164405FTT/FLTT Series
HM5165405FTT/FLTT Series (TTP-32DC)
Unit: mm
20.95
21.35 Max
L
16
1.27
0.21
M
11.76 ± 0.20
1.15 Max
*0.145 ± 0.05
0.125 ± 0.04
0.10
Pr
1.20 Max
0.80
0° – 5° 0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
*Dimension including the plating thickness
Base material dimension
0.68
*0.42 ± 0.08
0.40 ± 0.06
0.13 ± 0.05
1
17
10.16
32
TTP-32DC
Conforms
—
0.51 g
t
uc
od
Data Sheet E0097H10
33
HM5164405F Series, HM5165405F Series
Cautions
EO
L
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any
third party’s patent, copyright, trademark, or other intellectual property rights for information contained
in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third
party’s rights, including intellectual property rights, in connection with use of the information contained
in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause
risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally
foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such
as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily
injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
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Data Sheet E0097H10
34
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