SPANSION MB84VD22398EJ-90 32m (x16) flash memory 16m (x16) sram interface fcram Datasheet

TM
SPANSION MCP
Data Sheet
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50212-3E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
32M (×16) FLASH MEMORY &
16M (×16) SRAM Interface FCRAM
MB84VD22386EJ/VD22387EJ/VD22388EJ-85/90
MB84VD22396EJ/VD22397EJ/VD22398EJ-85/90
■ FEATURES
• Power Supply Voltage of 2.7 V to 3.1 V for FCRAM
• Power Supply Voltage of 2.7 V to 3.3 V for Flash
• High Performance
85 ns maximum access time (Flash)
85 ns maximum access time (FCRAM)
• Operating Temperature
–30 °C to +85 °C
• Package 71-ball BGA
(Continued)
■ PRODUCT LINE-UP
Power Supply Voltage (V)
Flash Memory
FCRAM
VCCf* = 2.7 to 3.3
VCCs* = 2.7 to 3.1
Max Address Access Time (ns)
85
85
Max CE Access Time (ns)
85
85
Max OE Access Time (ns)
35
50
*: Both VCCf and VCCs must be the same level when either part is being accessed.
■ PACKAGE
71-ball plastic BGA
(BGA-71P-M02)
Note : These guarantee both FCRAM and Flash at 85 ns Access Cycle.
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
1. FLASH MEMORY
• Simultaneous Read/Write Operations (Dual Bank)
Multiple devices available with different bank sizes
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
• Sector Erase Architecture
Eight 4 K words and sixty three 32 K words.
Any combination of sectors can be concurrently erased. The devices also support full chip erase.
• Boot Code Sector Architecture
MB84VD22386EJ/VD22387EJ/VD22388EJ: Top sector
MB84VD22396EJ/VD22397EJ/VD22398EJ: Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
• Hidden ROM (Hi-ROM) Region
64 Kbyte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
Allows protection of boot sectors at VIL, regardless of sector protection/unprotection status
(MB84VD22386EJ/VD22387EJ/VD22388EJ: SA69,SA70
MB84VD22396EJ/VD22397EJ/VD22398EJ: SA0,SA1)
Allows removal of boot sector protection at VIH.
At VACC, program time will reduce by 40%.
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please Refer to “MBM29DL32XTE/BE” Data Sheet in Detailed Function
2. FCRAM
• Power Dissipation
Operating: 20 mA Max
Standby: 70 µA Max
Power Down: 10 µA Max
• Power Down Control by CE2s
• Byte Write Control: LBs (DQ7-DQ0), UBs (DQ15-DQ5)
• 4 Words Address Access Capability
2
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ PIN ASSIGNMENT
(Top View)
Marking side
A8
B8
D8
E8
F8
G8
H8
J8
L8
M8
N.C.
N.C.
A15
N.C.
N.C.
A16
Vccf
Vss
N.C.
N.C.
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
N.C.
N.C.
A11
A12
A13
A14
N.C.
DQ15
DQ7
DQ14
N.C.
N.C.
C6
D6
E6
F6
G6
H6
J6
K6
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
C5
D5
E5
H5
J5
K5
WE
CE2s
A20
DQ4
Vccs
N.C.
C4
D4
E4
H4
J4
K4
RY/BY
DQ3
Vccf
DQ11
WP/ACC RESET
C3
D3
E3
F3
G3
H3
J3
K3
LBs
UBs
A18
A17
DQ1
DQ9
DQ10
DQ2
A2
C2
D2
E2
F2
G2
H2
J2
K2
L2
M2
N.C.
A7
A6
A5
A4
VSS
OE
DQ0
DQ8
N.C.
N.C.
A1
B1
D1
E1
F1
G1
H1
J1
L1
M1
N.C.
N.C.
A3
A2
A1
A0
CEf
CE1s
N.C.
N.C.
(BGA-71P-M02)
3
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ PIN DESCRIPTIONS
4
Pin Name
Input/Output
Function
A19 to A0
I
Address Inputs (Common)
A20
I
Address Input (Flash)
DQ15 to DQ0
I/O
CEf
I
Chip Enable (Flash)
CE1s
I
Chip Enable (FCRAM)
CE2s
I
Chip Enable (FCRAM)
OE
I
Output Enable (Common)
WE
I
Write Enable (Common)
RY/BY
O
Ready/Busy Outputs (Flash) Open Drain Output
UBs
I
Upper Byte Control (FCRAM)
LBs
I
Lower Byte Control (FCRAM)
RESET
I
Hardware Reset Pin/Sector Protection Unlock (Flash)
WP/ACC
I
Write Protect / Acceleration (Flash)
N.C.
—
VSS
Power
Device Ground (Common)
VCCf
Power
Device Power Supply (Flash)
VCCs
Power
Device Power Supply (FCRAM)
Data Inputs/Outputs (Common)
No Internal Connection
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ BLOCK DIAGRAM
VCCf
VSS
A20 to A0
RY/BY
A20 to A0
WP/ACC
32 M bit
Flash Memory
RESET
CEf
DQ15 to DQ0
DQ15 to DQ0
VCCs
VSS
A19 to A0
DQ15 to DQ0
LBs
UBs
WE
OE
CE1s
CE2s
16 M bit
FCRAM
5
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ DEVICE BUS OPERATION
Operation *1, *2
Full Standby
CEf CE1s CE2s OE WE LBs UBs DQ7 to DQ0 DQ15 to DQ8 RESET
H
H
H
X
X
X
X
High-Z
High-Z
H
L
H
H
H
X
X
High-Z
High-Z
L
H
H
H
H
X
X
High-Z
High-Z
Read from Flash *4
L
H
H
L
H
X
X
DOUT
Write to Flash
L
H
H
H
L
X
X
Read from FCRAM *5
H
L
H
L
H
X
Output Disable *3
Write to FCRAM
H
L
H
H
L
H
X
H
X
DOUT
H
X
DIN
DIN
H
X
X
DOUT
DOUT
H
X
L
L
DIN
DIN
H
L
High-Z
DIN
H
X
L
H
DIN
High-Z
Temporary Sector
Group Unprotection *6
X
X
X
X
X
X
X
X
X
VID
X
Flash Hardware Reset
X
H
H
X
X
X
X
High-Z
High-Z
L
X
Boot Block Sector Write
Protection
X
X
X
X
X
X
X
X
X
X
L
FCRAM Power Down *8
X
X
L
X
X
X
X
X
X
X
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See “
DC CHARACTERISTICS” for voltage levels.
*1: Other operations except for indicated this column are prohibited.
*2: Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
*3: FCRAM Output Disable condition should not be kept longer than 1 µs.
*4: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*5: FCRAM Byte control at Read operation is not supported.
*6: Also used for the extended sector group protections.
*7: Protect “outermost” 2 × 8 Kbytes (4 words) on both ends of the boot block sectors.
*8: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.
6
WP/ACC
*7
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• Eight 4 K words, and sixty three 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
Bank 1
MB84VD22386EJ
Bank 1
MB84VD22387EJ
Bank 1
MB84VD22388EJ
Bank 2
MB84VD22386EJ
Bank 2
MB84VD22387EJ
Bank 2
MB84VD22388EJ
SA70 : 8KB (4KW)
SA69 : 8KB (4KW)
SA68 : 8KB (4KW)
SA67 : 8KB (4KW)
SA66 : 8KB (4KW)
SA65 : 8KB (4KW)
SA64 : 8KB (4KW)
SA63 : 8KB (4KW)
SA62 : 64KB (32KW)
SA61 : 64KB (32KW)
SA60 : 64KB (32KW)
SA59 : 64KB (32KW)
SA58 : 64KB (32KW)
SA57 : 64KB (32KW)
SA56 : 64KB (32KW)
SA55 : 64KB (32KW)
SA54 : 64KB (32KW)
SA53 : 64KB (32KW)
SA52 : 64KB (32KW)
SA51 : 64KB (32KW)
SA50 : 64KB (32KW)
SA49 : 64KB (32KW)
SA48 : 64KB (32KW)
SA47 : 64KB (32KW)
SA46 : 64KB (32KW)
SA45 : 64KB (32KW)
SA44 : 64KB (32KW)
SA43 : 64KB (32KW)
SA42 : 64KB (32KW)
SA41 : 64KB (32KW)
SA40 : 64KB (32KW)
SA39 : 64KB (32KW)
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 64KB (32KW)
SA6 : 64KB (32KW)
SA5 : 64KB (32KW)
SA4 : 64KB (32KW)
SA3 : 64KB (32KW)
SA2 : 64KB (32KW)
SA1 : 64KB (32KW)
SA0 : 64KB (32KW)
1FFFFFh
1FF000h
1FE000h
1FD000h
1FC000h
1FB000h
1FA000h
1F9000h
1F8000h
1F0000h
1E8000h
1E0000h
1D8000h
1D0000h
1C8000h
1C0000h
1B8000h
1B0000h
1A8000h
1A0000h
198000h
190000h
188000h
180000h
178000h
170000h
168000h
160000h
158000h
150000h
148000h
140000h
138000h
130000h
128000h
120000h
118000h
110000h
108000h
100000h
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
000000h
MB84VD22386EJ/VD22387EJ/VD22388EJ Sector Architecture (Top Boot Block)
(Continued)
7
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Bank 2
MB84VD22398EJ
Bank 2
MB84VD22397EJ
Bank 2
MB84VD22396EJ
Bank 1
MB84VD22398EJ
Bank 1
MB84VD22397EJ
Bank 1
MB84VD22396EJ
SA70 : 64KB (32KW)
SA69 : 64KB (32KW)
SA68 : 64KB (32KW)
SA67 : 64KB (32KW)
SA66 : 64KB (32KW)
SA65 : 64KB (32KW)
SA64 : 64KB (32KW)
SA63 : 64KB (32KW)
SA62 : 64KB (32KW)
SA61 : 64KB (32KW)
SA60 : 64KB (32KW)
SA59 : 64KB (32KW)
SA58 : 64KB (32KW)
SA57 : 64KB (32KW)
SA56 : 64KB (32KW)
SA55 : 64KB (32KW)
SA54 : 64KB (32KW)
SA53 : 64KB (32KW)
SA52 : 64KB (32KW)
SA51 : 64KB (32KW)
SA50 : 64KB (32KW)
SA49 : 64KB (32KW)
SA48 : 64KB (32KW)
SA47 : 64KB (32KW)
SA46 : 64KB (32KW)
SA45 : 64KB (32KW)
SA44 : 64KB (32KW)
SA43 : 64KB (32KW)
SA42 : 64KB (32KW)
SA41 : 64KB (32KW)
SA40 : 64KB (32KW)
SA39 : 64KB (32KW)
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 8KB (4KW)
SA6 : 8KB (4KW)
SA5 : 8KB (4KW)
SA4 : 8KB (4KW)
SA3 : 8KB (4KW)
SA2 : 8KB (4KW)
SA1 : 8KB (4KW)
SA0 : 8KB (4KW)
1FFFFFh
1F8000h
1F0000h
1E8000h
1E0000h
1D8000h
1D0000h
1C8000h
1C0000h
1B8000h
1B0000h
1A8000h
1A0000h
198000h
190000h
188000h
180000h
178000h
170000h
168000h
160000h
158000h
150000h
148000h
140000h
138000h
130000h
128000h
120000h
118000h
110000h
108000h
100000h
0F8000h
0F0000h
0E8000h
0E0000h
0D8000h
0D0000h
0C8000h
0C0000h
0B8000h
0B0000h
0A8000h
0A0000h
098000h
090000h
088000h
080000h
078000h
070000h
068000h
060000h
058000h
050000h
048000h
040000h
038000h
030000h
028000h
020000h
018000h
010000h
008000h
007000h
006000h
005000h
004000h
003000h
002000h
001000h
000000h
MB84VD22396EJ/VD22397EJ/VD22398EJ Sector Architecture (Bottom Boot Block)
8
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22386EJ)
Sector Address
Bank
Bank 2
Sector Bank Address
Address Range
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
SA0
0
0
0
0
0
0
X
X
X
X
000000h to 007FFFh
SA1
0
0
0
0
0
1
X
X
X
X
008000h to 00FFFFh
SA2
0
0
0
0
1
0
X
X
X
X
010000h to 017FFFh
SA3
0
0
0
0
1
1
X
X
X
X
018000h to 01FFFFh
SA4
0
0
0
1
0
0
X
X
X
X
020000h to 027FFFh
SA5
0
0
0
1
0
1
X
X
X
X
028000h to 02FFFFh
SA6
0
0
0
1
1
0
X
X
X
X
030000h to 037FFFh
SA7
0
0
0
1
1
1
X
X
X
X
038000h to 03FFFFh
SA8
0
0
1
0
0
0
X
X
X
X
040000h to 047FFFh
SA9
0
0
1
0
0
1
X
X
X
X
048000h to 04FFFFh
SA10
0
0
1
0
1
0
X
X
X
X
050000h to 057FFFh
SA11
0
0
1
0
1
1
X
X
X
X
058000h to 05FFFFh
SA12
0
0
1
1
0
0
X
X
X
X
060000h to 067FFFh
SA13
0
0
1
1
0
1
X
X
X
X
068000h to 06FFFFh
SA14
0
0
1
1
1
0
X
X
X
X
070000h to 077FFFh
SA15
0
0
1
1
1
1
X
X
X
X
078000h to 07FFFFh
SA16
0
1
0
0
0
0
X
X
X
X
080000h to 087FFFh
SA17
0
1
0
0
0
1
X
X
X
X
088000h to 08FFFFh
SA18
0
1
0
0
1
0
X
X
X
X
090000h to 097FFFh
SA19
0
1
0
0
1
1
X
X
X
X
098000h to 09FFFFh
SA20
0
1
0
1
0
0
X
X
X
X
0A0000h to 0A7FFFh
SA21
0
1
0
1
0
1
X
X
X
X
0A8000h to 0AFFFFh
SA22
0
1
0
1
1
0
X
X
X
X
0B0000h to 0B7FFFh
SA23
0
1
0
1
1
1
X
X
X
X
0B8000h to 0BFFFFh
SA24
0
1
1
0
0
0
X
X
X
X
0C0000h to 0C7FFFh
SA25
0
1
1
0
0
1
X
X
X
X
0C8000h to 0CFFFFh
SA26
0
1
1
0
1
0
X
X
X
X
0D0000h to 0D7FFFh
SA27
0
1
1
0
1
1
X
X
X
X
0D8000h to 0DFFFFh
SA28
0
1
1
1
0
0
X
X
X
X
0E0000h to 0E7FFFh
SA29
0
1
1
1
0
1
X
X
X
X
0E8000h to 0EFFFFh
SA30
0
1
1
1
1
0
X
X
X
X
0F0000h to 0F7FFFh
SA31
0
1
1
1
1
1
X
X
X
X
0F8000h to 0FFFFFh
SA32
1
0
0
0
0
0
X
X
X
X
100000h to 107FFFh
SA33
1
0
0
0
0
1
X
X
X
X
108000h to 10FFFFh
SA34
1
0
0
0
1
0
X
X
X
X
110000h to 117FFFh
(Continued)
9
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank
Bank 2
Bank 1
10
Sector Bank Address
Address Range
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
SA35
1
0
0
0
1
1
X
X
X
X
118000h to 11FFFFh
SA36
1
0
0
1
0
0
X
X
X
X
120000h to 127FFFh
SA37
1
0
0
1
0
1
X
X
X
X
128000h to 12FFFFh
SA38
1
0
0
1
1
0
X
X
X
X
130000h to 137FFFh
SA39
1
0
0
1
1
1
X
X
X
X
138000h to 13FFFFh
SA40
1
0
1
0
0
0
X
X
X
X
140000h to 147FFFh
SA41
1
0
1
0
0
1
X
X
X
X
148000h to 14FFFFh
SA42
1
0
1
0
1
0
X
X
X
X
150000h to 157FFFh
SA43
1
0
1
0
1
1
X
X
X
X
158000h to 15FFFFh
SA44
1
0
1
1
0
0
X
X
X
X
160000h to 167FFFh
SA45
1
0
1
1
0
1
X
X
X
X
168000h to 16FFFFh
SA46
1
0
1
1
1
0
X
X
X
X
170000h to 177FFFh
SA47
1
0
1
1
1
1
X
X
X
X
178000h to 17FFFFh
SA48
1
1
0
0
0
0
X
X
X
X
180000h to 187FFFh
SA49
1
1
0
0
0
1
X
X
X
X
188000h to 18FFFFh
SA50
1
1
0
0
1
0
X
X
X
X
190000h to 197FFFh
SA51
1
1
0
0
1
1
X
X
X
X
198000h to 19FFFFh
SA52
1
1
0
1
0
0
X
X
X
X
1A0000h to 1A7FFFh
SA53
1
1
0
1
0
1
X
X
X
X
1A8000h to 1AFFFFh
SA54
1
1
0
1
1
0
X
X
X
X
1B0000h to 1B7FFFh
SA55
1
1
0
1
1
1
X
X
X
X
1B8000h to 1BFFFFh
SA56
1
1
1
0
0
0
X
X
X
X
1C0000h to 1C7FFFh
SA57
1
1
1
0
0
1
X
X
X
X
1C8000h to 1CFFFFh
SA58
1
1
1
0
1
0
X
X
X
X
1D0000h to 1D7FFFh
SA59
1
1
1
0
1
1
X
X
X
X
1D8000h to 1DFFFFh
SA60
1
1
1
1
0
0
X
X
X
X
1E0000h to 1E7FFFh
SA61
1
1
1
1
0
1
X
X
X
X
1E8000h to 1EFFFFh
SA62
1
1
1
1
1
0
X
X
X
X
1F0000h to 1F7FFFh
SA63
1
1
1
1
1
1
0
0
0
X
1F8000h to 1F8FFFh
SA64
1
1
1
1
1
1
0
0
1
X
1F9000h to 1F9FFFh
SA65
1
1
1
1
1
1
0
1
0
X
1FA000h to 1FAFFFh
SA66
1
1
1
1
1
1
0
1
1
X
1FB000h to 1FBFFFh
SA67
1
1
1
1
1
1
1
0
0
X
1FC000h to 1FCFFFh
SA68
1
1
1
1
1
1
1
0
1
X
1FD000h to 1FDFFFh
SA69
1
1
1
1
1
1
1
1
0
X
1FE000h to 1FEFFFh
SA70
1
1
1
1
1
1
1
1
1
X
1FF000h to 1FFFFFh
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22396EJ)
Sector Address
Bank
Sector Bank Address
A20 A19 A18 A17
SA0
0
0
0
0
SA1
0
0
0
0
SA2
0
0
0
0
SA3
0
0
0
0
SA4
0
0
0
0
SA5
0
0
0
0
SA6
0
0
0
0
Bank 1
SA7
0
0
0
0
SA8
0
0
0
0
SA9
0
0
0
0
SA10
0
0
0
0
SA11
0
0
0
1
SA12
0
0
0
1
SA13
0
0
0
1
SA14
0
0
0
1
SA15
0
0
1
0
SA16
0
0
1
0
SA17
0
0
1
0
SA18
0
0
1
0
SA19
0
0
1
1
SA20
0
0
1
1
SA21
0
0
1
1
SA22
0
0
1
1
SA23
0
1
0
0
SA24
0
1
0
0
SA25
0
1
0
0
SA26
0
1
0
0
Bank 2
SA27
0
1
0
1
SA28
0
1
0
1
SA29
0
1
0
1
SA30
0
1
0
1
SA31
0
1
1
0
SA32
0
1
1
0
SA33
0
1
1
0
SA34
0
1
1
0
SA35
0
1
1
1
SA36
0
1
1
1
SA37
0
1
1
1
SA38
0
1
1
1
Address Range
A16
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
(Continued)
11
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank
Sector Bank Address
A20 A19 A18 A17
SA39
1
0
0
0
SA40
1
0
0
0
SA41
1
0
0
0
SA42
1
0
0
0
SA43
1
0
0
1
SA44
1
0
0
1
SA45
1
0
0
1
SA46
1
0
0
1
SA47
1
0
1
0
SA48
1
0
1
0
SA49
1
0
1
0
SA50
1
0
1
0
SA51
1
0
1
1
SA52
1
0
1
1
SA53
1
0
1
1
SA54
1
0
1
1
Bank 2
SA55
1
1
0
0
SA56
1
1
0
0
SA57
1
1
0
0
SA58
1
1
0
0
SA59
1
1
0
1
SA60
1
1
0
1
SA61
1
1
0
1
SA62
1
1
0
1
SA63
1
1
1
0
SA64
1
1
1
0
SA65
1
1
1
0
SA66
1
1
1
0
SA67
1
1
1
1
SA68
1
1
1
1
SA69
1
1
1
1
SA70
1
1
1
1
12
Address Range
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22387EJ)
Sector Address
Bank
Bank 2
Sector
Bank
Address
Address Range
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
SA0
0
0
0
0
0
0
X
X
X
X
000000h to 007FFFh
SA1
0
0
0
0
0
1
X
X
X
X
008000h to 00FFFFh
SA2
0
0
0
0
1
0
X
X
X
X
010000h to 017FFFh
SA3
0
0
0
0
1
1
X
X
X
X
018000h to 01FFFFh
SA4
0
0
0
1
0
0
X
X
X
X
020000h to 027FFFh
SA5
0
0
0
1
0
1
X
X
X
X
028000h to 02FFFFh
SA6
0
0
0
1
1
0
X
X
X
X
030000h to 037FFFh
SA7
0
0
0
1
1
1
X
X
X
X
038000h to 03FFFFh
SA8
0
0
1
0
0
0
X
X
X
X
040000h to 047FFFh
SA9
0
0
1
0
0
1
X
X
X
X
048000h to 04FFFFh
SA10
0
0
1
0
1
0
X
X
X
X
050000h to 057FFFh
SA11
0
0
1
0
1
1
X
X
X
X
058000h to 05FFFFh
SA12
0
0
1
1
0
0
X
X
X
X
060000h to 067FFFh
SA13
0
0
1
1
0
1
X
X
X
X
068000h to 06FFFFh
SA14
0
0
1
1
1
0
X
X
X
X
070000h to 077FFFh
SA15
0
0
1
1
1
1
X
X
X
X
078000h to 07FFFFh
SA16
0
1
0
0
0
0
X
X
X
X
080000h to 087FFFh
SA17
0
1
0
0
0
1
X
X
X
X
088000h to 08FFFFh
SA18
0
1
0
0
1
0
X
X
X
X
090000h to 097FFFh
SA19
0
1
0
0
1
1
X
X
X
X
098000h to 09FFFFh
SA20
0
1
0
1
0
0
X
X
X
X
0A0000h to 0A7FFFh
SA21
0
1
0
1
0
1
X
X
X
X
0A8000h to 0AFFFFh
SA22
0
1
0
1
1
0
X
X
X
X
0B0000h to 0B7FFFh
SA23
0
1
0
1
1
1
X
X
X
X
0B8000h to 0BFFFFh
SA24
0
1
1
0
0
0
X
X
X
X
0C0000h to 0C7FFFh
SA25
0
1
1
0
0
1
X
X
X
X
0C8000h to 0CFFFFh
SA26
0
1
1
0
1
0
X
X
X
X
0D0000h to 0D7FFFh
SA27
0
1
1
0
1
1
X
X
X
X
0D8000h to 0DFFFFh
SA28
0
1
1
1
0
0
X
X
X
X
0E0000h to 0E7FFFh
SA29
0
1
1
1
0
1
X
X
X
X
0E8000h to 0EFFFFh
SA30
0
1
1
1
1
0
X
X
X
X
0F0000h to 0F7FFFh
SA31
0
1
1
1
1
1
X
X
X
X
0F8000h to 0FFFFFh
(Continued)
13
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank
Bank 2
Bank 1
14
Sector
Bank
Address
Address Range
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
SA32
1
0
0
0
0
0
X
X
X
X
100000h to 107FFFh
SA33
1
0
0
0
0
1
X
X
X
X
108000h to 10FFFFh
SA34
1
0
0
0
1
0
X
X
X
X
110000h to 117FFFh
SA35
1
0
0
0
1
1
X
X
X
X
118000h to 11FFFFh
SA36
1
0
0
1
0
0
X
X
X
X
120000h to 127FFFh
SA37
1
0
0
1
0
1
X
X
X
X
128000h to 12FFFFh
SA38
1
0
0
1
1
0
X
X
X
X
130000h to 137FFFh
SA39
1
0
0
1
1
1
X
X
X
X
138000h to 13FFFFh
SA40
1
0
1
0
0
0
X
X
X
X
140000h to 147FFFh
SA41
1
0
1
0
0
1
X
X
X
X
148000h to 14FFFFh
SA42
1
0
1
0
1
0
X
X
X
X
150000h to 157FFFh
SA43
1
0
1
0
1
1
X
X
X
X
158000h to 15FFFFh
SA44
1
0
1
1
0
0
X
X
X
X
160000h to 167FFFh
SA45
1
0
1
1
0
1
X
X
X
X
168000h to 16FFFFh
SA46
1
0
1
1
1
0
X
X
X
X
170000h to 177FFFh
SA47
1
0
1
1
1
1
X
X
X
X
178000h to 17FFFFh
SA48
1
1
0
0
0
0
X
X
X
X
180000h to 187FFFh
SA49
1
1
0
0
0
1
X
X
X
X
188000h to 18FFFFh
SA50
1
1
0
0
1
0
X
X
X
X
190000h to 197FFFh
SA51
1
1
0
0
1
1
X
X
X
X
198000h to 19FFFFh
SA52
1
1
0
1
0
0
X
X
X
X
1A0000h to 1A7FFFh
SA53
1
1
0
1
0
1
X
X
X
X
1A8000h to 1AFFFFh
SA54
1
1
0
1
1
0
X
X
X
X
1B0000h to 1B7FFFh
SA55
1
1
0
1
1
1
X
X
X
X
1B8000h to 1BFFFFh
SA56
1
1
1
0
0
0
X
X
X
X
1C0000h to 1C7FFFh
SA57
1
1
1
0
0
1
X
X
X
X
1C8000h to 1CFFFFh
SA58
1
1
1
0
1
0
X
X
X
X
1D0000h to 1D7FFFh
SA59
1
1
1
0
1
1
X
X
X
X
1D8000h to 1DFFFFh
SA60
1
1
1
1
0
0
X
X
X
X
1E0000h to 1E7FFFh
SA61
1
1
1
1
0
1
X
X
X
X
1E8000h to 1EFFFFh
SA62
1
1
1
1
1
0
X
X
X
X
1F0000h to 1F7FFFh
SA63
1
1
1
1
1
1
0
0
0
X
1F8000h to 1F8FFFh
SA64
1
1
1
1
1
1
0
0
1
X
1F9000h to 1F9FFFh
SA65
1
1
1
1
1
1
0
1
0
X
1FA000h to 1FAFFFh
SA66
1
1
1
1
1
1
0
1
1
X
1FB000h to 1FBFFFh
SA67
1
1
1
1
1
1
1
0
0
X
1FC000h to 1FCFFFh
SA68
1
1
1
1
1
1
1
0
1
X
1FD000h to 1FDFFFh
SA69
1
1
1
1
1
1
1
1
0
X
1FE000h to 1FEFFFh
SA70
1
1
1
1
1
1
1
1
1
X
1FF000h to 1FFFFFh
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22397EJ)
Sector Address
Bank
Bank Sector
Address
A20 A19 A18
SA0
0
0
0
SA1
0
0
0
SA2
0
0
0
SA3
0
0
0
SA4
0
0
0
SA5
0
0
0
SA6
0
0
0
SA7
0
0
0
SA8
0
0
0
SA9
0
0
0
SA10
0
0
0
Bank 1 SA11
0
0
0
SA12
0
0
0
SA13
0
0
0
SA14
0
0
0
SA15
0
0
1
SA16
0
0
1
SA17
0
0
1
SA18
0
0
1
SA19
0
0
1
SA20
0
0
1
SA21
0
0
1
SA22
0
0
1
SA23
0
1
0
SA24
0
1
0
SA25
0
1
0
SA26
0
1
0
SA27
0
1
0
SA28
0
1
0
SA29
0
1
0
SA30
0
1
0
Bank 2
SA31
0
1
1
SA32
0
1
1
SA33
0
1
1
SA34
0
1
1
SA35
0
1
1
SA36
0
1
1
SA37
0
1
1
SA38
0
1
1
Address Range
A17
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
(Continued)
15
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank
Bank 2
16
Sector
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Bank
Address
A20 A19 A18
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address Range
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22388EJ)
Sector Address
Bank
Bank 2
Sector
Bank
Address Range
Address
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
SA0
0
0
0
0
0
0
X
X
X
X
000000h to 007FFFh
SA1
0
0
0
0
0
1
X
X
X
X
008000h to 00FFFFh
SA2
0
0
0
0
1
0
X
X
X
X
010000h to 017FFFh
SA3
0
0
0
0
1
1
X
X
X
X
018000h to 01FFFFh
SA4
0
0
0
1
0
0
X
X
X
X
020000h to 027FFFh
SA5
0
0
0
1
0
1
X
X
X
X
028000h to 02FFFFh
SA6
0
0
0
1
1
0
X
X
X
X
030000h to 037FFFh
SA7
0
0
0
1
1
1
X
X
X
X
038000h to 03FFFFh
SA8
0
0
1
0
0
0
X
X
X
X
040000h to 047FFFh
SA9
0
0
1
0
0
1
X
X
X
X
048000h to 04FFFFh
SA10
0
0
1
0
1
0
X
X
X
X
050000h to 057FFFh
SA11
0
0
1
0
1
1
X
X
X
X
058000h to 05FFFFh
SA12
0
0
1
1
0
0
X
X
X
X
060000h to 067FFFh
SA13
0
0
1
1
0
1
X
X
X
X
068000h to 06FFFFh
SA14
0
0
1
1
1
0
X
X
X
X
070000h to 077FFFh
SA15
0
0
1
1
1
1
X
X
X
X
078000h to 07FFFFh
SA16
0
1
0
0
0
0
X
X
X
X
080000h to 087FFFh
SA17
0
1
0
0
0
1
X
X
X
X
088000h to 08FFFFh
SA18
0
1
0
0
1
0
X
X
X
X
090000h to 097FFFh
SA19
0
1
0
0
1
1
X
X
X
X
098000h to 09FFFFh
SA20
0
1
0
1
0
0
X
X
X
X
0A0000h to 0A7FFFh
SA21
0
1
0
1
0
1
X
X
X
X
0A8000h to 0AFFFFh
SA22
0
1
0
1
1
0
X
X
X
X
0B0000h to 0B7FFFh
SA23
0
1
0
1
1
1
X
X
X
X
0B8000h to 0BFFFFh
SA24
0
1
1
0
0
0
X
X
X
X
0C0000h to 0C7FFFh
SA25
0
1
1
0
0
1
X
X
X
X
0C8000h to 0CFFFFh
SA26
0
1
1
0
1
0
X
X
X
X
0D0000h to 0D7FFFh
SA27
0
1
1
0
1
1
X
X
X
X
0D8000h to 0DFFFFh
SA28
0
1
1
1
0
0
X
X
X
X
0E0000h to 0E7FFFh
SA29
0
1
1
1
0
1
X
X
X
X
0E8000h to 0EFFFFh
SA30
0
1
1
1
1
0
X
X
X
X
0F0000h to 0F7FFFh
SA31
0
1
1
1
1
1
X
X
X
X
0F8000h to 0FFFFFh
(Continued)
17
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank
Bank 1
18
Sector
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Bank
Address Range
Address
A20
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A17
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
A16
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
A15
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1F8FFFh
1F9000h to 1F9FFFh
1FA000h to 1FAFFFh
1FB000h to 1FBFFFh
1FC000h to 1FCFFFh
1FD000h to 1FDFFFh
1FE000h to 1FEFFFh
1FF000h to 1FFFFFh
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Address Tables (MB84VD22398EJ)
Sector Address
Bank
Bank 1
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
Bank
Address Range
Address
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A17
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A16
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A15
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A14
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A13
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A12
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
(Continued)
19
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Sector Address
Bank
Bank 2
20
Sector
Bank
Address Range
Address
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
SA39
1
0
0
0
0
0
X
X
X
X
100000h to 107FFFh
SA40
1
0
0
0
0
1
X
X
X
X
108000h to 10FFFFh
SA41
1
0
0
0
1
0
X
X
X
X
110000h to 117FFFh
SA42
1
0
0
0
1
1
X
X
X
X
118000h to 11FFFFh
SA43
1
0
0
1
0
0
X
X
X
X
120000h to 127FFFh
SA44
1
0
0
1
0
1
X
X
X
X
128000h to 12FFFFh
SA45
1
0
0
1
1
0
X
X
X
X
130000h to 137FFFh
SA46
1
0
0
1
1
1
X
X
X
X
138000h to 13FFFFh
SA47
1
0
1
0
0
0
X
X
X
X
140000h to 147FFFh
SA48
1
0
1
0
0
1
X
X
X
X
148000h to 14FFFFh
SA49
1
0
1
0
1
0
X
X
X
X
150000h to 157FFFh
SA50
1
0
1
0
1
1
X
X
X
X
158000h to 15FFFFh
SA51
1
0
1
1
0
0
X
X
X
X
160000h to 167FFFh
SA52
1
0
1
1
0
1
X
X
X
X
168000h to 16FFFFh
SA53
1
0
1
1
1
0
X
X
X
X
170000h to 177FFFh
SA54
1
0
1
1
1
1
X
X
X
X
178000h to 17FFFFh
SA55
1
1
0
0
0
0
X
X
X
X
180000h to 187FFFh
SA56
1
1
0
0
0
1
X
X
X
X
188000h to 18FFFFh
SA57
1
1
0
0
1
0
X
X
X
X
190000h to 197FFFh
SA58
1
1
0
0
1
1
X
X
X
X
198000h to 19FFFFh
SA59
1
1
0
1
0
0
X
X
X
X
1A0000h to 1A7FFFh
SA60
1
1
0
1
0
1
X
X
X
X
1A8000h to 1AFFFFh
SA61
1
1
0
1
1
0
X
X
X
X
1B0000h to 1B7FFFh
SA62
1
1
0
1
1
1
X
X
X
X
1B8000h to 1BFFFFh
SA63
1
1
1
0
0
0
X
X
X
X
1C0000h to 1C7FFFh
SA64
1
1
1
0
0
1
X
X
X
X
1C8000h to 1CFFFFh
SA65
1
1
1
0
1
0
X
X
X
X
1D0000h to 1D7FFFh
SA66
1
1
1
0
1
1
X
X
X
X
1D8000h to 1DFFFFh
SA67
1
1
1
1
0
0
X
X
X
X
1E0000h to 1E7FFFh
SA68
1
1
1
1
0
1
X
X
X
X
1E8000h to 1EFFFFh
SA69
1
1
1
1
1
0
X
X
X
X
1F0000h to 1F7FFFh
SA70
1
1
1
1
1
1
X
X
X
X
1F8000h to 1FFFFFh
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Group Addresses (MB84VD22386EJ/VD22387EJ/VD22388EJ)
(Top Boot Block)
Sector Group
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
0
X
X
X
SA0
0
1
1
0
X
X
X
SA1 to SA3
1
1
SGA1
0
0
0
0
SGA2
0
0
0
1
X
X
X
X
X
SA4 to SA7
SGA3
0
0
1
0
X
X
X
X
X
SA8 to SA11
SGA4
0
0
1
1
X
X
X
X
X
SA12 to SA15
SGA5
0
1
0
0
X
X
X
X
X
SA16 to SA19
SGA6
0
1
0
1
X
X
X
X
X
SA20 to SA23
SGA7
0
1
1
0
X
X
X
X
X
SA24 to SA27
SGA8
0
1
1
1
X
X
X
X
X
SA28 to SA31
SGA9
1
0
0
0
X
X
X
X
X
SA32 to SA35
SGA10
1
0
0
1
X
X
X
X
X
SA36 to SA39
SGA11
1
0
1
0
X
X
X
X
X
SA40 to SA43
SGA12
1
0
1
1
X
X
X
X
X
SA44 to SA47
SGA13
1
1
0
0
X
X
X
X
X
SA48 to SA51
SGA14
1
1
0
1
X
X
X
X
X
SA52 to SA55
SGA15
1
1
1
0
X
X
X
X
X
SA56 to SA59
0
0
0
1
X
X
X
SA60 to SA62
1
0
SGA16
1
1
1
1
SGA17
1
1
1
1
1
1
0
0
0
SA63
SGA18
1
1
1
1
1
1
0
0
1
SA64
SGA19
1
1
1
1
1
1
0
1
0
SA65
SGA20
1
1
1
1
1
1
0
1
1
SA66
SGA21
1
1
1
1
1
1
1
0
0
SA67
SGA22
1
1
1
1
1
1
1
0
1
SA68
SGA23
1
1
1
1
1
1
1
1
0
SA69
SGA24
1
1
1
1
1
1
1
1
1
SA70
21
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Sector Group Addresses (MB84VD22396EJ/VD22397EJ/VD22398EJ)
(Bottom Boot Block)
Sector Group
A20
A19
A18
A17
A16
A15
A14
A13
A12
Sectors
SGA0
0
0
0
0
0
0
0
0
0
SA0
SGA1
0
0
0
0
0
0
0
0
1
SA1
SGA2
0
0
0
0
0
0
0
1
0
SA2
SGA3
0
0
0
0
0
0
0
1
1
SA3
SGA4
0
0
0
0
0
0
1
0
0
SA4
SGA5
0
0
0
0
0
0
1
0
1
SA5
SGA6
0
0
0
0
0
0
1
1
0
SA6
SGA7
0
0
0
0
0
0
1
1
1
SA7
0
1
1
0
X
X
X
SA8 to SA10
1
1
SGA8
0
0
0
SGA9
0
0
0
1
X
X
X
X
X
SA11 to SA14
SGA10
0
0
1
0
X
X
X
X
X
SA15 to SA18
SGA11
0
0
1
1
X
X
X
X
X
SA19 to SA22
SGA12
0
1
0
0
X
X
X
X
X
SA23 to SA26
SGA13
0
1
0
1
X
X
X
X
X
SA27 to SA30
SGA14
0
1
1
0
X
X
X
X
X
SA31 to SA34
SGA15
0
1
1
1
X
X
X
X
X
SA35 to SA38
SGA16
1
0
0
0
X
X
X
X
X
SA39 to SA42
SGA17
1
0
0
1
X
X
X
X
X
SA43 to SA46
SGA18
1
0
1
0
X
X
X
X
X
SA47 to SA50
SGA19
1
0
1
1
X
X
X
X
X
SA51 to SA54
SGA20
1
1
0
0
X
X
X
X
X
SA55 to SA58
SGA21
1
1
0
1
X
X
X
X
X
SA59 to SA62
SGA22
1
1
1
0
X
X
X
X
X
SA63 to SA66
0
0
0
1
X
X
X
SA67 to SA69
1
0
1
1
X
X
X
SA70
SGA23
SGA24
22
0
1
1
1
1
1
1
1
1
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Flash Memory Autoselect Codes
A19 to A12
A6
A1
A0
Code (HEX)
BA
VIL
VIL
VIL
04h
MB84VD22386EJ
BA
VIL
VIL
VIH
2255h
MB84VD22396EJ
BA
VIL
VIL
VIH
2256h
MB84VD22387EJ
BA
VIL
VIL
VIH
2250h
MB84VD22397EJ
BA
VIL
VIL
VIH
2253h
MB84VD22388EJ
BA
VIL
VIL
VIH
225Ch
MB84VD22398EJ
BA
VIL
VIL
VIH
225Fh
Sector Group Address
VIL
VIH
VIL
01h *
Type
Manufacturer’s Code
Device Code
Sector Group protect
*: Output 01h at protected sector address and output 00h at unprotected sector address.
23
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
Flash Memory Command Definitions
Bus
First Bus
Second Bus
Write Write Cycle
Write Cycle
Cycles
Req’d Addr. Data Addr. Data
Command
Sequence
Third Bus
Write Cycle
Addr.
Fourth Bus
Read/Write
Cycle
Fifth Bus
Sixth Bus
Write Cycle Write Cycle
Data Addr. Data Addr. Data Addr. Data
Read/Reset *1
1
XXXh
F0h
—
—
—
—
—
—
—
—
—
—
Read/Reset *1
3
555h
AAh
2AAh
55h
555h
F0h
RA
RD
—
—
—
—
Autoselect
3
555h
AAh
2AAh
55h
(BA)
555h
90h
—
—
—
—
—
—
Program
4
555h
AAh
2AAh
55h
555h
A0h
PA
PD
—
—
—
—
Chip Erase
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
555h
10h
Sector Erase
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
SA
30h
Sector Erase Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
Sector Erase Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
Program Suspend
1
BA
B0h
—
—
—
—
—
—
—
—
—
—
Program Resume
1
BA
30h
—
—
—
—
—
—
—
—
—
—
Set to Fast Mode
3
555h
AAh
2AAh
55h
555h
20h
—
—
—
—
—
—
Fast Program *2
2
XXXh
A0h
PA
PD
—
—
—
—
—
—
—
—
Reset from Fast Mode
*2
2
BA
90h
XXXh
F0h*6
—
—
—
—
—
—
—
—
Extended Sector
Group Protection *3
4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
—
—
—
—
Query *4
1
55h
98h
—
—
—
—
—
—
—
—
—
—
3
555h
AAh
2AAh
55h
555h
88h
—
—
—
—
—
—
4
555h
AAh
2AAh
55h
555h
A0h
PA
PD
—
—
—
—
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
HRA
30h
4
555h
AAh
2AAh
55h
(HRBA)
555h
90h
XXXh
00h
—
—
—
—
Hi-ROM Entry
Hi-ROM Program *
Hi-ROM Erase *
Hi-ROM Exit *5
5
5
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2: This command is valid during Fast Mode.
*3: This command is valid while RESET=VID.
*4: The valid Address is A6 to A0.
*5: This command is valid during Hi-ROM mode.
*6: The data “00h” is also acceptable.
Notes: Address bits A20 to A11 = X = “H” or “L” for all address commands except for Program Address (PA),
Sector Address (SA), and Bank Address (BA).
Bus operations are defined in “■ DEVICE BUS OPERATION”.
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank address (A20 to A15)
SPA = Sector group address to be protected. Set sector group address (SPA) and (A6, A1, A0) = (0, 1, 0).
24
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
HRA= Address of the Hidden-ROM area.
MB84VD22386EJ/VD22387EJ/VD22388EJ (Top Boot Type)
Word mode: 1F8000h to 1FFFFFh
Byte mode: 3F0000h to 3FFFFFh
MB84VD22396EJ/VD22397EJ/VD22398EJ (Bottom Boot Type)
Word mode: 000000h to 007FFFh
Byte mode: 000000h to 00FFFFh
HRBA = Bank address of the Hidden-ROM area
MB84VD22386EJ/VD22387EJ/VD22388EJ (Top Boot Type)
A20 = A19 = A18 = A17 = A16 = A15 = 1
MB84VD22396EJ/VD22397EJ/VD22398EJ (Bottom Boot Type)
A20 = A19 = A18 = A17 = A16 = A15 = 0
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA.
SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h
at unprotected sector addresses.
The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0
25
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Min
Max
Tstg
–55
+125
°C
Ambient Temperature with Power Applied
TA
–30
+85
°C
Voltage with Respect to Ground All pins *1
VIN, VOUT
–0.3
VCCf +0.3
V
VCCs +0.3
V
VCCf
–0.2
+3.6
V
VCCs
–0.2
+3.3
V
RESET *
VIN
–0.5
+13.0
V
WP/ACC *3
VIN
–0.5
+10.5
V
Storage Temperature
VCCf Supply *1
1
VCCs Supply *
2
*1: Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot
VSS to –1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCs + 0.3
V. During voltage transitions, input or I/O pins may overshoot to VCCf + 1.0 V or VCCs + 1.0 V for periods of up to 5 ns.
*2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pin may undershoot VSS
to –2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V.
Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
*3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +10.5 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min
Max
TA
–30
+85
°C
VCCf Supply Voltage
VCCf
+2.7
+3.3
V
VCCs Supply Voltage
VCCs
+2.7
+3.1
V
Ambient Temperature
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
26
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ DC CHARACTERISTICS
Parameter
Symbol
Value
Conditions
Min
Typ
Max
Unit
Input Leakage Current
ILI
VIN = VSS to VCC
–1.0
—
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCC
–1.0
—
+1.0
µA
RESET Inputs Leakage
Current
ILIT
VCC = VCC Max,
RESET = 12.5 V
—
—
35
µA
ACC Input Leakage
Current
ILIA
VCC = VCC Max,
WP/ACC = VACC Max
—
—
20
mA
Flash VCC Active Current
(Read) *1
ICC1f
CEf = VIL,
OE = VIH
tCYCLE = 5 MHz
—
—
18
mA
tCYCLE = 1 MHz
—
—
7
mA
Flash VCC Active Current
(Program/Erase) *2
ICC2f
CEf = VIL, OE = VIH
—
—
35
mA
Flash VCC Active Current
(Read-While-Program) *5
ICC3f
CEf = VIL, OE = VIH
—
—
53
mA
Flash VCC Active Current
(Read-While-Erase) *5
ICC4f
CEf = VIL, OE = VIH
—
—
53
mA
Flash VCC Active Current
(Erase-Suspend-Program)
ICC5f
CEf = VIL, OE = VIH
—
—
35
mA
15
20
ICC1s
VCCs = VCCs Max,
tRC / tWC =Min
CE1s = VIL, CE2s = VIH,
VIN = VIH or VIL, IOUT = 0 mA tRC / tWC =Max
—
FCRAM VCC Active Current
—
2.5
3.0
Flash VCC Standby Current
ISB1f
VCCf = VCCf Max, CEf = VCCf ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V
—
1
5
µA
Flash VCC Standby Current
(RESET)
ISB2f
VCCf = VCCf Max, RESET = VSS ± 0.3 V,
WP/ACC = VCCf± 0.3 V
—
1
5
µA
Flash VCC Current (Automatic
Sleep Mode) *3
ISB3f
VCCf = VCCf Max, CEf = VSS ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V
VIN = VCCf± 0.3 V or VSS ± 0.3 V
—
1
5
µA
FCRAM VCC Standby Current
ISBs
VCCs = VCCs Max,CE1s = CE2s = VIH,
VIN = VIH or VIL, IOUT = 0 mA
—
0.5
1
mA
FCRAM VCC Standby Current
ISB1s
VCCs = VCCs Max,CE1s > VCCs – 0.2 V,
CE2s > VCCs– 0.2 V,
VIN < 0.2 V or VCCs – 0.2 V, IOUT = 0 mA
—
—
70
µA
FCRAM VCC Standby Current
ISB2s
VCCs = VCCs Max,CE1s > VCCs – 0.2 V,
CE2s > VCCs– 0.2 V,
VIN Cycle time = tRC Min, IOUT = 0 mA
—
—
5 *6
mA
FCRAM VCC Power Down
Current
IPDs
VCCs = VCCs Max,
VIN > VCCf – 0.2 V or VIN < 0.2 V
CE2s < 0.2 V, IOUT = 0 mA
—
—
10
µA
mA
(Continued)
27
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Symbol
Conditions
Input Low Level
VIL
Input High Level
Parameter
Value
Typ
Max
—
–0.3
—
0.4
V
VIH
—
2.3
—
VCC+0.3
V
Voltage for Autoselect and
Sector Protection (RESET) *4
VID
—
11.5
—
12.5
V
Voltage for WP/ACC Sector
Protection/Unprotection and
Program Acceleration
VACC
—
8.5
9.0
9.5
V
FCRAM Output Low Level
VOL
VCCs = VCCs Min, IOL =1.0 mA
—
—
0.4
V
FCRAM Output High Level
VOH
VCCs = VCCs Min, IOH = –0.5 mA
2.1
—
—
V
Flash Output Low Level
VOL
VCCf = VCCf Min, IOL = 4.0 mA
—
—
0.45
V
Flash Output High Level
VOH
VCCf = VCCf Min, IOH = –0.1 mA
VCCf–
0.4
—
—
V
Low Vcc Lock-Out
Voltage
VLKO
2.3
—
2.5
V
—
*1: The ICC current listed includes both the DC operating current and the frequency dependent component.
*2: ICC active while Embedded Algorithm (program or erase) is in progress.
*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
*4: Applicable for only VCC applying.
*5: Embedded Algorithm (program or erase) is in progress. (@5MHz)
*6: ISB2s depends on VIN cycle time. Refer to “■ APPENDIX”.
28
Unit
Min
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ AC CHARACTERISTICS
• CE Timing
Parameter
Symbol
JEDEC
Standard
CE Recover Time
—
tCCR
CE Hold Time
—
tCHOLD
Condition
Value
Unit
Min
Max
—
0
—
ns
—
3
—
ns
• Timing Diagram for alternating FCRAM to Flash
CEf
tCCR
tCCR
CE1s
WE
tCHOLD
tCCR
tCHOLD
tCCR
CE2s
29
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Read Only Operations Characteristics (Flash)
Parameter
Symbol
JEDEC
Standard
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
Chip Enable to Output Delay
Value
Unit
Min
Max
—
85
—
ns
tACC
CEf = VIL
OE = VIL
—
85
ns
tELQV
tCE
OE = VIL
—
85
ns
Output Enable to Output Delay
tGLQV
tOE
—
—
35
ns
Chip Enable to Output High-Z
tEHQZ
tDF
—
—
30
ns
Output Enable to Output High-Z
tGHQZ
tDF
—
—
30
ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
tOH
—
0
—
ns
—
tREADY
—
—
20
µs
RESET Pin Low to Read Mode
Note: Test Conditions– Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or VCC
Timing measurement reference level
Input: 0.5×VCC
Output: 0.5×VCC
30
Conditions
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Read Cycle (Flash)
tRC
Address
Address Stable
tACC
CEf
tOE
tDF
OE
tOEH
WE
tCE
tOH
High-Z
Outputs
High-Z
Output Valid
• Hardware Reset/Read Operation Timing Diagram (Flash)
tRC
Address
Address Stable
tACC
CEf
tRH
tRP
tRH
tCE
RESET
tOH
Outputs
High-Z
Output Valid
31
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Erase/Program Operations Characteristics (Flash)
Parameter
Symbol
Value
Unit
JEDEC
Standard
Min
Typ
Max
Write Cycle Time
tAVAV
tWC
85
—
—
ns
Address Setup Time (WE to Addr.)
tAVWL
tAS
0
—
—
ns
—
tASO
15
—
—
ns
tWLAX
tAH
45
—
—
ns
—
tAHT
0
—
—
ns
Data Setup Time
tDVWH
tDS
35
—
—
ns
Data Hold Time
tWHDX
tDH
0
—
—
ns
—
tOES
0
—
—
ns
—
tOEH
0
—
—
ns
10
—
—
ns
CEf High During Toggle Bit Polling
—
tCEPH
20
—
—
ns
OE High During Toggle Bit Polling
—
tOEPH
20
—
—
ns
Read Recover Time Before Write (OE to CEf)
tGHEL
tGHEL
0
—
—
ns
Read Recover Time Before Write (OE to WE)
tGHWL
tGHWL
0
—
—
ns
WE Setup Time (CEf to WE)
tWLEL
tWS
0
—
—
ns
CEf Setup Time (WE to CEf)
tELWL
tCS
0
—
—
ns
WE Hold Time (CEf to WE)
tEHWH
tWH
0
—
—
ns
CEf Hold Time (WE to CEf)
tWHEH
tCH
0
—
—
ns
Write Pulse Width
tWLWH
tWP
35
—
—
ns
CEf Pulse Width
tELEH
tCP
35
—
—
ns
Write Pulse Width High
tWHWL
tWPH
30
—
—
ns
CEf Pulse Width High
tEHEL
tCPH
30
—
—
ns
Word Programming Operation
tWHWH1
tWHWH1
—
16
—
µs
Sector Erase Operation *1
tWHWH2
tWHWH2
—
1
—
s
Address Setup Time to CEf Low During Toggle Bit Polling
Address Hold Time (WE to Addr.)
Address Hold Time from CEf or OE High During Toggle
Bit Polling
Output Enable Setup Time
Output Enable Hold Time
Read
Toggle and Data Polling
(Continued)
32
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
(Continued)
Parameter
Symbol
Value
Unit
JEDEC
Standard
Min
Typ
Max
—
tVCS
50
—
—
µs
—
tVLHT
4
—
—
µs
Rise Time to VID *2
—
tVIDR
500
—
—
ns
Rise Time to VACC
—
tVACCR
500
—
—
ns
Recover Time from RY/BY
—
tRB
0
—
—
ns
RESET Pulse Width
—
tRP
500
—
—
ns
Delay Time from Embedded Output Enable
—
tEOE
—
—
85
ns
RESET Hold Time Before Read
—
tRH
200
—
—
ns
Program/Erase Valid to RY/BY Delay
—
tBUSY
—
—
90
ns
—
tTOW
50
—
—
µs
—
tSPD
—
—
20
µs
VCCf Setup Time
Voltage Transition Time *
Erase Time-out Time *
2
3
Erase Suspend Transition Time *4
*1: This does not include the preprogramming time.
*2: This timing is for Sector Protection Operation.
*3: The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will
start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will initiate the execution
of the Sector Erase command(s).
*4: When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of “tSPD” to suspend the erase operation.
33
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
555h
Address
PA
tWC
tAS
PA
tRC
tAH
CEf
tCH
tCS
tCE
OE
tGHWL
tWP
tWPH
tOE
tWHWH1
WE
tDS
Data
A0h
tDF
tDH
PD
DQ7
DOUT
Notes: • PA is an address of the memory location to be programmed.
• PD is data to be programmed at the word address.
• DQ7 is the output of the data complement written to the device.
• DOUT is the data output written to the device.
• Figure indicates the last two out of four bus cycle sequence.
34
tOH
DOUT
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Address
Data Polling
PA
555h
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CEf
tDS
Data
A0h
tDH
PD
DQ7
DOUT
Notes: • PA is an address of the memory location to be programmed.
• PD is data to be programmed at the word address.
• DQ7 is the output of the data complement written to the device.
• DOUT is the data output written to the device.
• Figure indicates the last two out of four bus cycle sequence.
35
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• AC Waveforms Chip/Sector Erase Operations (Flash)
Address
2AAh
555h
tWC
tAS
555h
555h
2AAh
SA*
tAH
CEf
tCS
tCH
OE
tGHWL
tWP
tWPH
tDS
tDH
WE
AAh
Data
30h for Sector Erase
55h
80h
AAh
55h
tVCS
VCCf
*: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.
36
10h
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tOE
tDF
OE
tOEH
WE
tCE
*
DQ7
Data
DQ7 =
Valid Data
DQ7
High-Z
tWHWH1 or 2
DQ6 to DQ0
Data
DQ6 to DQ0 = Output Flag
tBUSY
DQ6 to DQ0
Valid Data
High-Z
tEOE
RY/BY
* : DQ7 = Valid Data (the device has completed the Embedded operation).
37
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT
tASO
tAHT
tAS
CEf
tCEPH
WE
tOEH
tOEH
tOEPH
OE
tDH
DQ6/DQ2
Data
tOE
Toggle
Data
tCE
Toggle
Data
*
Toggle
Data
tBUSY
RY/BY
* : DQ6 stops toggling (the device has completed the Embedded operation).
38
Stop
Toggling
Output
Valid
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Back-to-back Read/Write Timing Diagram (Flash)
Address
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
BA2
(PA)
BA1
BA2
(PA)
BA2
(555h)
BA1
tAS
BA1
tACC
tAH
tAS
tAHT
tCE
CEf
tOE
tCEPH
OE
tGHWL
tDF
tOEH
tWP
WE
tDS
DQ
Valid
Output
tDH
Valid
Input
(A0h)
tDF
Valid
Output
Valid
Input
Valid
Output
Status
(PD)
Note: This is an example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
39
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
40
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Temporary Sector Group Unprotection (Flash)
VCCf
tVIDR
tVCS
tVLHT
VID
VIH
RESET
CEf
WE
tVLHT
Program or Erase Command Sequence
tVLHT
RY/BY
Unprotection period
• Acceleration Mode Timing Diagram (Flash)
VCCf
tVACCR
tVCS
tVLHT
VID
VIH
WP/ACC
CEf
WE
tVLHT
tVLHT
RY/BY
Acceleration Mode Period
41
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Extended Sector Group Protection (Flash)
VCCf
tVCS
RESET
tVLHT
tVIDR
tWC
Address
tWC
SPAX
SPAX
SPAY
A0
A1
CEf
OE
TIME-OUT
tWP
WE
Data
60h
60h
01h
40h
tOE
SPAX: Sector Group Address to be protected
SPAY : Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min)
42
60h
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ OPERATION (FCRAM)
Parameter
Symbol
Value
Min
Max
Unit
Notes
Read Cycle Time
tRC
90

ns
Chip Enable Access Time
tCE

85
ns
*1, *3
Output Enable Access Time
tOE

45
ns
*1
Chip Enable Access Time
tAA

85
ns
*1, *4
Output Data Hold Time
tOH
5

ns
*1
CE1s Low to Output Low-Z
tCLZ
5

ns
*2
OE Low to Output Low-Z
tOLZ
0

ns
*2
CE1s High to Output High-Z
tCHZ

30
ns
*2
OE High to Output High-Z
tOHZ

25
ns
*2
Address Setup Time to CE1s Low
tASC
−5

ns
*5
tASO
45

ns
*3, *6
tASO[ABS]
10

ns
*7
tAX

5
ns
*4
CE1s Low to Address Hold Time
tCLAH
90

ns
*4
OE Low to Address Hold Time
tOLAH
45

ns
*4, *8
CE1s High to Address Hold Time
tCHAH
−5

ns
OE High to Address Hold Time
tOHAH
−5

ns
CE1s Low to OE Low Delay Time
tCLOL
45
1000
ns
*4, *6, *8, *9
OE Low to CE1s High Delay Time
tOLCH
45

ns
*8
tCP
20

ns
tOP
45
1000
ns
*6, *8, *9
tOP[ABS]
20

ns
*7
Address Setup Time to OE
Address Invalid Time
CE1s High Pulse Width
OE High Pulse Width
*1: The output load is 30 pF.
*2: The output load is 5 pF.
*3: The tCE is applicable if OE is brought to Low before CE1s goes Low and is also applicable if actual value of both
or either tASO or tCLOL is shorter than specified value.
*4: Applicable only to A0 and A1 when both CE1s and OE are kept at Low for the address access.
*5: Applicable if OE is brought to Low before CE1s goes Low.
*6: The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE.
If actual value of each parameter is shorter than specified minimum value, tOE becomes longer by the amount
of subtracting actual value from specified minimum value.
For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control
access (i.e., CE1s stays Low) , the tOE becomes tOE (Max) + tASO (Min) − tASO (actual) .
*7: The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access.
*8: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min)
− tCLOL (actual) or tRC (Min) − tOP (actual) .
*9: Maximum value is applicable if CE1s is kept at Low.
43
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• WRITE OPERATION (FCRAM)
Parameter
Symbol
Value
Min
Max
Unit
Notes
Write Cycle Time
tWC
90

ns
*1
Address Setup Time
tAS
0

ns
*2
Address Hold Time
tAH
45

ns
*2
CE1s Write Setup Time
tCS
0
1000
ns
CE1s Write Hold Time
tCH
0
1000
ns
WE Setup Time
tWS
0

ns
WE Hold Time
tWH
0

ns
LBs and UBs Setup Time
tBS
0

ns
LBs and UBs Hold Time
tBH
−5

ns
OE Setup Time
tOES
0
1000
ns
*3
tOEH
45
1000
ns
*3, *4
tOEH[ABS]
20

ns
*5
OE High to CE1s Low Setup Time
tOHCL
−3

ns
*6
OE High to Address Hold Time
tOHAH
−5

ns
*7
CE1s Write Pulse Width
tCW
60

ns
*1, *8
WE Write Pulse Width
tWP
60

ns
*1, *8
CE1s Write Recovery Time
tWRC
15

ns
*1, *9
WE Write Recovery Time
tWR
15
1000
ns
*1, *3, *9
Data Setup Time
tDS
20

ns
Data Hold Time
tDH
0

ns
CE1s High Pulse Width
tCP
20

ns
OE Hold Time
*9
*1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) .
*2: New write address is valid from either CE1s or WE that is brought to High.
*3: Maximum value is applicable if CE1s is kept at Low and both WE and OE are kept at High.
*4: The tOEH is specified from end of tWC (Min) , and is a reference value when access time is determined by tOE.
If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual
value from specified minimum value.
*5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1s stays Low.
*6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1s Low.
In other words, read operation is initiated if tOHCL (Min) is not satisfied.
*7: Applicable if CE1s stays Low after read operation.
*8: tCW and tWP are applicable if write operation is initiated by CE1s and WE, respectively.
*9: tWRC and tWR are applicable if write operation is terminated by CE1s and WE, respectively.
The tWR (Min) can be ignored if CE1s is brought to High together or after WE is brought to High.
In such a case, the tCP (Min) must be satisfied.
44
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• POWER DOWN PARAMETER (FCRAM)
Parameter
Symbol
Value
Min
Max
Unit
CE2s Low Setup Time for Power Down Entry
tCSP
10

ns
CE2s Low Hold Time after Power Down Entry
tC2LP
100

ns
CE1s High Hold Time following CE2s High after
Power Down Exit
tCHH
350

µs
CE1s High Setup Time following CE2s High after
Power Down Exit
tCHS
10

ns
Note
• OTHER TIMING PARAMETER (FCRAM)
Parameter
Symbol
CE1s High to OE Invalid Time for Standby Entry
Value
Unit
Note
Min
Max
tCHOX
20

ns
CE1s High to WE Invalid Time for Standby Entry
tCHWX
20

ns
*1
CE2s Low Hold Time after Power-up
tC2LH
50

µs
*2
CE2s High Hold Time after Power-up
tC2HL
50

µs
*3
CE1s High Hold Time following CE2s High after
Power-up
tCHH
350

µs
*2
tT
1
25
ns
*4
Input Transition Time
*1: It may write date into any address location tCHWX is not satisfied.
*2: Must satisfy tCHH (Min) after tC2LH (Min) .
*3: Requires Power Down mode entry and exit after tC2HL.
*4: The Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns, it may violate
AC specification of some timing parameters.
• AC TEST CONDITIONS (FCRAM)
Parameter
Symbol
Condition
Value
Unit
Input High Level
VIH
VCCs = 2.7 V to 3.1 V
2.3
V
Input Low Level
VIL
VCCs = 2.7 V to 3.1 V
0.4
V
VREF
VCCs = 2.7 V to 3.1 V
1.3
V
tT
Between VIL and VIH
5
ns
Input Timing Measurement Level
Input Transition Time
Note
45
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ Timing #1 (OE Control Access) (FCRAM)
tRC
Address
tRC
Address Valid
Address Valid
tOHAH
tASO
tCE
tOHAH
CE1s
tOLCH
tCLOL
tCE
tOP
tOE
OE
tOHZ
tASO
tOLZ
tOHZ
tOLZ
tOH
tOH
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
• READ Timing #2 (CE1s Control Access) (FCRAM)
tRC
tRC
Address
Address Valid
tASC
Address Valid
tCE
tCHAH
tASC
tCE
tCHAH
CE1s
tOLCH
tCP
tOE
tCHZ
tCHZ
OE
tCLZ
tOH
tCLZ
tOH
DQ
(Output)
Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
46
Valid Data Output
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ Timing #3 (Address Access after OE Control Access) (FCRAM)
tRC
tRC
Address
(A19 - A2)
Address Valid
Address Valid (No change)
Address
(A1, A0)
Address Valid
Address Valid
tASO
tOLAH
tOHAH
tAA
tAX
CE1s
tOHZ
tOE
OE
tOLZ
tOH
tOH
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
• READ Timing #4 (Address Access after CE1s Control Access) (FCRAM)
tRC
Address
(A19 - A2)
Address Valid
Address
(A1, A0)
Address Valid
tRC
Address Valid (No change)
Address Valid
tCLAH
tASC
tAA
tCHAH
tAX
CE1s
tCHZ
tCE
OE
tCLZ
tOH
tOH
DQ
(Output)
Valid Data Output
Valid Data Output
Note : CE2s and WE must be High during the entire read cycle.
47
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• WRITE Timing #1 (CE1s Control) (FCRAM)
tWC
Address
Address Valid
tAS
tAH
tAS
CE1s
tCW
tWRC
tWS
tWH
tWS
tBS
tBH
tBS
WE
UBs, LBs
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2s must be High during the write cycle.
48
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• WRITE Timing #2-1 (WE Control, Single Write Operetion) (FCRAM)
tWC
Address
Address Valid
tOHAH
tAS
tAH
tAS
tCH
CE1s
tCP
tOHCL
tCS
tWP
tWR
WE
tBS
tBH
UBs, LBs
tOES
OE
tOHZ
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2s must be High during the write cycle.
49
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• WRITE Timing #2 (WE Control, Continuous Write Operetion) (FCRAM)
tWC
Address Valid
Address
tOHAH
tAS
tAH
tAS
CE1s
tOHCL
tCS
tWP
tWR
WE
tBH
tBS
UBs, LBs
tOES
OE
tOHZ
tDS
tDH
DQ
(Input)
Valid Data Input
Note : CE2s must be High during the write cycle.
50
tBS
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ/WRITE Timing #1-1 (CE1s Control) (FCRAM)
tWC
Address
Write Address
tCHAH
tAS
Read Address
tASC
tAH
CE1s
tCP
tWH
tWRC
tWS
tCW
tWH
tWS
WE
tBH
tBS
UBs, LBs
tCLOL
tOHCL
OE
tOLZ
tCHZ
tOH
tDS
tDH
tCLZ
DQ
Read Data Output
Write Data Input
Note : Write address is vaild from either CE1s or WE of the last falling edge.
51
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ/WRITE Timing #1-2 (CE1s Control) (FCRAM)
tRC
Address
Read Address
Write Address
tASC
tCHAH
tWRC
tAS
CE1s
tWRC (Min)
tWH
tCP
tWH
tWS
tWS
WE
tBH
tBS
tCE
UBs, LBs
tOHCL
tOEH
OE
tCHZ
tDH
tCLZ
tOH
DQ
Write Data Input
Read Data Output
Note : tOEH is specified from the time satisfied both tWRC and tWR (Min) .
52
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ (OE Control) /WRITE (WE Control) Timing #2-1 (FCRAM)
tWC
Write Address
Address
tOHAH
CE1s
tAS
Read Address
tAH
tASO
Low
tWR
tWP
WE
tBH
tBS
UBs, LBs
tOEH
tOES
OE
tOHZ
tOH
tDS
tDH
tOLZ
DQ
Read Data Output
Write Data Input
Note : CE1s can be tied to Low for WE and OE controlled operation.
When CE1s is tied to Low, output is exclusively controlled by OE.
53
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• READ (OE Control) / WRITE (WE Control) Timing #2-2
tRC
Address
Read Address Valid
Write Address
tOHAH
tASO
CE1s
tAS
Low
tWR
WE
tBS
tBH
UBs, LBs
tOEH
tOES
tOE
OE
tOHZ
tDH
tOLZ
tOH
DQ
Write Data Input
Read Data Output
Note : CE1s can be tied to Low for WE and OE controlled operation.
When CE1s is tied to Low, output is exclusively controlled by OE.
54
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• POWER DOWN Timing (FCRAM)
CE1s
tCHS
CE2s
tCSP
tC2LP
tCHH
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
• Standby Entry Timing after Read or Write (FCRAM)
CE1s
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied,
it takes tRC (Min) period from either last address transition of A0 and A1, or CE1s Low to High transition.
55
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• POWER-UP Timing 1 (FCRAM)
CE1s
tCHS
tC2LH
tCHH
*
CE2s
VCCs
VCCs Min
0V
* : It is recommended to keep CE2s at Low during VCCs power-up.
tC2LH specifies after VCCs reaches specified minimum level.
• POWER-UP Timing 2 (FCRAM)
CE1s
tC2HL
tCSP
tCHS
tC2LP
tCHH
CE2s
tC2HL
VCCs
VCCs Min
0V
Note : tC2LH specifies from CE2S Low to High transition after VCCS reaches specified minimum level.
CE1s must be brought to High prior to or together with CE2s Low to High transition.
56
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ ERASE AND PROGRAMMING PERFORMANCE (Flash)
Value
Parameter
Unit
Remarks
10
s
Excludes programming time prior to erasure
16
360
µs
Excludes system-level overhead
—
—
200
s
Excludes system-level overhead
100,000
—
—
cycle
Min
Typ
Max
Sector Erase Time
—
1
Word Programming Time
—
Chip Programming Time
Erase/Program Cycle
■ DATA RETENTION CHARACTERISTICS (FCRAM)
Parameter
Symbol
Conditions
VDR
Value
Unit
Min
Typ
Max
CE1s = CE2s ≥ VCCs – 0.2 V or,
CE1s = CE2s = VIH
2.3
—
3.1
V
IDR
2.3 V ≤ VCCs ≤ 2.7 V,
VIN = VIH * or VIL
CE1s = CE2s = VIH * , IOUT=0 mA
—
0.5
1
mA
IDR1
2.3 V ≤ VCCs ≤ 2.7 V,
VIN ≤ 0.2 V or VIN ≥ VCCs – 0.2 V,
CE1s = CE2s ≥ VCCs – 0.2 V,
IOUT=0 mA
—
—
70
µA
Data Retention Setup Time
tDRS
2.7 V ≤ VCCs ≤ 3.1 V
at data retention entry
0
—
—
ns
Data Retention Recovery Time
tDRR
2.7 V ≤ VCCs ≤ 3.1 V
after data retention
90
—
—
ns
0.5
—
—
V/µs
VCCS Data Retention Supply
Voltage
VCCS Data Retention Supply
Current
VCCS Voltage Transition Time
∆V/∆t
—
*: 2.0 V ≤ VIH ≤ VCCs + 0.3 V
57
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
• Data Retention Timing
tDRS
tDRR
3.1 V
VCCs
∆V/∆t
∆V/∆t
2.7 V
CE2s
2.3 V
VCCs ≥ 0.2 V or VIH (*) Min
CE1s
0.4 V
VSS
Data Retention Mode
Data bus must be in High-Z at data retention entry.
* : 2.0 V ≤ VIH ≤ VCCS + 3 V
■ PIN CAPACITANCE
Parameter
Input Capacitance
Symbol
CIN
Condition
Value
Unit
Typ
Max
VIN = 0 V
11
14
pF
Output Capacitance
COUT
VOUT = 0 V
12
16
pF
Control Pin Capacitance
CIN2
VIN = 0 V
14
16
pF
WP/ACC Pin Capacitance
CIN3
VIN = 0 V
21.5
26
pF
Note: Test conditions TA = +25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of package are created acute angles.
■ CAUTION
• The high voltage (VID) cannot apply to address pins and control pins except RESET.
Exception is when autoselect and sector protect function are used. Then the high voltage (VID) can be applied
to RESET.
• Without the high voltage (VID) , sector protection can be achieved by using “Extended Sector Group Protection”
command.
58
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ ORDERING INFORMATION
MB84VD2238
X
EJ
-90
-PBS
PACKAGE TYPE
PBS = 71-ball BGA
SPEED OPTION
See Product Selector Guide
Device Revision
Bank Size
6 = 4 Mbit /
7 = 8 Mbit /
8 = 16 Mbit /
28 Mbit
24 Mbit
16 Mbit
DEVICE NUMBER/DESCRIPTION
32 Mega-bit (2 M × 16-bit) Dual Operation Flash Memory
3 V-only Read, Program, and Erase
16 Mega-bit(1M × 16-bit) FCRAM
BOOT CODE SECTOR ARCHITECTURE
84VD2238 = Top sector
84VD2239 = Bottom sector
59
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ APPENDIX
• ISB2s vs. VIN Cycle time
2.5
: RT = + 25 °C
: LT = − 30 °C
: HT = + 85 °C
ISB2s (mA)
2.0
1.5
1.0
0.5
0.0
0
200
400
600
VIN cycle time (ns)
60
800
1000
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
■ PACKAGE DIMENSION
71-pin plastic FBGA
(BGA-71P-M02)
8.80(.346)
+0.15
11.00±0.10(.433±.004)
1.05 ±0.10
+.006
.041 –.004
(Mounting height)
0.38±0.10
(Stand off)
(.015±.004)
7.00±0.10
(.276±.004)
7.20(.283)
5.60(.220)REF
0.80
(.031)
8
7
6
5
4
3
2
1
5.60(.220)
REF
0.80
(.031)
M L K J H G F E D C B A
INDEX-MARK AREA
+0.10
71-Ø0.45 –0.05
+.004
71-Ø.018 –.002
0.08(.003)
M
0.10(.004)
C
2000 FUJITSU LIMITED B71002S-1c-1
Dimensions in mm (inches).
61
MB84VD22386/387/388EJ-85/90/MB84VD22396/397/398EJ-85/90
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0111
 FUJITSU LIMITED Printed in Japan