G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Features : Description : ∗ ∗ ∗ The GLT44108 is a 524,288 x 8 bit highperformance CMOS dynamic random access memory. The GLT44108 offers Fast Page mode with asymmetric address and accepts 512-cycle refresh in 8ms interval. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 512 x 8 bits within a page, with cycle times as short as 22ns. The GLT44108 is best suited for graphics, digital signal processing and high performance peripherals. ∗ ∗ ∗ ∗ ∗ ∗ 524,288 words by 8 bits organization. Fast access time and cycle time. Low power dissipation. Operating Current-150mA max. TTL Standby Current-2mA max. Read-Modify-Write, RAS -Only Refresh, CAS -Before- RAS Refresh, Hidden Refresh and Test Mode Capability. 1024 refresh cycles/16ms. Available in 28pin 400 mil SOJ Single +5.0V±10% Power Supply. All inputs and Outputs are TTLcompatible. Fast Page Mode supports sustained data rates up to 50MHZ. PIN CONFIGURATION : GLT44108 28 Lead SOJ Vcc DQ0 DQ1 DQ2 DQ3 NC WE RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ7 DQ6 DQ5 DQ4 CAS OE NC A8 A7 A6 A5 A4 VSS G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -1- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) Max. CAS Access Time (tCAC) -40 40 ns -50 50 ns -60 60 ns 20 ns 22 ns 75 ns 12 ns 25 ns 31 ns 90 ns 13 ns 30 ns 40 ns 110 ns 15 ns Pin Descriptions: Name Function A0 – A9 RAS CAS WE OE DQ0 - DQ7 VCC VSS Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Inputs / Outputs +5V Power Supply Ground Block Diagram: OE WE CAS RAS RAS CLOCK GENERATOR CAS CLOCK GENERATOR W E CLOCK GENERATOR OE CLOCK GENERATOR V CC V SS Data I/O B U S I/O0 COLUMN DECODERS REFRESH COUNTER SENSE AMPLIFIERS I/O BUFFER Y 0 - Y8 512×8 9 1024 A0 A1 A8 . . ADDRESS BUFFERS AND PREDECODERS A9 ROW DECODERS MEMORY ARRAY X 0 - x9 G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -2- I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Absolute Maximum Ratings* Capacitance* TA=25°C, VCC=5V±10%, VSS=0V Operating Temperature, TA (ambient) ......................................-10°C to +80°C Storage Temperature(plastic)....-55°C to +150°C Voltage Relative to VSS...............-1.0V to + 7.0V Short Circuit Output Current......................50mA Power Dissipation......................................1.0W *Note:Operation above Absolute Maximum Ratings can adversely affect device reliability. Symbol Parameter Max. Unit CIN1 Address Input 5 pF CIN2 RAS , CAS , WE , OE 7 pF COUT Data Input/Output 7 pF *Note: Capacitance is sampled and not 100% tested Electrical Specifications l All voltages are referenced to GND. l After power up, wait more than 200µs and then, execute eight CAS before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit. G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -3- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) DC and Operating Characteristics (1-2) TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified. Sym. Parameter ILI Input Leakage Current (any input pin) ILO Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE ICC1 ICC2 ICC3 Standby Current,(TTL) Refresh Current, RAS -Only ICC4 Operating Current, FAST Page Mode Test Conditions 0V ≤ VIN ≤ 5.5V (All other pins not under test=0V) 0V ≤ Vout ≤ 5.5V Output is disabled (Hiz) ICC6 Refresh Current, Min. CAS at VIH tRC = tRC (min.) RAS at VIL, CAS Before RAS RAS , CAS , address cycling: tRC=tRC(min.) Standby Current, (CMOS) RAS ≥ VCC-0.2V, µA -10 +10 µA 150 140 120 mA 2 mA tRAC = 40ns tRAC = 50ns tRAC = 60ns 150 140 120 mA 2 tRAC = 40ns tRAC = 50ns tRAC = 60ns 150 140 120 mA 1,2 tRAC = 40ns tRAC = 50ns tRAC = 60ns 150 140 120 mA 1 1 mA +0.8 VCC+1 0.4 V V V V CAS ≥ VCC-0.2V, All other inputs ≥VSS VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage -1 2.4 IOL = 4.2mA IOH = -5mA Max. Unit Notes +10 RAS , CAS , at VIH other inputs ≥ VSS RAS cycling, Typ -10 tRAC = 40ns tRAC = 50ns tRAC = 60ns tRC = tRC (min.) CAS ,address cycling:tPC=tPC(min.) ICC5 Access Time 2.4 1,2 3 3 Notes: 1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open. 2.ICC is dependent upon the number of address transitions specified. ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and Fast Page Mode. 3. Specified VIL(min.) is steady state operation. During transitions, VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns.All AC parameters are measured with VIL(min.)≥Vss and VIH(max.)≤Vcc. G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -4- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) AC Characteristics (0° C≤ ≤ TA≤ 70° C,See note 1,2) Test condition:VCC=5.0V±10%, VIH/VIL=2.4V/0.8V,VOH/VOL=2.0V/0.8V Parameter 40 ns 50 ns Symbol MIN. MAX. MIN. MAX. Read/Write Cycle Time Read Midify Write Cycle Time 60 ns MIN. MAX. Unit Notes tRC tRWC tRAC 75 120 - 40 90 140 - 50 110 160 - 60 ns ns ns 3,4 tCAC - 12 - 13 - 15 ns 3,4 tAA tCLZ 0 20 - 0 25 - 0 30 - ns ns 3,4 3 tOFF 0 8 0 10 0 13 ns 7 tT tRP 3 25 50 - 3 30 50 - 3 40 50 - ns ns 2 tRAS 40 10000 50 10000 60 10000 ns tRSH 12 - 13 - 15 - ns tCSH 40 - 50 - 60 - ns tCAS 12 10000 13 10000 15 10000 ns tRCD 16 30 18 37 20 45 ns 4 tRAD 11 22 13 25 15 30 ns 4 tCRP 5 - 5 - 5 - ns 8 tASR tRAH tASC tCAH tAR 0 6 0 6 30 - 0 8 0 8 40 - 0 10 0 10 45 - ns ns ns ns ns to RAS Column Address Lead Time Referenced tRAL 20 - 25 - 30 - ns to RAS Read Command Setup Time Read Command Hold Time Referenced tRCS tRRH 0 0 - 0 0 - 0 0 - ns ns 9 to RAS Read Command Hold Time Referenced tRCH 0 - 0 - 0 - ns 9 tWCH 6 - 7 - 10 - ns 10 tWCR 30 - 40 - 45 - ns 5 Access Time from RAS Access Time from CAS Access Time from Column Address CAS to Output in Low-Z Output Buffer Turn-off Delay from CAS Transition Time(Rise and Fall) RAS Precharge Time RAS Pulse Width RAS Hold Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time Column Address Hold Time Referenced to CAS WE Hold Time Referenced to CAS Write Command Hold Time Referenced to RAS G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -5- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Parameter Symbol WE Pulse Width WE Lead Time Referenced to RAS WE Lead Time Referenced to CAS Data-In Setup Time Data-In Hold Time Data Hold Time Referenced to RAS Refresh Time(256cycles) WE Setup Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time CAS Setup Time( CAS before RAS Refresh) CAS Hold Time( CAS before RAS Refresh) RAS to CAS Precharge Time CAS Precharge Time(CBR Counter Test Cycle) Access Time from CAS Precharge Fast Page mode Read/Write Cycle Time Fast Page mode Read Modify Write Cycle Time CAS Precharge Time(Fast Page mode) RAS Pulse Width(Fast Page mode) RAS Hold Time from CAS Precharge Access Time from OE OE to Delay Time Output Buffer Turn-off Delay Time from 40 ns MIN. MAX. 50 ns MIN. MAX. 60 ns MIN. MAX. Unit 6 - 7 - 10 - ns tRWL 13 - 17 - 15 - ns tCWL 13 - 14 - 15 - ns tDS tDH tDHR 0 6 33 - 0 7 40 - 0 10 45 - ns ns ns 11 11 6 tREF tWCS 0 8 - 0 8 - 0 8 - ms ns 5 tRWD 60 - 70 - 85 - ns 5 tCWD 28 - 33 - 38 - ns 5 tAWD 38 - 43 - 53 - ns 5 tCSR 5 - 5 - 5 - ns tCHR 10 - 10 - 10 - ns tRPC 5 - 5 - 5 - ns tCPT 20 - 20 - 20 - ns tCPA - 25 - 30 - 35 ns tPC tPRWC 30 65 - 35 80 - 40 90 - ns ns tCP 7 - 8 - 10 - ns tRASP 40 125000 50 125000 60 125000 ns tRHCP 25 - 30 - 35 - ns tOEA - 10 - 13 - 15 ns tOED 8 - 10 - 13 - ns tOEZ 0 8 0 10 0 13 ns tOEH 0 - 0 - 0 - ns tWHR 15 - 15 - 15 - ns OE OE Hold Time WE Hold Time(Hidden Refresh Cycle) Notes tWP G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -6- 10 3 7 G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Notes 1. An initial pause of 200µs is required after power-up followed by any 8 RAS only Refresh or CAS before RAS Refresh cycles to initialize the internal circuit. 2. VIH(min.) and VIL(min.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.) are assumed to be 5ns for all inputs. 3. Measured with an equivalent to 1 TTL loads and 50pF. 4. For read cycles, the access time is defined as follows: Input Conditions Access Time tRAC(MAX.) tRAD ≤ tRAD(MAX.) and tRCD ≤ tRCD(MAX.) tAA(MAX.) tRAD(max.)< tRAD and tRCD ≤ tRCD(MAX.) tRCD(max.)< tRCD tCACMAX.) tRAD(MAX.) and tRCD(MAX.) indicate the points which the access time changes and are not the limits of operation. 5. tWCS,tRWD,tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle.If tCWD ≥ tCWD(min.),tRWD ≥ tRWD (min.) and tAWD ≥ tAWD(min.), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 6. tAR,tWCR, and tDHR are referenced to tRAD(max.). 7. tOFF(max.) and tOEZ(max.) define the time at which the output achieves the open circuit condition and are not referenced to VOH or VOL. 8. tCRP(min) requirement should be applicable for RAS , CAS cycle preceded by any cycles. 9. Either tRCH(min.) or tRRH(min.) must be satisfied for a read cycle. 10. tWP(min.) is applicable for late write cycle or read modify write cycle. In early write cycles,tWCH(min.) should be satisfied. 11.This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in late write or read modify write cycles. G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -7- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Read Cycle tRC tRAS tRP VIH- RAS VIL- tCSH tCRP tRCD tCRP tRSH VIH- CAS tCAS VIL- tRAD tASR VIH- Address VIL- tRAL tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCH tRRH tRCS VIH- WE VIL- tOFF tAR tAA tOEZ VIH- OE tOEA VIL- tCAC tCLZ tRAC DQ VOH- OPEN DATA-OUT VOLDon't Care Early Write Cycle NOTE : DOUT = Open tRC tRP tRAS VIH- RAS VIL- tCSH tCRP tRCD tRSH VIH- tCRP tCAS CAS VIL- VIH- Address VIL- tASR tRAH tRAD tRAL tCAH tASC ROW ADDRESS COLUMN ADDRESS tCWL tRWL tAR tWCS VIH- WE tWCR tWCH tWP VIL- VIH- OE VIL- tDHR tDS tDH VIH- DQ VIL- DATA - IN Don't Care G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -8- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Late Write Cycle ( OE Controlled Write) NOTE : DOUT = Open tRC tRP tRAS VIH- RAS VIL- tCSH tCRP tRCD CAS tCRP tRSH VIH- tCAS VIL- VIH- Address VIL- tRAD tASC tASR tRAH tRAL tCAH ROW ADDRESS COLUMN ADDRESS tCWL tRWL tRCS tWP VIH- WE VIL- VIH- OE tOEH tOED VIL- tDS VIH- DQ tDH COLUMN ADDRESS VIL- Don't Care Read - Modify - Write Cycle tRC tRP RAS tRAS VIHVIL- tCRP CAS tRCD tCRP tRSH VIH- tCAS VIL- tCSH tASR Address VIHVIL- tRAD tCAH tASC tRAH ROW ADDR. COLUMN ADDRESS tAWD tCWD WE OE VIH- tWP VIL- VIH- tOEA VIL- tCLZ tAA DQ tRWL tCWL VI/OHVI/OL- tRAC tCAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don't Care G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -9- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Fast Page Read Cycle tRASP tRP VIH- RAS VIL- tPC tCRP tRCD tCAS tCP tPC tCAS tCP tRSH tCAS VIH- CAS VIL- tRAD tCSH tASR VIH- Address VIL- tRAH tASC ROW ADDR. tASC tCAH COLUMN ADDRESS tRCS tRCH tCAH tCAH tASC COLUMN ADDRESS COLUMN ADDRESS tRCS tRCS tRRH tRCH VIH- WE VIL- tCAC tCAC tOEA tOEA VIH- OE VIL- tAA tRAC tCLZ tAA tOFF tCLZ tOEZ VIH- tOFF tOEZ tAA tOFF tCLZ tOEZ DQ VILVALID DATA-UOT Fast Page Write Cycle VALID DATA-UOT VALID DATA-UOT Don't Care NOTE : DOUT = Open tRASP t RP VIH- tRHCP RAS VIL- tPC tCRP tRCD tCAS tPC tCP tCAS tRSH tCP tCAS VIH- CAS VIL- tRAD tASR Address VIHVIL- tRAH tASC ROW ADDR. COLUMN ADDRESS tWCS VIH- WE tCSH tCAH tASC tCAH COLUMN ADDRESS tWCH tWCS tWP tWP tWCH tCAH tASC COLUMN ADDRESS tWCS tWCH tWP VIL- tCWL tCWL tCWL tRWL VIH- OE VIL- tDS VIH- DQ VIL- tDH VALID DATA-IN tDS VALID DATA-IN tDS tDS tDS VALID DATA-IN Don't Care G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 10 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Fast Page Mode Late Write Cycle tRASP t RP VIH- tRHCP RAS VIL- tCSH tCRP CAS tRCD t PC tCAS tCP tCAS tCP tRSH tCRP tCAS VIHVIL- tRAD tASR Address VIH- tCAH tASC tRAH COLUMN ADDRESS ROW ADDR. VIL- VIH- COLUMN ADDRESS tCWL tRCS tRAL tCAH tASC COLUMN ADDRESS tCWL tRCS WE tCAH tASC tCWL tRWL tRCS tWP tWP tWP tOEH tOEH tOEH VIL- VIH- OE VIL- tOED tDS Hi-Z VIH- tDH VALID DATA-IN DQ VIL- tOED tDS Hi-Z tOED tDS tDH VALID DATA-IN Hi-Z tDH VALID DATA-IN Don't Care Fast Page Read - Modify - Write Cycle tRASP RAS VIH- tRP tCSH VIL- tRCD tCAS tRSH tCAS tCP tCRP VIH- CAS VIL- tASR VIH- Address VIL- tRAD tRAH tASC ROW ADDR. tPRWC tRAL tCAH tCAH tASC COL. ADDR. COL. ADDR. tRWL tCWL tCWL tRCS VIH- WE tCWD tWP tCWD VIL- tAWD tCPWD tOEH tRWD VIH- OE tOEA tRAC tOEA tDH VIL- tCAC tAA tWP tAWD tCAC tAA tOED tOEZ tDS tOED tOEZ tDH VALID DATA-OUT VALID DATA-IN tDS VI/OH- DQ VI/OL- tCLZ tCLZ VALID DATA-OUT VALID DATA-IN Don't Care G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 11 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) CAS Before RAS Refresh Cycle tRC tRC tRP tRAS tRAS tRP V IH- RAS V IL- tCSR CAS tCHR tRPC tCSR tCHR tRPC tCRP V IHV IL- RAS -Only Refresh Cycle tRC tRC tRP tRAS tRAS tRP VIH- RAS VIL- tCRP CAS tRPC VIHVIL- tRAH tASR Address tCRP tASR tRAH VIHROW ROW VIL- Hidden Refresh Cycle ( Read ) tRC tRC tRP tRAS RAS tRAS tRP VIHVIL- tCRP tRCD tRSH tCHR VIH- CAS VIL- tRAD tASR Address VIHVIL- tRAL tCAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS tWHR VIH- WE tAA VIL- tOEA VIH- OE VIL- tCAC tRAC DQ VIHVIL- tCLZ OPEN tOEZ tOFF DATA-OUT Don't Care G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 12 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Hidden Refresh Cycle ( Write ) NOTE : DOUT =Open tRC tRC tRP tRAS RAS tRAS tRP VIHVIL- tRCD tCRP tRSH tCHR VIH- CAS VIL- tRAD tASC Address VIHVIL- tCAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWCS tWCH tWP VIH- WE VIL- VIH- OE VIL- tDS DQ tDH VIHDATA-IN VIL- Don't Care G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 13 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) CAS - Before RAS Refresh Counter Test Cycle tRP tRAS VIHRAS VIL- tCSR tRSH tCAS tCPT tCHR VIHCAS VIL- tRAL tASC AddressVIH- COLUMN ADDRESS VIL- Read Cycle tCAH tWRP tAA tCAC tWRH VIH- tRRH tRCH tRCS WE VIL- tOEA VIH- OE VIL- tOEZ tCLZ VOH- DQ VOL- Write Cycle tCEZ VALID DATA-OUT tWRP tWRH tRWL tCWL tWCH tWCS VIHWE VIL- tWP VIH- OE VIL- tDS VIHDQ VIL- OPEN tDH VALID DATA-IN Read-Modify-Write tRCS VIH- WE VIL- tAWD tCWD tCWL tRWL tWP tCAC tAA tOEA VIH- OE VIL- tOED tCLZ tOEZ tDH tDS VI/OH- DQ VI/OL- VALID VALID DATA-OUT DATA-IN Don't Care G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 14 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Ordering Information Part Number SPEED POWER FEATURE PACKAGE GLT44108-40J4 GLT44108-50J4 GLT44108-60J4 40ns 50ns 60ns Normal Normal Normal FPM FPM FPM SOJ 400mil 28L SOJ 400mil 28L SOJ 400mil 28L Parts Numbers (Top Mark) Definition : GLT 4 41 08 - 40 J4 PACKAGE -SRAM CONFIG. SPEED T : PDIP(300mil) 064 : 8K 04 : x04 -SRAM TS : TSOP(Type I) 256 : 256K 08 : x08 12 : 12ns TC : TSOP(Type ll) 512 : 512K 16 : x16 15 : 15ns PL : PLCC 100 : 1M 32 : x32 20 : 20ns FA : 300mil SOP -DRAM 70 : 70ns FB : 330mil SOP 10 : 1M(C/EDO)* -DRAM FC : 445mil SOP 11 : 1M(C/FPM)* 35 : 35ns J3 : 300mil SOJ 12 : 1M(H/EDO)* 40 : 40ns J4 : 400mil SOJ 13 : 1M(H/FPM)* 45 : 45ns VOLTAGE P : PDIP(600mil) 20 : 2M(EDO) 50 : 50ns Blank : 5V Q : PQFP 21 : 2M(FPM) 60 : 60ns L : 3.3V TQ : TQFP 40 : 4M(EDO) M : Mix Voltage 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note Note : CÙCDROM , HÙHDD. Example : 1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type. 2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type. 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 15 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Package Information 400mil 28 Lead Small Outline J-form Package (SOJ) G-Link Technology G-Link Technology Corporation,Taiwan 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 16 -