Maxim MAX144BC/D 2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin î¼max Datasheet

19-1387; Rev 2; 10/05
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
Features
♦ Single-Supply Operation (+2.7V to +5.25V)
The MAX144 provides 2-channel, single-ended operation and accepts input signals from 0 to V REF. The
MAX145 accepts pseudo-differential inputs ranging
from 0 to V REF . An external clock accesses datathrough the 3-wire serial interface, which is SPI™,
QSPI™, and MICROWIRE™-compatible.
Excellent dynamic performance and low power, combined with ease of use and small package size, make
these converters ideal for battery-powered and dataacquisition applications, or for other circuits with
demanding power-consumption and space requirements. For pin-compatible 10-bit ADCs, see the
MAX157 and MAX159 data sheets.
♦ 108ksps Sampling Rate
Applications
Battery-Powered Systems
Instrumentation
Portable Data Logging
Test Equipment
Isolated Data Acquisition
Medical Instruments
♦ Two Single-Ended Channels (MAX144) One
Pseudo-Differential Channel (MAX145)
♦ Low Power
0.9mA (108ksps, +3V Supply)
100µA (10ksps, +3V Supply)
10µA (1ksps, +3V Supply)
0.2µA (Power-Down Mode)
♦ Internal Track/Hold
♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial
Interface
♦ Space-Saving 8-Pin µMAX Package
♦ Pin-Compatible 10-Bit Versions Available
Ordering Information
PART
MAX144ACUA
MAX144BCUA
MAX144ACPA
MAX144BCPA
Process-Control Monitoring System Supervision
MAX144BC/D
Pin Configuration
TOP VIEW
MAX144AEUA
MAX144BEUA
VDD 1
CH0 (CH+) 2
CH1 (CH-)
3
MAX144
MAX145
GND 4
8
SCLK
MAX144AEPA
7
DOUT
MAX144BEPA
6
CS/SHDN
5
REF
MAX144AMJA
MAX144BMJA
TEMP
RANGE
0°C to
+70°C
0°C to
+70°C
0°C to
+70°C
0°C to
+70°C
0°C to
+70°C
-40°C to
+85°C
-40°C to
+85°C
-40°C to
+85°C
-40°C to
+85°C
-55°C to
+125°C
-55°C to
+125°C
PINPACKAGE
INL
(LSB)
8 µMAX
±0.5
U8-1
8 µMAX
±1
U8-1
8 Plastic DIP
±0.5
P8-1
8 Plastic DIP
±1
P8-1
Dice*
±1
—
8 µMAX
±0.5
U8-1
8 µMAX
±1
U8-1
8 Plastic DIP
±0.5
P8-1
8 Plastic DIP
±1
P8-1
8 CERDIP**
±0.5
J8-2
8 CERDIP**
±1
J8-2
µMAX/DIP
*Dice are specified at TA = +25°C, DC parameters only.
**Contact factory for availability.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
( ) ARE FOR MAX145 ONLY
PKG
CODE
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX144/MAX145
General Description
The MAX144/MAX145 low-power, 12-bit analog-todigital converters (ADCs) are available in 8-pin µMAX®
and DIP packages. Both devices operate with a single
+2.7V to +5.25V supply and feature a 7.4µs successive-approximation ADC, automatic power-down, fast
wake-up (2.5µs), an on-chip clock, and a high-speed,
3-wire serial interface.
Power consumption is only 3.2mW (VDD = +3.6V) at the
maximum sampling rate of 108ksps. At slower throughput rates, the automatic shutdown (0.2µA) further
reduces power consumption.
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
CH0, CH1 (CH+, CH-) to GND ................. -0.3V to (VDD + 0.3V)
REF to GND .............................................. -0.3V to (VDD + 0.3V)
Digital Inputs to GND. ............................................. -0.3V to +6V
DOUT to GND............................................ -0.3V to (VDD + 0.3V)
DOUT Sink Current ........................................................... 25mA
Continuous Power Dissipation (TA = +70°C)
µMAX (derate 4.1mW/°C above +70°C) .................... 330mW
Plastic DIP (derate 9.09mW/°C above +70°C) ............727mW
CERDIP (derate 8.00mW/°C above +70°C) . .............. 640mW
Operating Temperature Ranges (TA)
MAX144/MAX145_C_A .......................................0°C to +70°C
MAX144/MAX145_E_A. ...................................-40°C to +85°C
MAX144/MAX145_M_A ................................ -55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V DD = +2.7V to +5.25V, V REF = 2.5V, 0.1µF capacitor at REF, f SCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX145, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
12
RES
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
Bits
MAX14_A
±0.5
MAX14_B
±1
No missing codes over temperature
Offset Error
Gain Error
±0.75
LSB
±3
LSB
±3
(Note 3)
LSB
LSB
Gain Temperature Coefficient
±0.8
ppm/°C
Channel-to-Channel Offset
Matching
±0.05
LSB
Channel-to-Channel Gain
Matching
±0.05
LSB
DYNAMIC SPECIFICATIONS (fIN(sine-wave) = 10kHz, VIN = 2.5Vp-p, 108ksps, fSCLK = 2.17MHz, CH- = GND for MAX145)
Signal-to-Noise Plus
Distortion Ratio
SINAD
Total Harmonic Distortion
(including 5th-order harmonic)
THD
Spurious-Free Dynamic Range
SFDR
70
dB
-80
80
dB
dB
Channel-to-Channel Crosstalk
fIN = 65kHz, VIN = 2.5Vp-p (Note 4)
-85
dB
Small-Signal Bandwidth
-3dB rolloff
2.25
MHz
1.0
MHz
Full-Power Bandwidth
CONVERSION RATE
Conversion Time (Note 5)
tCONV
External clock, fSCLK = 2.17MHz,
16 clocks/conversion cycle
Internal clock
T/H Acquisition Time
7.4
2.5
25
Aperture Jitter
2
7
tACQ
Aperture Delay
Serial Clock Frequency
µs
5
ns
<50
fSCLK
External clock mode
Internal clock mode, for data transfer only
ps
0.1
2.17
0
5
_______________________________________________________________________________________
µs
MHz
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
(V DD = +2.7V to +5.25V, V REF = 2.5V, 0.1µF capacitor at REF, f SCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX145, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VREF
V
±1
µA
ANALOG INPUTS
Analog Input Voltage Range
VIN
Multiplexer Leakage Current
Input Capacitance
(Note 6)
0
On/off leakage current, VIN = 0 to VDD
±0.01
CIN
16
pF
EXTERNAL REFERENCE
Input Voltage Range
VREF
Input Current
(Note 7)
0
VREF = 2.5V
Input Resistance
100
18
Shutdown REF Input Current
10
µA
µA
V
3.0
VHYS
V
kΩ
2.0
VIL
Input Hysteresis
140
25
0.01
DIGITAL INPUTS (CS/SHDN) AND OUTPUT (DOUT)
VDD ≤ 3.6V
Input High Voltage
VIH
VDD > 3.6V
Input Low Voltage
VDD
+ 50mV
0.8
V
0.2
V
Input Leakage Current
IIN
VIN = 0 or VDD
±1
µA
Input Capacitance
CIN
(Note 8)
15
pF
Output Low Voltage
VOL
Output High Voltage
VOH
Three-State Output Leakage
Current
Three-State Output Capacitance
ISINK = 5mA
0.4
ISINK = 16mA
ISOURCE = 0.5mA
0.5
VDD - 0.5
V
CS/SHDN = VDD
COUT
V
CS/SHDN = VDD (Note 8)
±10
µA
15
pF
POWER REQUIREMENTS
Positive Supply Voltage
VDD
Positive Supply Current
IDD
Power-Supply Rejection
PSR
5.25
V
Operating mode
2.7
0.9
2.0
mA
Shutdown, CS/SHDN = GND
0.2
5
µA
VDD = 2.7V to 5.25V,
VREF = 2.5V, full-scale input (Note 9)
±0.15
mV
_______________________________________________________________________________________
3
MAX144/MAX145
ELECTRICAL CHARACTERISTICS (continued)
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
TIMING CHARACTERISTICS (Figure 7)
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH-= GND
for MAX145, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
Wake-Up Time
MIN
TYP
MAX
2.5
UNITS
µs
CS/SHDN Fall to Output Enable
tDV
CL = 100pF
120
ns
CS /SHDN Rise to Output Disable
tTR
CL = 100pF, Figure 1
120
ns
SCLK Fall to Output Data Valid
tDO
CL = 100pF, Figure 1
20
120
ns
External clock
0.1
2.17
0
5
SCLK Clock Frequency
fSCLK
SCLK Pulse Width High
tCH
SCLK Pulse Width Low
tCL
SCLK to CS /SHDN Setup
CS /SHDN Pulse Width
Internal clock, SCLK for data transfer only
External clock
215
Internal clock, SCLK for data transfer only
(Note 8)
50
External clock
215
Internal clock, SCLK for data transfer only
(Note 8)
50
MHz
ns
ns
tSCLKS
60
ns
tCS
60
ns
Note 1: Tested at VDD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset nulled.
Note 4: "On" channel is grounded; sine wave applied to "off" channel (MAX144 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to VDD (MAX145 only).
Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as VFS(2.7V) -VFS(5.25V).
4
_______________________________________________________________________________________
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
SUPPLY CURRENT
vs. TEMPERATURE
900
500
100
3.0
3.5
4.0
4.5
5.0
MAX144/5-02
0.1
-60 -40 -20 0
5.5
20 40 60 80 100 120 140
0.1
100
1k
SAMPLING RATE (sps)
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs. TEMPERATURE
OFFSET ERROR
vs. SUPPLY VOLTAGE
400
0
600
400
3.5
4.0
4.5
5.0
20 40 60 80 100 120 140
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OFFSET ERROR
vs. TEMPERATURE
GAIN ERROR
vs. SUPPLY VOLTAGE
GAIN ERROR
vs. TEMPERATURE
0.8
0.3
GAIN ERROR (LSB)
0.7
0.4
0.6
0.5
0.4
0.5
0.2
0.4
0.3
GAIN ERROR (LSB)
0.9
0.1
0
-0.1
0.2
0.1
0
-0.1
0.3
-0.2
-0.2
0.2
-0.3
-0.3
0.1
-0.4
-0.4
-10
15 40 65 90
TEMPERATURE (°C)
115 140
-0.5
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
MAX144/5-09
0.5
MAX144/5-07
1.0
5.5
0.4
0
-60 -40 -20 0
5.5
0.6
0.2
0
3.0
5.0
0.8
200
200
100k
MAX144/5-06
800
OFFSET ERROR (LSB)
SHUTDOWN CURRENT (nA)
600
VREF = VDD
10k
1.0
MAX144/5-05
1000
MAX144/5-04
800
-35
10
TEMPERATURE (°C)
VREF = VDD
0
-60
1
SUPPLY VOLTAGE (V)
1000
2.5
10
1
500
2.5
SHUTDOWN CURRENT (nA)
1000
VDD = VREF
CL = 20pF
CODE = 101010100000
1000
750
700
OFFSET ERROR (LSB)
1250
10,000
SUPPLY CURRENT (µA)
1100
VREF = VDD
RL = ∞
CL = 50pF
CODE = 101010100000
MAX144/5-08
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
VREF = VDD
RL = ∞
CL = 50pF
CODE = 101010100000
1300
1500
MAX144/5-01
1500
SUPPLY CURRENT
vs. SAMPLING RATE
MAX144/5-03
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
-0.5
-60
-35
-10
15
40
65
90
115 140
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX144/MAX145
Typical Operating Characteristics
(VDD = +3.0V, VREF = 2.5V, 0.1µF at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, TA = +25°C,
unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = +3.0V, VREF = 2.5V, 0.1µF at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, TA = +25°C,
unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0
-0.05
-0.10
0.4
0.3
INL (LSB)
INL (LSB)
0.05
MAX144/5-12
0.4
0.10
0.5
MAX144/5-11
0.15
INTEGRAL NONLINEARITY
vs. TEMPERATURE
0.5
MAX144/5-10
0.20
INL (LSB)
0.2
0.1
0.3
0.2
0.1
-0.15
-0.20
0
1024
2048
3072
4096
0
2.5
3.0
3.5
OUTPUT CODE
4.0
4.5
5.0
-60
5.5
-35
-10
VDD = +2.7V
EFFECTIVE NUMBER OF BITS
-20
12.0
MAX144/5-13
VDD = +2.7V
fIN = 10kHz
fSAMPLE = 108ksps
0
40
65
90
115 140
EFFECTIVE NUMBER OF BITS
vs. FREQUENCY
FFT PLOT
20
15
TEMPERATURE (°C)
VDD (V)
-40
-60
-80
-100
MAX144/5-14
0
AMPLITUDE (dB)
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
11.8
11.6
11.4
11.2
-120
-140
0
27
54
11.0
1
FREQUENCY (kHz)
10
100
FREQUENCY (kHz)
Pin Description
6
PIN
NAME
1
VDD
FUNCTION
2
CH0 (CH+)
Analog Input: MAX144 = single-ended (CH0); MAX145 = differential (CH+)
3
CH1 (CH-)
Analog Input: MAX144 = single-ended (CH1); MAX145 = differential (CH-)
4
GND
Analog and Digital Ground
5
REF
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 100nF capacitor close to
the device.
6
CS/SHDN
7
DOUT
Serial Data Output. Data changes state at SCLK’s falling edge. High impedance when CS/SHDN
is high.
8
SCLK
Serial Clock Input. DOUT changes on the falling edge of SCLK.
Positive Supply Voltage, +2.7V to +5.25V
Active-Low Chip-Select Input/Active-High Shutdown Input. Pulling CS/SHDN high puts the device into
shutdown with a maximum current of 5µA.
_______________________________________________________________________________________
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
MAX144/MAX145
VDD
DOUT
6k
DOUT
6k
CL
CL
GND
GND
a) HIGH-Z TO V0H, V0L TO V0H, AND VOH TO HIGH-Z
b) HIGH-Z TO V0L, V0H TO V0L, AND VOL TO HIGH-Z
Figure 1. Load Circuits for Enable and Disable Time
_______________Detailed Description
The MAX144/MAX145 analog-to-digital converters
(ADCs) use a successive-approximation conversion
(SAR) technique and on-chip track-and-hold (T/H)
structure to convert an analog signal to a serial 12-bit
digital output data stream.
This flexible serial interface provides easy interface to
microprocessors (µPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX144 (2 channels, single-ended) and the MAX145
(1 channel, pseudo-differential).
Analog Inputs: Single-Ended (MAX144)
and Pseudo-Differential (MAX145)
The sampling architecture of the ADC’s analog comparator is illustrated in the equivalent input circuit of
Figure 3. In single-ended mode (MAX144), both channels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted and
the conversions will continue to alternate between
channels. Channel switching is performed by toggling
the CS/SHDN pin. Conversions can be performed on
the same channel by toggling CS/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however, the output
data will still contain the channel identification bit
(before the MSB).
For the MAX145, the input channels form a single differential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ±0.5LSB (±0.1LSB for optimum results) with
respect to GND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans from when CS/SHDN falls to
the falling edge of the second clock cycle (external
CS/SHDN
SCLK
INTERNAL
CLOCK
OUTPUT
REGISTER
CONTROL
LOGIC
CH0
(CH+)
CH1
(CH-)
ANALOG
INPUT
MUX
(2 CHANNEL)
T/H
SCLK
12-BIT
IN SAR OUT
ADC
REF
DOUT
MAX144
MAX145
( ) ARE FOR MAX145
Figure 2. Simplified Functional Diagram
12-BIT CAPACITIVE DAC
MAX144
MAX145
REF
CH0
(CH+)
CH1
(CH-)
INPUT
MUX
CHOLD
16pF
COMPARATOR
ZERO
TO SAR
RIN
9kΩ
CSWITCH
TRACK
GND
SINGLE-ENDED MODE: CH0, CH1 = IN+; GND = INDIFFERENTIAL-ENDED MODE: CH+ = IN+; CH- = IN-
HOLD
T/H
CONTROL LOGIC
( ) ARE FOR MAX145
Figure 3. Analog Input Channel Structure
clock mode) or from when CS/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input.
_______________________________________________________________________________________
7
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
The capacitive digital-to-analog converter (DAC)
adjusts during the remainder of the conversion cycle
to restore node ZERO to 0V within the limits of 12-bit
resolution. This action is equivalent to transferring a
16pF · [(VIN+) - (VIN-)] charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal.
Track/Hold (T/H)
The ADC’s T/H stage enters its tracking mode on the
falling edge of CS/SHDN. For the MAX144 (singleended inputs), IN- is connected to GND and the converter samples the positive (“+”) input. For the MAX145
(pseudo-differential inputs), IN- connects to the negative input (“-”) and the difference of [(VIN+) - (VIN-)] is
sampled. At the end of the conversion, the positive
input connects back to IN+ and CHOLD charges to the
input signal.
The time required for the T/H stage to acquire an input
signal is a function of how fast its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the following equation:
tACQ = 9(RS + RIN)CIN
where RS is the source impedance of the input signal,
RIN (9kΩ) is the input resistance, and CIN (16pF) is the
input capacitance of the ADC. Source impedances
below 1kΩ have no significant impact on the AC performance of the MAX144/MAX145.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX144/MAX145 T/H stage offers a 2.25MHz
small-signal and a 1MHz full-power bandwidth, which
make it possible to use the parts for digitizing highspeed transients and measuring periodic signals with
bandwidths exceeding the ADCs sampling rate by
using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended. Most
aliasing problems can be fixed easily with an external
resistor and a capacitor. However, if DC precision is
required, it is usually best to choose a continuous or
switched-capacitor filter, such as the MAX7410/
MAX7414 (Figure 4). Their Butterworth characteristic
generally provides the best compromise (with regard to
rolloff and attenuation) in filter configurations, is easy to
design, and provides a maximally flat passband response.
Analog Input Protection
Internal protection diodes, which clamp the analog input
to VDD and GND, allow each input channel to swing
within GND - 300mV to VDD + 300mV without damage.
However, for accurate conversions, both inputs must not
exceed VDD + 50mV or be less than GND - 50mV.
If an off-channel analog input voltage exceeds the
supplies, limit the input current to 4mA.
VDD
4
VDD
2
MAX7410
MAX7414
IN
SHDN
7
OUT 5
8
CLK
0.1µF
2
CH0
1
VDD
REF
5
470Ω**
MAX144
3
fC = 15kHz
CH1
DOUT
7
0.01µF**
8
COM
1
0.01µF
OS
6
GND
3
SCLK
CS/SHDN
GND
6
4
1.5MHz
OSCILLATOR
**USED TO ATTENUATE SWITCHED-CAPACITOR FILTER CLOCK NOISE
Figure 4. Analog Input with Anti-Aliasing Filter Structure
8
EXTERNAL
REFERENCE
_______________________________________________________________________________________
µP/µC
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
Internal Clock (fSCLK < 100kHz or fSCLK > 2.17MHz)
In internal clock mode, the MAX144/MAX145 run from
an internal, laser-trimmed oscillator to within 20% of the
2MHz specified clock rate. This releases the system
microprocessor from running the SAR conversion clock
and allows the conversion results to be read back at
the processor’s convenience, at any clock rate from 0
to 5MHz. Operating the MAX144/MAX145 in internal
clock mode is necessary for serial interfaces operating
with clock frequencies lower than 100kHz or greater
than 2.17MHz. Select internal clock mode (Figure 5), by
holding SCLK high during a high/low transition of
CS/SHDN. The first SCLK falling edge samples the data
and initiates a conversion using the integrated on-chip
oscillator. After the conversion, the oscillator shuts off
and DOUT goes high, signaling the end of conversion
(EOC). Data can then be read out with SCLK.
ACTIVE
POWER
DOWN
Output Data Format
Table 1 illustrates the 16-bit, serial data stream output
format for both the MAX144 and MAX145. The first
three bits are always logic high (including the EOC bit
for internal clock mode), followed by the channel identification (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 0
for the MAX145), and then 12 bits of data in MSB-first
format. After the last bit has been read out, additional
SCLK pulses will clock out trailing zeros. DOUT transitions on the falling edge of SCLK. The output remains
high-impedance when CS/SHDN is high.
ACTIVE
tCS
tWAKE
(tACQ)
CS/SHDN
tCONV
SCLK
1
HIGH-Z
EOC
DOUT
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1 CHID MSB D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
SAMPLING INSTANT
Figure 5. Internal Clock Mode Timing
ACTIVE
POWER
DOWN
ACTIVE
ACTIVE
POWER
DOWN
SAMPLING INSTANT
tCS
CS/SHDN
tWAKE
(tACQ)
SCLK
1
HIGH-Z
DOUT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CHID MSB D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
Figure 6. External Clock Mode Timing
_______________________________________________________________________________________
9
MAX144/MAX145
External Clock (fSCLK = 100kHz to 2.17MHz)
The external clock mode (Figure 6) is selected by transitioning CS/SHDN from high to low while SCLK is low.
The external clock signal not only shifts data out, but
also drives the analog-to-digital conversion. The input
is sampled and conversion begins on the falling edge
of the second clock pulse. Conversion must be completed within 140µs to prevent degradation in the conversion results caused by droop on the T/H capacitors.
External clock mode provides the best throughput for
clock frequencies between 100kHz and 2.17MHz.
Selecting Clock Mode
To start the conversion process on the MAX144/
MAX145, pull CS/SHDN low. At CS/SHDN’s falling
edge, the part wakes up and the internal T/H enters
track mode. In addition, the state of SCLK at
CS/SHDN’s falling edge selects internal (SCLK = high)
or external (SCLK = low) clock mode.
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
Table 1. Serial Output Data Stream for Internal and External Clock Mode
1
2
3
6
7
8
9
10
11
12
13
14
15
16
DOUT (Internal Clock)
SCLK CYCLE
EOC
1
1
CHID D11
4
5
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT (External Clock)
1
1
1
CHID D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
External Reference
Effective Number of Bits (ENOB)
An external reference is required for both the MAX144
and the MAX145. At REF, the DC input resistance is a
minimum of 18kΩ. During a conversion, a reference
must be able to deliver 250µA of DC load current and
have an output impedance of 10Ω or less. Use a 0.1µF
bypass capacitor for best performance. The reference
input structure allows a voltage range of 0 to VDD +
50mV, although noise levels will decrease effective resolution at lower reference voltages.
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists only of quantization noise. With an
input range equal to the full-scale range of the ADC, the
effective number of bits can be calculated as follows:
ENOB = (SINAD - 1.76) / 6.02
Automatic Power-Down Mode
Whenever the MAX144/MAX145 are not selected
(CS/SHDN = V DD ), the parts enter their shutdown
mode. In shutdown all internal circuitry turns off, reducing supply current to typically less than 0.2µA. With an
external reference stable to within 1LSB, the wake-up
time is 2.5µs. If the external reference is not stable within 1LSB, the wake-up time must be increased to allow
the reference to stabilize.
__________Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR(MAX) = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is
expressed as:
 

2
2
2
2 
 V2 + V3 + V4 + V5  

THD = 20 x log 


V1




where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
Connection to Standard Interfaces
The MAX144/MAX145 interface is fully compatible with
SPI, QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s serial interface as master so that the CPU generates the
serial clock for the MAX144/MAX145. Select a clock frequency from 100kHz to 2.17MHz (external clock mode).
Signal-to-Noise Plus Distortion (SINAD)
1) Use a general-purpose I/O line on the CPU to pull
CS/SHDN low while SCLK is low.
2) Wait for the minimum wake-up time (tWAKE) specified before activating SCLK.
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to RMS equivalent of all other ADC output signals:


SIGNALRMS
SINAD(dB) = 20 x log 

 (Noise + Distortion)RMS 
3) Activate SCLK for a minimum of 16 clock cycles.
The serial data stream of three leading ones, the
channel identification, and the MSB of the digitized
input signal begin at the first falling clock edge.
DOUT transitions on SCLK’s falling edge and is
available in MSB-first format. Observe the SCLK to
10
______________________________________________________________________________________
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
padded with three leading ones and the channel identification before the MSB. If the serial clock hasn’t been
idled after the last LSB and CS/SHDN is kept low,
DOUT sends trailing zeros.
SPI and MICROWIRE Interface
When using SPI (Figure 8a) or MICROWIRE (Figure 8b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS/SHDN (Figure 8c).
Two consecutive 8-bit readings are necessary to obtain
the entire 12-bit result from the ADC. DOUT data transitions on the serial clock’s falling edge and is clocked
into the µP on SCLK’s rising edge. The first 8-bit data
stream contains three leading ones, the channel identi-
•••
CS/SHDN
tSCLKS
tCH
tCL
tCS
SCLK
•••
tDV
DOUT
tDO
HIGH-Z
tTR
HIGH-Z
•••
Figure 7. Detailed Serial-Interface Timing Sequence
I/O
SPI
CS/SHDN
I/O
CS/SHDN
SCK
SCLK
SK
SCLK
MISO
DOUT
SI
DOUT
MICROWIRE
VDD
MAX144
MAX145
SS
MAX144
MAX145
8b. MICROWIRE Connections
Figure 8a. SPI Connections
1ST BYTE READ
SCLK
CS/SHDN
1
2
3
4
2ND BYTE READ
5
6
7
CHID D11
D10
D9
8
9
10
11
12
13
14
15
16
HIGH-Z
DOUT*
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
D8
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
______________________________________________________________________________________
11
MAX144/MAX145
DOUT valid timing characteristic. Data should be
clocked into the µP on SCLK’s rising edge.
4) Pull CS/SHDN high at or after the 16th falling clock
edge. If CS/SHDN remains low, trailing zeros will be
clocked out after the LSB.
5) With CS/SHDN high, wait at least 60ns (tCS) before
starting a new conversion by pulling CS/SHDN low.
A conversion can be aborted by pulling CS/SHDN
high before the conversion ends; wait at least 60ns
before starting a new conversion.
Data can be output in two 8-bit sequences or continuously. The bytes will contain the result of the conversion
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
PIC16 with SSP Module and PIC17 Interface
The MAX144/MAX145 are compatible with a PIC16/
PIC17 controller (µC), using the synchronous serial-port
(SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master by initializing its synchronous serialport control register (SSPCON) and synchronous serialport status register (SSPSTAT) to the bit patterns shown
in Tables 2 and 3.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings (Figure 10b)
are necessary to obtain the entire 12-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µC on SCLK’s rising edge.
The first 8-bit data stream contains three leading ones,
the channel identification, and the first four data bits
starting with the MSB. The second 8-bit data stream
contains the remaining bits, D7 through D0.
fication, and the first four data bits starting with the
MSB. The second 8-bit data stream contains the
remaining bits, D7 through D0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX144/MAX145 support a maximum fSCLK of 2.17MHz. The QSPI circuit in Figure 9a
can be programmed to perform a conversion on each
of the two channels for the MAX144. Figure 9b shows
the QSPI interface timing.
CS
CS/SHDN
SCK
SCLK
MISO
QSPI
DOUT
VDD
MAX144
MAX145
SS
Figure 9a. QSPI Connections
1
SCLK
CS/SHDN
2
3
4
5
6
7
CHID D11
D10
D9
8
9
10
11
12
13
14
15
16
HIGH-Z
DOUT
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
D8
MSB
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
Table 2. Detailed SSPCON Register Contents
CONTROL BIT
MAX144/MAX145
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL
BIT7
X
Write Collision Detection Bit
SSPOV
BIT6
X
Receive Overflow Detect Bit
SSPEN
BIT5
1
Synchronous Serial-Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
CKP
BIT4
0
SSPM3
BIT3
0
SSPM2
BIT2
0
SSPM1
BIT1
0
SSPM0
BIT0
1
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
fCLK = fOSC / 16.
X = Don’t care
12
______________________________________________________________________________________
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
MAX144/MAX145
SETTINGS
CONTROL BIT
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
BIT6
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
BIT5
X
Data Address Bit
P
BIT4
X
Stop Bit
S
BIT3
X
Start Bit
R/W
BIT2
X
Read/Write Bit Information
UA
BIT1
X
Update Address
BF
BIT0
X
Buffer Full Status Bit
SMP
BIT7
CKE
D/A
X = Don’t care
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards
(PCBs). Wire-wrap configurations are not recommended, since the layout should ensure proper separation of
analog and digital traces. Run analog and digital lines
anti-parallel to each other, and don’t lay out digital signal paths underneath the ADC package. Use separate
analog and digital PCB ground sections with only one
star-point (Figure 11) connecting the two ground systems
VDD
VDD
SCLK
SCK
DOUT
SDI
CS/SHDN
I/O
MAX144
MAX145
(analog and digital). For lowest-noise operation, ensure
the ground return to the star ground’s power supply is
low impedance and as short as possible. Route digital
signals far away from sensitive analog and reference
inputs.
High-frequency noise in the power supply VDD could
influence the proper operation of the ADC’s fast comparator. Bypass VDD to the star ground with a network
of two parallel capacitors (0.1µF and 1µF) located as
close as possible to the power supply pin of MAX144/
MAX145. Minimize capacitor lead length for best supply-noise rejection and add an attenuation resistor
(10Ω) if the power supply is extremely noisy.
PIC16/17
GND
GND
Figure 10a. SPI Interface Connection for a PIC16/PIC17
Controller
1ST BYTE READ
SCLK
CS/SHDN
1
2
3
4
2ND BYTE READ
5
6
7
CHID D11
D10
D9
8
9
10
11
12
13
14
15
16
HIGH-Z
DOUT*
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001)
______________________________________________________________________________________
13
MAX144/MAX145
Table 3. Detailed SSPSTAT Register Contents
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
MAX144/MAX145
Ordering Information (continued)
PART
POWER SUPPLIES
+3V
+3V
GND
MAX145ACUA
R* = 10 W
MAX145BCUA
1mF
MAX145ACPA
0.1 mF
V DD
GND
+3V
DGND
DIGITAL
CIRCUITRY
MAX144
MAX145
MAX145BCPA
MAX145BC/D
MAX145AEUA
* OPTIONAL FILTER RESISTOR
MAX145BEUA
Figure 11. Power-Supply Bypassing and Grounding
Chip Information
TRANSISTOR COUNT: 2,058
SUBSTRATE CONNECTED TO GND
TEMP
RANGE
0°C to
+70°C
0°C to
+70°C
0°C to
+70°C
0°C to
+70°C
0°C to
+70°C
-40°C to
+85°C
-40°C to
+85°C
PINPACKAGE
INL
(LSB)
8 µMAX
±0.5
U8-1
8 µMAX
±1
U8-1
8 Plastic DIP
±0.5
P8-1
8 Plastic DIP
±1
P8-1
Dice*
±1
—
8 µMAX
±0.5
U8-1
8 µMAX
±1
U8-1
MAX145AEPA
-40°C to
+85°C
8 Plastic DIP
±0.5
P8-1
MAX145BEPA
-40°C to
+85°C
8 Plastic DIP
±1
P8-1
MAX145AMJA
55°C to
+125°C
8 CERDIP**
±0.5
J8-2
MAX145BMJA
55°C to
+125°C
8 CERDIP**
±1
J8-2
*Dice are specified at TA = +25°C, DC parameters only.
**Contact factory for availability.
14
PKG
CODE
______________________________________________________________________________________
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
8LUMAXD.EPS
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________
15
MAX144/MAX145
________________________________________________________Package Information
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PDIPN.EPS
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 _________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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