SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 D Single Chip With Easy Interface Between D D D GD65232, GD75232 . . . DB, DW, N, OR PW PACKAGE (TOP VIEW) UART and Serial-Port Connector of IBM PC/AT and Compatibles Meet or Exceed the Requirements of TIA/EIA-232-F and ITU v.28 Standards Designed to Support Data Rates up to 120 kbit/s Pinout Compatible With SN75C185 and SN75185 VDD RA1 RA2 RA3 DY1 DY2 RA4 DY3 RA5 VSS description/ordering information 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC RY1 RY2 RY3 DA1 DA2 RY4 DA3 RY5 GND The GD65232 and GD75232 combine three drivers and five receivers from the Texas Instruments trade-standard SN75188 and SN75189 bipolar quadruple drivers and receivers, respectively. The pinout matches the flow-through design of the SN75C185 to decrease the part count, reduce the board space required, and allow easy interconnection of the UART and serial-port connector of an IBM PC/AT and compatibles. The bipolar circuits and processing of the GD65232 and GD75232 provide a rugged, low-cost solution for this function at the expense of quiescent power and external passive components relative to the SN75C185. The GD65232 and GD75232 comply with the requirements of the TIA/EIA-232-F and ITU (formerly CCITT) V.28 standards. These standards are for data interchange between a host computer and a peripheral at signaling rates up to 20 kbit/s. The switching speeds of these devices are fast enough to support rates up to 120 kbit/s with lower capacitive loads (shorter cables). Interoperability at the higher signaling rates cannot be expected unless the designer has design control of the cable and the interface circuits at both ends. For interoperability at signaling rates up to 120 kbit/s, use of TIA/EIA-423-B (ITU V.10) and TIA/EIA-422-B (ITU V.11) standards is recommended. ORDERING INFORMATION PDIP (N) SOIC (DW) −40°C to 85°C SSOP (DB) TSSOP (PW) PDIP (N) SOIC (DW) 0°C to 70°C ORDERABLE PART NUMBER PACKAGE† TA SSOP (DB) TSSOP (PW) Tube of 20 GD65232N Tube of 25 GD65232DW Reel of 2000 GD65232DWR Reel of 2000 GD65232DBR Tube of 70 GD65232PW Reel of 2000 GD65232PWR Tube of 20 GD75232N Tube of 25 GD75232DW Reel of 2000 GD75232DWR Reel of 2000 GD75232DBR Tube of 70 GD75232PW Reel of 2000 GD75232PWR TOP-SIDE MARKING GD65232N GD65232 GD65232 GD65232 GD75232N GD75232 GD75232 GD75232 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IBM is a trademark of International Business Machines Corporation. Copyright 2004, Texas Instruments Incorporated ! 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"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 logic diagram (positive logic) RA1 RA2 RA3 DY1 DY2 RA4 DY3 RA5 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 RY1 RY2 RY3 DA1 DA2 RY4 DA3 RY5 schematic (each driver) To Other Drivers VDD 11.6 kΩ 9.4 kΩ Input DAx 75.8 Ω 320 Ω 4.2 kΩ GND To Other Drivers 10.4 kΩ 3.3 kΩ VSS To Other Drivers Resistor values shown are nominal. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 68.5 Ω Output DYx SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 schematic (each receiver) To Other Receivers VCC 9 kΩ 5 kΩ 1.66 kΩ Output RYx 2 kΩ Input RAx 3.8 kΩ 10 kΩ GND To Other Receivers Resistor values shown are nominal. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (see Note 1): VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 7 V Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 V to 30 V Driver output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 15 V Receiver low-level output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Package thermal impedance, θJA (see Notes 2 and 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to the network ground terminal. 2. Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 recommended operating conditions MIN NOM MAX VDD VSS Supply voltage (see Note 4) 7.5 9 15 UNIT V Supply voltage (see Note 4) −7.5 −9 −15 V VCC VIH Supply voltage (see Note 4) 4.5 5 5.5 V High-level input voltage (driver only) 1.9 VIL Low-level input voltage (driver only) IOH High-level output current IOL Low-level output current TA Operating free-air temperature V 0.8 Driver −6 Receiver −0.5 Driver 6 Receiver 16 GD65232 −40 85 GD75232 0 70 V mA mA °C NOTE 4: When powering up the GD65232 and GD75232, the following sequence should be used: 1. VSS 2. VDD 3. VCC 4. I/Os Applying VCC before VDD may allow large currents to flow, causing damage to the device. When powering down the GD65232 and GD75232, the reverse sequence should be used. supply currents over recommended operating free-air temperature range PARAMETER TEST CONDITIONS All inputs at 1.9 V, IDD Supply current from VDD All inputs at 0.8 V, All inputs at 1.9 V, ISS 4 No load No load Supply current from VSS All inputs at 0.8 V, ICC No load Supply current from VCC All inputs at 5 V, No load No load, POST OFFICE BOX 655303 MIN MAX VDD = 9 V, VDD = 12 V, VSS = −9 V VSS = −12 V VDD = 15 V, VDD = 9 V, VSS = −15 V VSS = −9 V VDD = 12 V, VDD = 15 V, VDD = 9 V, VSS = −12 V VSS = −15 V 5.5 VSS = −9 V VSS = −12 V −15 VDD = 12 V, VDD = 15 V, VDD = 9 V, VDD = 12 V, VDD = 15 V, VCC = 5 V • DALLAS, TEXAS 75265 VSS = −15 V VSS = −9 V VSS = −12 V VSS = −15 V UNIT 15 19 25 4.5 mA 9 −19 −25 −3.2 mA −3.2 −3.2 GD65232 38 GD75232 30 mA SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 DRIVER SECTION electrical characteristics over recommended operating free-air temperature range, VDD = 9 V, VSS = −9 V, VCC = 5 V (unless otherwise noted) PARAMETER VOH VOL High-level output voltage IIH IIL High-level input current IOS(H) IOS(L) ro TEST CONDITIONS MIN MAX RL = 3 kΩ, See Figure 1 RL = 3 kΩ, See Figure 1 VI = 5 V, VI = 0, See Figure 2 10 µA Low-level input current See Figure 2 −1.6 mA High-level short-circuit output current (see Note 6) VIL = 0.8 V, VO = 0, See Figure 1 −4.5 −12 −19.5 mA VIH = 2 V, VO = 0, VCC = VDD = VSS = 0, See Figure 1 4.5 12 19.5 mA Low-level short-circuit output current 7.5 UNIT VIL = 0.8 V, VIH = 1.9 V, Low-level output voltage (see Note 5) 6 TYP −7.5 V −6 V Output resistance (see Note 7) VO = −2 V to 2 V 300 Ω NOTES: 5. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic levels only (e.g., if −10 V is maximum, the typical value is a more negative voltage). 6. Output short-circuit conditions must maintain the total power dissipation below absolute maximum ratings. 7. Test conditions are those specified by TIA/EIA-232-F and as listed above. switching characteristics, VCC = 5 V, VDD = 12 V, VSS = −12 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3 315 500 ns tPHL Propagation delay time, high- to low-level output RL = 3 kΩ to 7 kΩ, CL = 15 pF, See Figure 3 75 175 ns Transition time, low- to high-level output 60 100 ns RL = 3 kΩ to 7 kΩ CL = 15 pF, See Figure 3 tTLH CL = 2500 pF, See Figure 3 and Note 8 1.7 2.5 µs tTHL Transition time, high- to low-level output RL = 3 kΩ to 7 kΩ CL = 15 pF, See Figure 3 40 75 ns CL = 2500 pF, See Figure 3 and Note 8 1.5 2.5 µs NOTE 8: Measured between ±3-V and ±3-V points of the output waveform (TIA/EIA-232-F conditions); all unused inputs are tied either high or low. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 RECEIVER SECTION electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP† MAX See Figure 5 1.75 1.9 2.3 See Figure 5 1.55 TEST CONDITIONS TA = 25°C, TA = 0°C to 70°C, VIT+ Positive-going input threshold voltage VIT− Vhys Negative-going input threshold voltage 0.75 Input hysteresis voltage (VIT+ − VIT−) 0.5 VOH High-level output voltage IOH = −0.5 mA VIH = 0.75 V Inputs open VOL Low-level output voltage IOL = 10 mA, VI = 3 V IIH High-level input current VI = 25 V, See Figure 5 VI = 3 V, See Figure 5 VI = −25 V, See Figure 5 VI = −3 V, See Figure 4 See Figure 5 IIL Low-level input current 2.6 2.3 0.97 1.25 UNIT V V V 4 5 V 2.6 0.2 0.45 GD65232 3.6 11 GD75232 3.6 8.3 V mA 0.43 GD65232 −3.6 −11 GD75232 −3.6 −8.3 mA −3.4 −12 mA TYP MAX UNIT −0.43 IOS Short-circuit output current † All typical values are at TA = 25°C, VCC = 5 V, VDD = 9 V, and VSS = −9 V. switching characteristics, VCC = 5 V, VDD = 12 V, VSS = −12 V, TA = 25°C PARAMETER 6 TEST CONDITIONS MIN tPLH tPHL Propagation delay time, low- to high-level output 107 250 ns Propagation delay time, high- to low-level output 42 150 ns tTLH tTHL Transition time, low- to high-level output 175 350 ns 16 60 ns tPLH tPHL Propagation delay time, low- to high-level output 100 160 ns Propagation delay time, high- to low-level output 60 100 ns tTLH tTHL Transition time, low- to high-level output 90 175 ns 15 50 ns CL = 50 pF, RL = 5 kΩ kΩ, See Figure 6 Transition time, high- to low-level output CL = 15 pF, RL = 1.5 kΩ kΩ, Transition time, high- to low-level output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 See Figure 6 SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION IOS(L) VDD VDD or GND VCC −IOS(H) VSS or GND VI VO RL = 3 kΩ VSS Figure 1. Driver Test Circuit for VOH, VOL, IOS(H), and IOS(L) VDD VCC IIH VI −IIL VI VSS Figure 2. Driver Test Circuit for IIH and IIL 3V Input VDD Input V CC 1.5 V 1.5 V 0V tPHL Pulse Generator RL See Note A CL (see Note B) 90% 50% 10% Output VSS tPLH 50% 10% tTHL TEST CIRCUIT 90% VOH VOL tTLH VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. B. CL includes probe and jig capacitance. Figure 3. Driver Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION VDD VCC VI VSS Figure 4. Receiver Test Circuit for IOS VDD VCC −IOH VOH VIT, VI VOL IOL VSS Figure 5. Receiver Test Circuit for VIT, VOH, and VOL 4V Input VDD Input V CC 50% 50% 0V tPHL Pulse Generator RL See Note A CL (see Note B) 90% Output VSS 50% 10% tPLH 50% 10% tTHL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns. B. CL includes probe and jig capacitance. Figure 6. Receiver Propagation and Transition Times 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 90% VOH VOL tTLH SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS DRIVER SECTION OUTPUT CURRENT vs OUTPUT VOLTAGE ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ VOLTAGE TRANSFER CHARACTERISTICS 12 9 12 IO − Output Current − mA VO − Output Voltage − V 16 VDD = 9 V, VSS = −9 V 6 VDD = 6 V, VSS = −6 V 3 0 −3 −6 −9 ÎÎÎÎ ÎÎÎÎ 0 0.2 0.4 0.6 VDD = 9 V VSS = −9 V TA = 25°C 4 0 −4 1 1.2 1.4 1.6 1.8 −20 −16 2 −12 0 SHORT-CIRCUIT OUTPUT CURRENT vs FREE-AIR TEMPERATURE 0 −3 −6 16 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1000 VDD = 9 V VSS = −9 V RL = 3 kΩ TA = 25°C IOS(L) (VI = 1.9 V) 3 12 SLEW RATE vs LOAD CAPACITANCE ÎÎÎÎÎÎ ÎÎÎÎÎÎ 6 8 Figure 8 SR − Slew Rate − V/ µs IOS − Short-Circuit Output Current − mA 4 −4 3-kΩ Load Line VO − Output Voltage − V Figure 7 9 −8 ÎÎÎÎÎ VI − Input Voltage − V 12 VOH (VI = 0.8 V) ÎÎÎÎÎ ÎÎÎÎÎ −8 −16 0.8 VOL (VI = 1.9 V) 8 −12 RL = 3 kΩ TA = 25°C −12 ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ 20 VDD = 12 V, VSS = −12 V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ VDD = 9 V VSS = −9 V VO = 0 100 10 IOS(H) (VI = 0.8 V) −9 −12 0 10 20 30 40 50 60 70 1 10 TA − Free-Air Temperature − °C 100 1000 10000 CL − Load Capacitance − pF Figure 9 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS 2.4 2 2.2 1.8 2 V IT − Input Threshold Voltage − V V IT − Input Threshold Voltage − V INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE VIT+ 1.8 1.6 1.4 1.2 1 VIT− 0.8 0.6 INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE VIT+ 1.6 1.4 1.2 1 VIT− 0.8 0.6 0.4 0.2 0.4 0 10 20 30 40 50 60 0 70 2 3 4 TA − Free-Air Temperature − °C 5 6 7 8 9 10 VCC − Supply Voltage − V Figure 11 Figure 12 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÁÁÁÁ ÎÎÎÎÎ ÁÁÁÁ NOISE REJECTION 5 Amplitude − V 4 3 ÎÎÎÎ ÁÁÁÁ ÎÎÎÎÎ 2 CC = 12 pF 16 CC = 300 pF 14 CC = 500 pF CC = 100 pF 1 0 10 40 MAXIMUM SUPPLY VOLTAGE vs FREE-AIR TEMPERATURE VCC = 5 V TA = 25°C See Note A 100 400 1000 tw − Pulse Duration − ns 4000 10000 NOTE A: This figure shows the maximum amplitude of a positive-going pulse that, starting from 0 V, does not cause a change of the output level. VDD − Maximum Supply Voltage − V 6 12 10 8 6 4 2 0 ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ RL ≥ 3 kΩ (from each output to GND) 0 10 30 Figure 14 POST OFFICE BOX 655303 40 50 TA − Free-Air Temperature − °C Figure 13 10 20 • DALLAS, TEXAS 75265 60 70 SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 APPLICATION INFORMATION Diodes placed in series with the VDD and VSS leads protect the GD65232 and GD75232 in the fault condition in which the device outputs are shorted to ±15 V and the power supplies are at low and provide low-impedance paths to ground (see Figure 15). VDD GD65232, GD75232 ±15 V VDD Output GD65232, GD75232 VSS VSS Figure 15. Power-Supply Protection to Meet Power-Off Fault Conditions of TIA/EIA-232-F TL16C450 ACE RI DTR CTS SO RTS SI DSR DCD −12 V 11 43 12 37 13 40 14 13 15 36 16 11 17 41 18 42 19 5V 20 VSS GND RY5 RA5 DA3 DY3 RY4 RA4 DA2 DY2 DA1 GD65232, GD75232 DY1 RY3 RA3 RY2 RA2 RY1 RA1 VCC VDD 10 5 9 RI 8 DTR 7 CTS 6 TX 5 RTS 4 RX 3 DSR 2 DCD 1 9 C3 TIA/EIA-232-F DB9S Connector C2 C1 6 1 12 V Figure 16. Typical Connection POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) GD65232DBR ACTIVE SSOP DB 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM GD65232DW ACTIVE SOIC DW 20 25 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM GD65232DWR ACTIVE SOIC DW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM GD65232N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC GD65232PW ACTIVE TSSOP PW 20 70 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM GD65232PWR ACTIVE TSSOP PW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM GD75232DB OBSOLETE SSOP DB 20 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM GD75232DBR ACTIVE SSOP DB 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM GD75232DW ACTIVE SOIC DW 20 25 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM GD75232DWR ACTIVE SOIC DW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM GD75232N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC GD75232PW ACTIVE TSSOP PW 20 70 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM GD75232PWR ACTIVE TSSOP PW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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