CA3096, CA3096A, CA3096C NPN/PNP Transistor Arrays December 1997 Applications Description • Five-Independent Transistors The CA3096C, CA3096, and CA3096A are general purpose high voltage silicon transistor arrays. Each array consists of five independent transistors (two PNP and three NPN types) on a common substrate, which has a separate connection. Independent connections for each transistor permit maximum flexibility in circuit design. - Three NPN and - Two PNP • Differential Amplifiers • DC Amplifiers • Sense Amplifiers Types CA3096A, CA3096, and CA3096C are identical, except that the CA3096A specifications include parameter matching and greater stringency in ICBO , ICEO , and VCE(SAT). The CA3096C is a relaxed version of the CA3096. • Level Shifters • Timers • Lamp and Relay Drivers • Thyristor Firing Circuits CA3096, CA3096A, CA3096C Essential Differences • Temperature Compensated Amplifiers • Operational Amplifiers CHARACTERISTIC Ordering Information PART NUMBER (BRAND) CA3096A CA3096 CA3096C NPN 35 35 24 PNP -40 -40 -24 V(BR)CEO (V) (Min) TEMP. RANGE (oC) PACKAGE PKG. NO. CA3096AE -55 to 125 16 Ld PDIP E16.3 CA3096AM (3096A) -55 to 125 16 Ld SOIC M16.15 CA3096AM96 (3096A) -55 to 125 16 Ld SOIC Tape and Reel M16.15 CA3096CE -55 to 125 16 Ld PDIP E16.3 CA3096E -55 to 125 16 Ld PDIP E16.3 CA3096M (3096) -55 to 125 16 Ld SOIC M16.15 CA3096M96 (3096) -55 to 125 V(BR)CBO (V) (Min) NPN 45 45 30 PNP -40 -40 -24 NPN 150-500 150-500 100-670 PNP 20-200 20-200 15-200 40-250 40-250 30-300 hFE at 1mA hFE at 100µA 16 Ld SOIC Tape and Reel PNP M16.15 ICBO (nA) (Max) Pinout CA3096, CA3096A, CA3096C (PDIP, SOIC) TOP VIEW 16 1 SUBSTRATE Q5 5 Q2 6 Q3 -100 NPN 100 1000 1000 PNP -100 -1000 -1000 0.5 0.7 0.7 NPN 5 - - PNP 5 - - NPN 0.6 - - PNP 0.25 - - |VIO| (mV) (Max) |IIO| (µA) (Max) 11 10 7 8 14 12 Q4 100 -100 NPN 13 4 100 -40 VCE SAT (V) (Max) Q1 3 40 PNP ICEO (nA) (Max) 15 2 NPN 9 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 File Number 595.4 CA3096, CA3096A, CA3096C Absolute Maximum Ratings Operating Conditions NPN Collector-to-Emitter Voltage, VCEO CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 35V CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V Collector-to-Base Voltage, VCBO CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 45V CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Collector-to-Substrate Voltage, VCIO (Note 1) CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 45V CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Emitter-to-Substrate Voltage, VEIO CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . . CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Emitter-to-Base Voltage, VEBO CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . . 6V CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Collector Current, IC (All Types) . . . . . . . . . . . . 50mA PNP Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC -40V -24V Thermal Information Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Maximum Power Dissipation (Each Transistor, Note 3) . . . . . 200mW Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) -40V -24V -40V -24V -40V -24V -10mA CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor of the CA3096 is isolated from the substrate by an integral diode. The substrate (Terminal 16) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. 2. θJA is measured with the component mounted on an evaluation PC board in free air. 3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal resistances to calculate the junction temperature. Electrical Specifications PARAMETER For Equipment Design, At TA = 25oC TEST CONDITIONS CA3096 MIN TYP CA3096A CA3096C MAX MIN TYP MAX MIN TYP MAX UNITS DC CHARACTERISTICS FOR EACH NPN TRANSISTOR ICBO VCB = 10V, IE = 0 - 0.001 100 - 0.001 40 - 0.001 100 nA ICEO VCE = 10V, IB = 0 - 0.006 1000 - 0.006 100 - 0.006 1000 nA V(BR)CEO IC = 1mA, IB = 0 35 50 - 35 50 - 24 35 - V V(BR)CBO IC = 10µA, IE = 0 45 100 - 45 100 - 30 80 - V V(BR)CIO ICI = 10µA, IB = IE = 0 45 100 - 45 100 - 30 80 - V V(BR)EBO IE = 10µA, IC = 0 6 8 - 6 8 - 6 8 - V VZ IZ = 10µA 6 7.9 9.8 6 7.9 9.8 6 7.9 9.8 V VCE SAT lC = 10mA, IB = 1mA - 0.24 0.7 - 0.24 0.5 - 0.24 0.7 V VBE (Note 4) IC = 1mA, VCE = 5V 0.6 0.69 0.78 0.6 0.69 0.78 0.6 0.69 0.78 V 150 390 500 150 390 500 100 390 670 - 1.9 - - 1.9 - - 1.9 - mV/oC -100 - -0.006 -40 - -0.06 -100 nA hFE (Note 4) |∆VBE/∆T| (Note 4) IC = 1mA, VCE = 5V DC CHARACTERISTICS FOR EACH PNP TRANSISTOR ICBO VCB = -10V, IE = 0 - -0.06 2 CA3096, CA3096A, CA3096C Electrical Specifications PARAMETER For Equipment Design, At TA = 25oC (Continued) TEST CONDITIONS CA3096 CA3096A CA3096C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS ICEO VCE = -10V, IB = 0 - -0.12 -1000 - -0.12 -100 - -0.12 -1000 nA V(BR)CEO IC = -100µA, IB = 0 -40 -75 - -40 -75 - -24 -30 - V V(BR)CBO IC = -10µA, IE = 0 -40 -80 - -40 -80 - -24 -60 - V V(BR)EBO IE = -10µA, IC = 0 -40 -100 - -40 -100 - -24 -80 - V V(BR)ElO IEI = 10µA, IB = IC = 0 40 100 - 40 100 - 24 80 - V VCE SAT IC = -1mA, IB = -100µA - -0.16 -0.4 - -0.16 -0.4 - -0.16 -0.4 V VBE (Note 4) IC = -100µA, VCE = -5V -0.5 -0.6 -0.7 -0.5 -0.6 -0.7 -0.5 -0.6 -0.7 V hFE (Note 4) IC = -100µA, VCE = -5V 40 85 250 40 85 250 30 85 300 IC = -1mA, VCE = -5V 20 47 200 20 47 200 15 47 200 - 2.2 - - 2.2 - - 2.2 - |∆VBE/∆T| (Note 4) IC = -100µA, VCE = -5V ICBO Collector-Cutoff Current VZ Emitter-to-Base Zener Voltage ICEO Collector-Cutoff Current VCE SAT Collector-to-Emitter Saturation Voltage V(BR)CEO Collector-to-Emitter Breakdown Voltage VBE Base-to-Emitter Voltage V(BR)CBO Collector-to-Base Breakdown Voltage hFE DC Forward-Current Transfer Ratio V(BR)CIO |∆VBE/∆T| Magnitude of Temperature Coefficient: (for each transistor) Collector-to-Substrate Breakdown Voltage V(BR)EBO Emitter-to-Base Breakdown Voltage mV/oC NOTE: 4. Actual forcing current is via the emitter for this test. Electrical Specifications For Equipment Design At TA = 25oC (CA3096A Only) CA3096A PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 0.3 5 mV FOR TRANSISTORS Q1 AND Q2 (AS A DIFFERENTIAL AMPLIFIER) Absolute Input Offset Voltage |VIO| VCE = 5V, IC = 1mA Absolute Input Offset Current |IIO| - 0.07 0.6 µA Absolute Input Offset Voltage Temperature Coefficient ∆V IO -----------------∆T - 1.1 - µV/oC - 0.15 5 mV FOR TRANSISTORS Q4 AND Q5 (AS A DIFFERENTIAL AMPLIFIER) Absolute Input Offset Voltage |VIO| VCE = -5V, IC = -100µA RS = 0 Absolute Input Offset Current |IIO| - 2 250 nA Absolute Input Offset Voltage Temperature Coefficient ∆V IO -----------------∆T - 0.54 - µV/oC 3 CA3096, CA3096A, CA3096C Typical Values Intended Only for Design Guidance At TA = 25oC Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITS DYNAMIC CHARACTERISTICS FOR EACH NPN TRANSISTOR Noise Figure (Low Frequency) NF f = 1kHz, VCE = 5V, IC = 1mA, RS = 1kΩ 2.2 dB Low-Frequency, Input Resistance RI f = 1.0kHz, VCE = 5V IC = 1 mA 10 kΩ Low-Frequency Output Resistance RO f = 1.0kHz, VCE = 5V IC = 1 mA 80 kΩ gFE f = 1MHz, VCE = 5V, IC = 1mA 7.5 mS bFE f = 1MHz, VCE = 5V, IC = 1mA -j13 mS gIE f = 1MHz, VCE = 5V, IC = 1mA 2.2 mS bIE f = 1MHz, VCE = 5V, IC = 1mA j3.1 mS gOE f = 1MHz, VCE = 5V, IC = 1mA 0.76 mS bOE f = 1MHz, VCE = 5V, IC = 1mA j2.4 mS VCE = 5V, IC = 1.0mA 280 MHz VCE = 5V, IC = 5mA 335 MHz Admittance Characteristics Forward Transfer Admittance yFE Input Admittance yIE Output Admittance yOE Gain-Bandwidth Product fT Emitter-To-Base Capacitance CEB VEB = 3V 0.75 pF Collector-To-Base Capacitance CCB VCB = 3V 0.46 pF Collector-To-Substrate Capacitance CCI VCI = 3V 3.2 pF DYNAMIC CHARACTERISTICS FOR EACH PNP TRANSISTOR Noise Figure (Low Frequency) NF f = 1kHz, IC = 100µA, RS = 1kΩ 3 dB Low-Frequency Input Resistance RI f = 1kHz, VCE = 5V, IC = 100µA 27 kΩ Low-Frequency Output Resistance RO f = 1kHz, VCE = 5V, IC = 100µA 680 kΩ Gain-Bandwidth Product fT VCE = 5V, IC = 100µA 6.8 MHz Emitter-To-Base Capacitance CEB VEB = -3V 0.85 pF Collector-To-Base Capacitance CCB VCB = -3V 2.25 pF Base-To-Substrate Capacitance CBI VBI = 3V 3.05 pF Typical Applications 9 (SUBSTRATE) 2 CENTER FREQUENCY: 1kHz 16 8 1µF 7 1 3kΩ 0.1µF 3 15 1kΩ 10 Q4 OUTPUT VOLTAGE (V) f1 500Ω 12 14 Q5 V+ = 10V 11 3kΩ 13 1kΩ 0.1µF 6 f2 500Ω 6 5 4 3 2 7 9 OUTPUT 1 Q2 5 44003 8 0 -20 4 NOTE: F1 OR F2 < 10kHz -10 f2 - f1 > 0 0 f1 = f2 10 f1 - f2 > 0 20 FREQUENCY DEVIATION (kHz) FIGURE 1. FREQUENCY COMPARATOR USING CA3096 FIGURE 2. FREQUENCY COMPARATOR CHARACTERISTICS 4 CA3096, CA3096A, CA3096C Typical Applications (Continued) 3 G NTC SENSOR 10kΩ 10 2 + 120VAC 100µF 12V Q1 - 12 1 Q3 MT2 14 6 15 5 5.1kΩ 7 8 9 T2300B 1kΩ RP 6.8kΩ 2W MT1 5.1kΩ 13 Q4 Q5 11 10kΩ Q2 10kΩ LOAD 4 16 FIGURE 3. LINE-OPERATED LEVEL SWITCH USING CA3096A OR CA3096 +6V 40841 MOSFET 13 20kΩ Q5 5kΩ 5kΩ 14 OUTPUT 15 10 11 3 6 1 12 5 Q1 Q2 2 50MΩ 20kΩ 1kΩ Q4 5µF 8 Q3 4 1kΩ 9 7 3.9kΩ 10kΩ 16 TIME DELAY CHANGES ±7% FOR SUPPLY VOLTAGE CHANGE OF ±10% FIGURE 4. ONE-MINUTE TIMER USING CA3096A AND A MOSFET V+ 36 V T = ± --------------IO RL IF IO = 1mA AND RL = 1kΩ VT = ± 36mV 1kΩ RL 1kΩ EO 12 10 Q4 11 2kΩ 15 14 1 13 2 100Ω 5 4 9 1kΩ 8 t -VT 6 Q2 Q1 100Ω VIN Q5 3 VIN +VT IO Q3 EO 0 1kΩ 7 V- FIGURE 5. CA3096A SMALL-SIGNAL ZERO VOLTAGE DETECTOR HAVING NOISE IMMUNITY 5 t CA3096, CA3096A, CA3096C Typical Applications (Continued) 1.5V LAMP GE 2158D OR EQUIVALENT 13 Q5 14 2kΩ 10kΩ 10 9 15 Q4 11 12 1.5MΩ 6 7 Q1 Q2 1 2 500kΩ Q3 8 3 5 4 2kΩ 5µF 1kΩ 16 (SUBSTRATE) FIGURE 6. TEN-SECOND TIMER OPERATED FROM 1.5V SUPPLY USING CA3096 +6V 100kΩ 1% 6.2kΩ 1% 6.2kΩ 1% OUTPUT 10 13 6 3 NOTES: Q4 Q5 11 100kΩ 1% 14 5 100kΩ 15 1% 12 1 Q2 Q1 4 5. Can be operated with either dual supply or single supply. 2 6. Wide-input common mode range +5V to -5V. 9 7. Low bias current: <1µA. Q3 51kΩ 1% 8 5kΩ 1% 7 51kΩ 1% 300Ω 1% 1kΩ 1% 16 -6V FIGURE 7. CASCADE OF DIFFERENTIAL AMPLIFIERS USING CA3096A 70 60 VOLTAGE GAIN (dB) INPUT 50 40 30 20 10 1 10 100 FREQUENCY (kHz) FIGURE 8. FREQUENCY RESPONSE 6 1000 CA3096, CA3096A, CA3096C Typical Performance Curves 104 COLLECTOR CUT-OFF CURRENT (pA) ZENER CURRENT (mA) 10 1 VZ 10-1 10-2 7 7.5 8 8.5 103 VCE = 10V 102 VCE = 5V 10 1 10-1 -100 9 -75 -50 -25 FIGURE 9. BASE-TO-EMITTER ZENER CHARACTERISTIC (NPN) DC FORWARD CURRENT TRANSFER RATIO COLLECTOR CUT-OFF CURRENT (pA) 102 VCB = 15V VCB = 10V VCB = 5V 1 10-1 10-2 -75 -50 -25 0 25 25 50 75 100 FIGURE 10. COLLECTOR CUT-OFF CURRENT (ICEO) vs TEMPERATURE (NPN) 103 10 0 TEMPERATURE (oC) ZENER VOLTAGE (V) 50 75 100 500 TA = 85oC 400 TA = 25oC 300 TA = -40oC 200 100 0 0.01 0.1 1 COLLECTOR CURRENT (mA) TEMPERATURE (oC) FIGURE 11. COLLECTOR CUT-OFF CURRENT (ICBO) vs TEMPERATURE (NPN) 10 FIGURE 12. TRANSISTOR (NPN) hFE vs COLLECTOR CURRENT 0.9 0.8 0.7 0.6 0.5 0.4 0.01 IC = 10mA, 1.67mV/oC 0.9 BASE TO EMITTER VOLTAGE (V) BASE TO EMITTER VOLTAGE (V) VCE = 5V 0.1 1 COLLECTOR CURRENT (mA) 0.8 IC = 100µA, 2.05mV/oC 0.7 0.6 0.5 0.4 -40 10 IC = 5mA, 1.77mV/oC IC = 1mA, 1.90mV/oC -20 0 20 40 60 80 TEMPERATURE (oC) FIGURE 13. VBE (NPN) vs COLLECTOR CURRENT FIGURE 14. VBE (NPN) vs TEMPERATURE 7 100 CA3096, CA3096A, CA3096C Typical Performance Curves (Continued) 104 COLLECTOR CUT-OFF CURRENT (pA) TA = 85oC COLLECTOR TO EMITTER SATURATION VOLTAGE (V) 1.0 TA = 25oC β = 10 0.8 TA = -40oC 0.6 0.4 0.2 1.0 10 COLLECTOR CURRENT (mA) VCE = -5V 102 10 -50 100 DC FORWARD CURRENT TRANSFER RATIO VCB = -15V VCB = -10V 102 VCB = -5V 10 0 25 50 75 100 50 75 100 VCE = 20V 90 VCE = 5V 80 70 VCE = 1V 60 50 40 30 20 10 0 0.01 100 FIGURE 17. COLLECTOR CUT-OFF CURRENT (ICBO) vs TEMPERATURE (PNP) 0.1 1.0 COLLECTOR CURRENT (mA) 10 FIGURE 18. TRANSISTOR (PNP) hFE vs COLLECTOR CURRENT 100 1.0 VCE = 5V 0.9 IC = 100µA BASE TO EMITTER VOLTAGE (V) DC FORWARD CURRENT TRANSFER RATIO 25 110 TEMPERATURE (oC) 80 IC = 10µA 60 IC = 1mA 40 20 0 FIGURE 16. COLLECTOR CUT-OFF CURRENT (ICEO) vs TEMPERATURE (PNP) 103 -25 -25 TEMPERATURE (oC) FIGURE 15. VCE SAT (NPN) vs COLLECTOR CURRENT COLLECTOR CUT-OFF CURRENT (pA) VCE = -10V 1 0.1 0.1 1 -50 VCE = -15V 103 IC = 5mA VCE = 5V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 -20 0 20 40 60 0 0.01 80 TEMPERATURE (oC) FIGURE 19. TRANSISTOR (PNP) hFE vs TEMPERATURE 0.1 1.0 COLLECTOR CURRENT (mA) FIGURE 20. VBE (PNP) vs COLLECTOR CURRENT 8 10 CA3096, CA3096A, CA3096C Typical Performance Curves MAGNITUDE OF INPUT OFFSET VOLTAGE (mV) (Continued) BASE TO EMITTER VOLTAGE (V) 0.9 IC = 5mA, ∆VBE/∆T - 0.97mV/oC 0.8 IC = 1mA, -1.84mV/oC 0.7 0.6 IC = 100µA, -2.2mV/oC 0.5 0.4 -40 -20 0 20 40 TEMPERATURE (oC) 60 80 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.01 10 18 0.5 RSOURCE = 500Ω 16 0.4 14 0.3 0.2 12 IC = 3mA 10 1mA 8 10µA 6 100µA 4 0.1 2 0 0.01 0.1 1 COLLECTOR CURRENT (mA) 0 0.01 10 100 RSOURCE = 10kΩ 16 24 NOISE FIGURE (dB) IC = 3mA 12 1mA 8 6 10 28 RSOURCE = 1kΩ 10 1.0 FIGURE 24. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS 18 14 0.1 FREQUENCY (kHz) FIGURE 23. MAGNITUDE OF INPUT OFFSET VOLTAGE |VIO| vs COLLECTOR CURRENT FOR PNP TRANSISTOR Q4 - Q5 NOISE FIGURE (dB) 0.1 1.0 COLLECTOR CURRENT (mA) FIGURE 22. MAGNITUDE OF INPUT OFFSET VOLTAGE |VIO| vs COLLECTOR CURRENT FOR NPN TRANSISTOR Q1 - Q2 NOISE FIGURE (dB) MAGNITUDE OF INPUT OFFSET VOLTAGE (mV) FIGURE 21. VBE (PNP) vs TEMPERATURE 0.9 10µA 20 16 IC = 3mA 12 8 1mA 10µA 4 2 0 0.01 4 100µA 0.1 1 FREQUENCY (kHz) 10 0 0.01 100 FIGURE 25. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS 100µA 0.1 1.0 FREQUENCY (kHz) 10 FIGURE 26. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS 9 100 CA3096, CA3096A, CA3096C Typical Performance Curves 28 400 GAIN-BANDWIDTH PRODUCT (MHz) RSOURCE = 100kΩ RSOURCE = 1MΩ 24 NOISE FIGURE (dB) (Continued) 20 IC = 1mA 16 100µA 12 10µA 8 100µA 4 VCE = 5V 300 200 100 10µA 0 0.01 0 0.1 1 FREQUENCY (kHz) 10 0.1 100 FIGURE 27. NOISE FIGURE vs FREQUENCY FOR NPN TRANSISTORS 1.0 COLLECTOR CURRENT (mA) 10 FIGURE 28. GAIN-BANDWIDTH PRODUCT vs COLLECTOR CURRENT (NPN) 4.0 1000 f = 1kHz INPUT RESISTANCE (kΩ) CAPACITANCE (pF) 3.5 3.0 CCI 2.5 2.0 1.5 CEB 1.0 100 NPN PNP 10 CCB 0.5 0 1 2 3 4 5 6 7 8 9 1 0.01 10 OUTPUT RESISTANCE (kΩ) f = 1kHz NPN 103 PNP 102 10 1 0.01 0.1 1.0 1 10 FIGURE 30. INPUT RESISTANCE vs COLLECTOR CURRENT FORWARD TRANSFER CONDUCTANCE (gFE) OR FORWARD TRANSFER SUSCEPTANCE (bFE) (mS) FIGURE 29. CAPACITANCE vs BIAS VOLTAGE (NPN) 104 0.1 COLLECTOR CURRENT (mA) BIAS VOLTAGE (V) 10 COLLECTOR CURRENT (mA) FIGURE 31. OUTPUT RESISTANCE vs COLLECTOR CURRENT 40 gFE 30 IC = 1mA 20 10 gFE 100µA bFE 100µA 0 -10 bFE 1mA -20 1 10 FREQUENCY (MHz) 100 FIGURE 32. FORWARD TRANSCONDUCTANCE vs FREQUENCY 10 CA3096, CA3096A, CA3096C Typical Performance Curves (Continued) gIE bIE 5 IC = 10mA 4 10mA 3 100µA 10µA 1mA 2 1mA 1 100µA 10µA 0 1 10 FREQUENCY (MHz) 2.5 OUTPUT CONDUCTANCE (gOE) OR OUTPUT SUSCEPTANCE (bOE) (mS) INPUT CONDUCTANCE (gIE) OR INPUT SUSCEPTANCE (bIE) (mS) 6 2.0 1.0 0.5 0 1 1mA gOE 10 FREQUENCY (MHz) 100 30 RSOURCE = 500Ω RSOURCE = 1kΩ NOISE FIGURE (dB) NOISE FIGURE (dB) 100µA gOE FIGURE 34. OUTPUT ADMITTANCE vs FREQUENCY 30 20 IC = 1mA 10µA 10 20 10µA 0 0.01 0.1 1.0 FREQUENCY (kHz) 10 100µA 0 0.01 100 IC = 1mA 10 100µA FIGURE 35. NOISE FIGURE vs FREQUENCY (PNP) 0.1 1 FREQUENCY (kHz) 10 100 FIGURE 36. NOISE FIGURE vs FREQUENCY (PNP) 8 40 RSOURCE = 10kΩ GAIN-BANDWIDTH PRODUCT (MHz) VCE = 5V 30 NOISE FIGURE (dB) 100µA bOE 1.5 100 FIGURE 33. INPUT ADMITTANCE vs FREQUENCY IC = 1mA bOE IC = 1mA 20 100µA 10 7 6 5 10µA 0 0.01 0.1 1.0 FREQUENCY (kHz) 10 4 0.1 100 FIGURE 37. NOISE FIGURE vs FREQUENCY (PNP) 1.0 COLLECTOR CURRENT (mA) FIGURE 38. GAIN-BANDWIDTH PRODUCT vs COLLECTOR CURRENT (PNP) 11 10 CA3096, CA3096A, CA3096C Typical Performance Curves (Continued) 6 CAPACITANCE (pF) 5 4 3 CBI CBC 2 CBE 1 0 0 1 2 3 4 5 6 7 8 9 10 BIAS VOLTAGE (V) FIGURE 39. CAPACITANCE vs BIAS VOLTAGE (PNP) Metallization Mask Layout CA3096H 0 10 20 30 40 40 30 37-45 (0.940-1.143) 20 10 0 4-10 (0.102-0.254) 37-45 (0.940-1.143) Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). The photographs and dimensions represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57 degrees instead of 90 degrees with respect to the face of the chip. Therefore, the isolated chip is actually 7mils (0.17mm) larger in both dimensions. 12 CA3096, CA3096A, CA3096C Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) E D 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE BASE PLANE A2 -C- SEATING PLANE A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S INCHES MILLIMETERS C L SYMBOL MIN MAX MIN MAX NOTES eA A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 13 B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 D 0.735 0.775 D1 0.005 - E 0.300 0.325 E1 0.240 0.280 6.10 e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 16 0.204 0.355 18.66 - 19.68 5 0.13 - 5 7.62 8.25 6 7.11 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 16 10.92 7 3.81 4 9 Rev. 0 12/93 CA3096, CA3096A, CA3096C Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- α e B 0.25(0.010) M C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MAX MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e A1 MIN 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α 16 0o 16 8o 0o 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 14 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029