MC33272A, MC33274A, NCV33272A, NCV33274A Single Supply, High Slew Rate, Low Input Offset Voltage Operational Amplifiers The MC33272/74 series of monolithic operational amplifiers are quality fabricated with innovative Bipolar design concepts. This dual and quad operational amplifier series incorporates Bipolar inputs along with a patented Zip−R−Trim element for input offset voltage reduction. The MC33272/74 series of operational amplifiers exhibits low input offset voltage and high gain bandwidth product. Dual−doublet frequency compensation is used to increase the slew rate while maintaining low input noise characteristics. Its all NPN output stage exhibits no deadband crossover distortion, large output voltage swing, and an excellent phase and gain margin. It also provides a low open loop high frequency output impedance with symmetrical source and sink AC frequency performance. http://onsemi.com MARKING DIAGRAMS DUAL 8 PDIP−8 P SUFFIX CASE 626 8 1 1 8 SOIC−8 D SUFFIX CASE 751 8 1 • • • 33272 ALYWx G 1 Features • • • • • • • • • • • • • • MC33272AP AWL YYWWG Input Offset Voltage Trimmed to 100 mV (Typ) Low Input Bias Current: 300 nA Low Input Offset Current: 3.0 nA High Input Resistance: 16 MW Low Noise: 18 nV/ √ Hz @ 1.0 kHz High Gain Bandwidth Product: 24 MHz @ 100 kHz High Slew Rate: 10 V/ms Power Bandwidth: 160 kHz Excellent Frequency Stability Unity Gain Stable: w/Capacitance Loads to 500 pF Large Output Voltage Swing: +14.1 V/ −14.6 V Low Total Harmonic Distortion: 0.003% Power Supply Drain Current: 2.15 mA per Amplifier Single or Split Supply Operation: +3.0 V to +36 V or ±1.5 V to ±18 V ESD Diodes Provide Added Protection to the Inputs Pb−Free Packages are Available NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes x = A for MC33272AD/DR2 = N for NCV33272ADR2 QUAD 14 PDIP−14 P SUFFIX CASE 646 MC33274AP AWLYYWWG 1 14 1 14 1 14 SOIC−14 D SUFFIX CASE 751A 14 MC33274ADG AWLYWW 1 NCV33274ADG AWLYWW 1 14 TSSOP−14 DTB SUFFIX CASE 948G 14 1 NCV3 3274 ALYWG G 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 11 1 Publication Order Number: MC33272A/D MC33272A, MC33274A, NCV33272A, NCV33274A PIN CONNECTIONS DUAL QUAD CASE 626/751 CASE 646/751A/948G Output 1 1 2 Inputs 1 VEE 3 8 7 − + − + 4 6 VCC Output 2 Output 1 1 14 2 13 Inputs 1 Inputs 2 3 5 VCC (Top View) 1 4 − + Inputs 4 12 4 11 5 10 Inputs 2 6 Output 2 − + + − 2 3 7 + − Output 4 9 8 VEE Inputs 3 Output 3 (Top View) MAXIMUM RATINGS Rating Symbol Value Unit VCC to VEE +36 V VIDR Note 1 V Input Voltage Range VIR Note 1 V Output Short Circuit Duration (Note 2) tSC Indefinite sec Maximum Junction Temperature TJ +150 °C Storage Temperature Tstg −60 to +150 °C Supply Voltage Input Differential Voltage Range ESD Protection at Any Pin − Human Body Model − Machine Model Maximum Power Dissipation Operating Temperature Range MC33272A, MC33274A NCV33272A, NCV33274A Vesd 2000 200 V PD Note 2 mW TA −40 to +85 −40 to +125 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Either or both input voltages should not exceed VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2). http://onsemi.com 2 MC33272A, MC33274A, NCV33272A, NCV33274A DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.) Figure Symbol Input Offset Voltage (RS = 10 W, VCM = 0 V, VO = 0 V) (VCC = +15 V, VEE = −15 V) TA = +25°C TA = −40° to +85°C TA = −40° to +125°C (NCV33272A) TA = −40° to +125°C (NCV33274A) (VCC = 5.0 V, VEE = 0) TA = +25°C Characteristics 3 |VIO| Average Temperature Coefficient of Input Offset Voltage RS = 10 W, VCM = 0 V, VO = 0 V, TA = −40° to +125°C 3 Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25°C TA = Tlow to Thigh 4, 5 Input Offset Current (VCM = 0 V, VO = 0 V) TA = +25°C TA = Tlow to Thigh Typ Max 6 Large Signal Voltage Gain (VO = 0 V to 10 V, RL = 2.0 kW) TA = +25°C TA = Tlow to Thigh 7 Unit mV − − − − 0.1 − − − 1.0 1.8 2.5 3.5 − − 2.0 − 2.0 − − − 300 − 650 800 − − 3.0 − 65 80 DVIO/DT mV/°C IIB nA |IIO| Common Mode Input Voltage Range (DVIO = 5.0 mV, VO = 0 V) TA = +25°C nA VICR V VEE to (VCC −1.8) AVOL dB 90 86 Output Voltage Swing (VID = ±1.0 V) (VCC = +15 V, VEE = −15 V) RL = 2.0 kW RL = 2.0 kW RL = 10 kW RL = 10 kW (VCC = 5.0 V, VEE = 0 V) RL = 2.0 kW RL = 2.0 kW 100 − − − 8, 9, 12 Power Supply Rejection VCC/VEE = +15 V/ −15 V, +5.0 V/ −15 V, +15 V/ −5.0 V V VO + VO − VO + VO − 13.4 − 13.4 − 13.9 −13.9 14 −14.7 − −13.5 − −14.1 VOL VOH − 3.7 − − 0.2 5.0 13 CMR 80 100 − 14, 15 PSR 80 105 − +25 −25 +37 −37 − − 10, 11 Common Mode Rejection (Vin = +13.2 V to −15 V) Output Short Circuit Current (VID = 1.0 V, Output to Ground) Source Sink 16 ISC Power Supply Current Per Amplifier (VO = 0 V) (VCC = +15 V, VEE = −15 V) TA = +25°C TA = Tlow to Thigh (VCC = 5.0 V, VEE = 0 V) TA = +25°C 17 ICC 3. MC33272A, MC33274A Tlow = −40°C NCV33272A, NCV33274A Tlow = −40°C Min Thigh = +85°C Thigh = +125°C http://onsemi.com 3 dB dB mA mA − − 2.15 − 2.75 3.0 − − 2.75 MC33272A, MC33274A, NCV33272A, NCV33274A AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.) Characteristics Figure Symbol Slew Rate (Vin = −10 V to +10 V, RL = 2.0 kW, CL = 100 pF, AV = +1.0 V) 18, 33 SR 19 20, 21, 22 Gain Bandwidth Product (f = 100 kHz) AC Voltage Gain (RL = 2.0 kW, VO = 0 V, f = 20 kHz) Min Typ Max Unit V/ms 8.0 10 − GBW 17 24 − MHz AVO − 65 − dB BW − 5.5 − MHz Unity Gain Bandwidth (Open Loop) Gain Margin (RL = 2.0 kW, CL = 0 pF) 23, 24, 26 Am − 12 − dB Phase Margin (RL = 2.0 kW, CL = 0 pF) 23, 25, 26 fm − 55 − Deg 27 CS − −120 − dB BWP − 160 − kHz − 0.003 − Channel Separation (f = 20 Hz to 20 kHz) Power Bandwidth (VO = 20 Vpp, RL = 2.0 kW, THD ≤ 1.0%) Total Harmonic Distortion (RL = 2.0 kW, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0) 28 THD Open Loop Output Impedance (VO = 0 V, f = 6.0 MHz) 29 % |ZO| − 35 − W Differential Input Resistance (VCM = 0 V) Rin − 16 − MW Differential Input Capacitance (VCM = 0 V) Cin − 3.0 − pF Equivalent Input Noise Voltage (RS = 100 W, f = 1.0 kHz) 30 en − 18 − nV/ √ Hz Equivalent Input Noise Current (f = 1.0 kHz) 31 in − 0.5 − pA/ √ Hz VCC Vin + − Vin + Sections B C D VO + VEE Figure 1. Equivalent Circuit Schematic (Each Amplifier) http://onsemi.com 4 2400 5.0 V, IO INPUT OFFSET VOLTAGE (mV) P(MAX), MAXIMUM POWER DISSIPATION (mW) D MC33272A, MC33274A, NCV33272A, NCV33274A 2000 MC33272P & MC33274P 1600 MC33274D 1200 800 MC33272D 400 0 −60 −40 −20 0 20 40 60 80 100 −3.0 −25 0 25 50 75 100 125 600 I IB, INPUT BIAS CURRENT (nA) 150 VCC = +15 V VEE = −15 V TA = 25°C −12 −8.0 −4.0 0 4.0 8.0 12 500 VCC = +15 V VEE = −15 V VCM = 0 V 400 300 200 100 0 −55 16 −25 0 25 50 75 VCM, COMMON MODE VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C) Figure 4. Input Bias Current versus Common Mode Voltage Figure 5. Input Bias Current versus Temperature VCC VCC VCC −0.5 VCC −1.0 VCC −1.5 VCC −2.0 VCC = +5.0 V to +18 V VEE = −5.0 V to −18 V DVIO = 5.0 mV VO = 0 V VEE +1.0 VEE −25 0 25 50 75 100 125 A, VOL OPEN LOOP VOLTAGE GAIN (X 1.0 kV/V) I IB, INPUT BIAS CURRENT (nA) V, ICR INPUT COMMON MODE VOLTAGE RANGE (V) 1. VIO > 0 @ 25°C 2. VIO = 0 @ 25°C 3. VIO < 0 @ 25°C Figure 3. Input Offset Voltage versus Temperature for Typical Units 200 VEE −55 2 1 3 Figure 2. Maximum Power Dissipation versus Temperature 250 VEE +0.5 2 −1.0 TA, AMBIENT TEMPERATURE (°C) 300 0 −16 3 1 TA, AMBIENT TEMPERATURE (°C) 350 50 1.0 −5.0 −55 120 140 160 180 400 100 VCC = +15 V VEE = −15 V VCM = 0 V 3.0 100 125 100 125 180 160 140 120 100 −55 VCC = +15 V VEE = −15 V RL = 2.0 kW f = 10 Hz DVO = −10 V to +10 V −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 6. Input Common Mode Voltage Range versus Temperature Figure 7. Open Loop Voltage Gain versus Temperature http://onsemi.com 5 V sat , OUTPUT SATURATION VOLTAGE (V) MC33272A, MC33274A, NCV33272A, NCV33274A TA = 25°C 30 RL = 10 kW 20 10 0 V sat , OUTPUT SATURATION VOLTAGE (V) RL = 2.0 kW 0 5.0 10 15 Source VCC −1.0 TA = −55°C TA = 125°C VCC −2.0 TA = 25°C VEE +2.0 Sink VEE +1.0 TA = 125°C TA = 25°C TA = −55°C VCC = +5.0 V to +18 V VEE = −5.0 V to −18 V VEE 20 0 5.0 10 15 20 VCC, VEE SUPPLY VOLTAGE (V) IL, LOAD CURRENT (±mA) Figure 8. Split Supply Output Voltage Swing versus Supply Voltage Figure 9. Split Supply Output Saturation Voltage versus Load Current VCC TA = 125°C VCC VCC −4.0 VCC = +5.0 V to +18 V RL to Gnd VEE = Gnd TA = 55°C VCC −8.0 VCC −12 +0.2 TA = 125°C TA = +25°C TA = −55°C +0.1 Gnd 0 100 1.0 k 10 k 100 k TA = 55°C 8.0 TA = 25°C 4.0 TA = −55°C TA = 125°C VCC = +15 V RL to VCC VEE = Gnd RFdbk = 100 kW 0 10 100 1.0 k 10 k 100 k Figure 11. Single Supply Output Saturation Voltage versus Load Resistance to VCC CMR, COMMON MODE REJECTION (dB) VCC = +15 V VEE = −15 V RL = 2.0 kW AV = +1.0 THD = ≤1.0% TA = 25°C 0 1.0 k 14.2 Figure 10. Single Supply Output Saturation Voltage versus Load Resistance to Ground 16 4 TA = 25°C RL, LOAD RESISTANCE TO VCC (W) 20 8 TA = 125°C 14.6 RL , LOAD RESISTANCE TO GROUND (kW) 24 12 15 1.0 M 28 VO , OUTPUT VOLTAGE (Vpp ) VCC V sat , OUTPUT SATURATION VOLTAGE (V) VO , OUTPUT VOLTAGE (Vpp ) 40 10 k 100 k 1.0 M 1 0M 120 100 80 60 40 20 0 10 TA = −55°C TA = 125°C VCC = +15 V VEE = −15 V VCM = 0 V DVCM = ±1.5 V − ADM DVCM DVO + CMR = 20Log 100 DVCM DVO X ADM 1.0 k 10 k 100 k f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 12. Output Voltage versus Frequency Figure 13. Common Mode Rejection versus Frequency http://onsemi.com 6 1.0 M MC33272A, MC33274A, NCV33272A, NCV33274A 100 80 TA = −55°C 60 VCC − ADM + 40 DVO VEE 20 DVO/ADM DVCC +PSR = 20Log |I|, SC OUTPUT SHORT CIRCUIT CURRENT (mA) 0 −PSR, POWER SUPPLY REJECTION (dB) VCC = +15 V VEE = −15 V DVCC = ±1.5 V TA = 125°C 10 100 1.0 k 10 k 100 k DVCC = ±1.5 V VCC = +15 V VEE = −15 V 100 TA = −55°C 80 60 VCC − ADM + 40 DVO TA = 125°C VEE 20 −PSR = 20Log 10 DVO/ADM DVEE 100 1.0 k 10 k 100 k 1.0 M f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 14. Positive Power Supply Rejection versus Frequency Figure 15. Negative Power Supply Rejection versus Frequency 11 60 VCC = +15 V VEE = −15 V VID = ±1.0 V RL < 100 W 50 Sink 40 Source Sink 30 Source 20 10 0 −55 −25 0 25 50 75 100 9.0 TA = +25°C 8.0 TA = −55°C 7.0 6.0 5.0 3.0 125 0 2.0 4.0 6.0 8.0 10 12 14 16 18 VCC, |VEE| , SUPPLY VOLTAGE (V) Figure 16. Output Short Circuit Current versus Temperature Figure 17. Supply Current versus Supply Voltage GBW, GAIN BANDWIDTH PRODUCT (MHz) − DVin + VO 2.0kW 100 pF 1.0 VCC = +15 V VEE = −15 V DVin = 20 V 0.95 0.9 0.85 −55 TA = +125°C TA, AMBIENT TEMPERATURE (°C) 1.1 1.05 10 4.0 1.15 SR, SLEW RATE (NORMALIZED) 120 0 1 .0 M I, CC SUPPLY CURRENT (mA) +PSR, POWER SUPPLY REJECTION (dB) 120 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 50 VCC = +15 V VEE = −15 V f = 100 kHz RL = 2.0 kW CL = 0 pF 40 30 20 10 0 −55 Figure 18. Normalized Slew Rate versus Temperature −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 Figure 19. Gain Bandwidth Product versus Temperature http://onsemi.com 7 20 125 100 20 100 120 140 Phase 5.0 160 0 180 −5.0 200 −15 VCC = +15 V VEE = −15 V RL = 2.0 kW TA = 25°C 220 240 1.0 M 280 100 M 10 M 180 2A 200 1B −10 1A − Phase V = 18 V, V = −18 V CC EE −15 2A − Phase VCC = 1.5 V, VEE = −1.5 V 2B 1B − Gain VCC = 18 V, VEE = −18 V −20 2B − Gain V = 1.5 V, V = −1.5 V CC EE −25 100 k 1.0 M 10 M 220 240 100 M f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 20. Voltage Gain and Phase versus Frequency Figure 21. Gain and Phase versus Frequency 12 100 20 120 10 140 1A 160 2A 0 180 VCC = +15 V VEE = −15 V −10 Vout = 0 V TA = 25°C 1A − Phase (RL = 2.0 kW) −20 2A − Phase (RL = 2.0 kW, CL = 300 pF) 1B − Gain (RL = 2.0 kW) 2B − Gain (RL = 2.0 kW, CL = 300 pF) −30 3.0 4.0 6.0 8.0 10 200 1B 220 2B 240 260 280 20 0 Gain Margin 10 10 VCC = +15 V VEE = −15 V VO = 0 V 8.0 6.0 20 30 − Vin VO + 2.0 kW 4.0 CL 40 2.0 50 Phase Margin 0 1.0 30 10 100 1000 f, FREQUENCY (MHz) CL, OUTPUT LOAD CAPACITANCE (pF) Figure 22. Open Loop Voltage Gain and Phase versus Frequency Figure 23. Open Loop Gain Margin and Phase Margin versus Output Load Capacitance 12 60 CL = 10 pF 10 8.0 CL = 100 pF 6.0 CL = 300 pF CL = 500 pF 4.0 2.0 0 −55 160 0 φ m, PHASE MARGIN (DEGREES) A, m OPEN LOOP GAIN MARGIN (dB) A, VOL OPEN LOOP VOLTAGE GAIN (dB) −25 100 k 140 −5.0 260 −20 5.0 120 1A TA = 25°C CL = 0 pF 10 A, m OPEN LOOP GAIN MARGIN (dB) −10 15 VCC = +15 V VEE = −15 V −25 0 25 50 75 100 CL = 10 pF 50 CL = 100 pF CL = 300 pF 40 30 CL = 500 pF 20 VCC = +15 V VEE = −15 V 10 0 −55 125 −25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C) Figure 24. Open Loop Gain Margin versus Temperature Figure 25. Phase Margin versus Temperature http://onsemi.com 8 φ m, PHASE MARGIN (DEGREES) 10 80 A V , VOLTAGE GAIN (dB) Gain 15 25 φ EXCESS PHASE (DEGREES) A V , VOLTAGE GAIN (dB) 20 80 φ, EXCESS PHASE (DEGREES) 25 φ, PHASE (DEGREES) MC33272A, MC33274A, NCV33272A, NCV33274A 125 MC33272A, MC33274A, NCV33272A, NCV33274A A, m GAIN MARGIN (dB) Phase Margin 40 9.0 VCC = +15 V VEE = −15 V RT = R1+R2 VO = 0 V TA = 25°C 3.0 0 Vin 20 − R1 + R2 1.0 10 10 VO 100 0 10 k 1.0 k 120 110 1.0 k 10 k 100 k 1.0 M f, FREQUENCY (Hz) Figure 26. Phase Margin and Gain Margin versus Differential Source Resistance Figure 27. Channel Separation versus Frequency |Z|, Ω O OUTPUT IMPEDANCE () AV = +1000 0.1 AV = +10 0.01 e, nV/ √ Hz ) n INPUT REFERRED NOISE VOLTAGE ( 130 RT, DIFFERENTIAL SOURCE RESISTANCE (W) AV = +100 AV = +1.0 VO = 2.0 Vpp TA = 25°C 10 100 1.0 k VCC = +15 V VEE = −15 V 10 k 30 AV = 1000 20 AV = 100 10 AV = 1.0 AV = 10 100 k 1.0 M 10 M f, FREQUENCY (Hz) f, FREQUENCY (Hz) Figure 29. Output Impedance versus Frequency 40 − 30 VO Input Noise Voltage Test Circuit 20 VCC = +15 V VEE = −15 V TA = 25°C 10 40 Figure 28. Total Harmonic Distortion versus Frequency + 10 VCC = +15 V VEE = −15 V VO = 0 V TA = 25°C 0 10 k 100 k 50 0 140 50 1.0 0.001 Driver Channel VCC = +15 V VEE = −15 V RL = 2.0 kW DVOD = 20 Vpp TA = 25°C 150 100 100 pA/ √ Hz ) i, n INPUT REFERRED NOISE CURRENT ( THD, TOTAL HARMONIC DISTORTION (%) 30 CS, CHANNEL SEPERATION (dB) 50 12 6.0 160 60 Gain Margin φ m , PHASE MARGIN (DEGREES) 15 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k 2.0 Input Noise Current Circuit 1.8 1.6 RS 1.4 + − 1.2 (RS = 10 kW) 1.0 0.8 0.6 VCC = +15 V VEE = −15 V TA = 25°C 0.4 0.2 0 10 Figure 30. Input Referred Noise Voltage versus Frequency 100 1.0 k f, FREQUENCY (Hz) 10 k Figure 31. Input Referred Noise Current versus Frequency http://onsemi.com 9 VO 100 k MC33272A, MC33274A, NCV33272A, NCV33274A PERCENT OVERSHOOT (%) 60 VCC = +15 V VEE = −15 V RL = 2.0 kW TA = 25°C 50 40 30 20 10 0 10 100 CL, LOAD CAPACITANCE (pF) 1000 V, O OUTPUT VOLTAGE (5.0 V/DIV) V, O OUTPUT VOLTAGE (5.0 V/DIV) Figure 32. Percent Overshoot versus Load Capacitance VCC = +15 V VEE = −15 V AV = +1.0 RL = 2.0 kW CL = 100 pF TA = 25°C t, TIME (2.0 ms/DIV) VCC = +15 V VEE = −15 V AV = +1.0 RL = 2.0 kW TA = 25°C CL = f t, TIME (2.0 ns/DIV) Figure 34. Non−inverting Amplifier Overshoot for the MC33274 VCC = +15 V VEE = −15 V AV = +1.0 RL = 2.0 kW CL = 300 pF TA = 25°C V, O OUTPUT VOLTAGE (5.0 V/DIV) Figure 33. Non−inverting Amplifier Slew Rate for the MC33274 V, O OUTPUT VOLTAGE (50 mV/DIV) CL = 100 pF VCC = +15 V VEE = −15 V AV = +1.0 RL = 2.0 kW CL = 300 pF TA = 25°C t, TIME (2.0 ms/DIV) t, TIME (1.0 ms/DIV) Figure 35. Small Signal Transient Response for MC33274 Figure 36. Large Signal Transient Response for MC33274 http://onsemi.com 10 MC33272A, MC33274A, NCV33272A, NCV33274A ORDERING INFORMATION Device MC33272AD Package SOIC−8 MC33272ADG SOIC−8 (Pb−Free) MC33272ADR2 SOIC−8 MC33272ADR2G MC33272AP MC33272APG NCV33272ADR2* Shipping † SOIC−8 (Pb−Free) 98 Units / Rail 2500 / Tape & Reel PDIP−8 PDIP−8 (Pb−Free) 50 Units / Rail SOIC−8 NCV33272ADR2G* SOIC−8 (Pb−Free) MC33274AD SOIC−14 MC33274ADG SOIC−14 (Pb−Free) MC33274ADR2 SOIC−14 MC33274ADR2G SOIC−14 (Pb−Free) MC33274AP PDIP−14 MC33274APG PDIP−14 (Pb−Free) NCV33274AD* SOIC−14 NCV33274ADG* SOIC−14 (Pb−Free) NCV33274ADR2* SOIC−14 NCV33274ADR2G* SOIC−14 (Pb−Free) NCV33274ADTBR2G* TSSOP−14 (Pb−Free) 2500 / Tape & Reel 55 Units / Rail 2500 / Tape & Reel 25 Units / Rail 55 Units / Rail 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV prefix for automotive and other applications requiring site and control changes. http://onsemi.com 11 MC33272A, MC33274A, NCV33272A, NCV33274A PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 1 0.25 (0.010) M Y M 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 12 DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC33272A, MC33274A, NCV33272A, NCV33274A PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C −T− SEATING PLANE H G D 14 PL J K 0.13 (0.005) M M http://onsemi.com 13 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 _ 0.38 1.01 MC33272A, MC33274A, NCV33272A, NCV33274A TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 DIM A B C D F G H J J1 K K1 L M SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC33272A, MC33274A, NCV33272A, NCV33274A PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M 7 1 G −T− D 14 PL 0.25 (0.010) T B S A DIM A B C D F G J K M P R J M K M F R X 45 _ C SEATING PLANE B M S SOLDERING FOOTPRINT* 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 15 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC33272A, MC33274A, NCV33272A, NCV33274A PACKAGE DIMENSIONS 8 PDIP−8 P SUFFIX CASE 626−05 ISSUE L 5 −B− 1 4 F −A− NOTE 2 L C J −T− N SEATING PLANE D H NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10 _ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10_ 0.030 0.040 M K G 0.13 (0.005) M T A M B M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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