Microchip MCP6H72 2.7 mhz, 12v op amp Datasheet

MCP6H71/2/4
2.7 MHz, 12V Op Amps
Features:
Description:
•
•
•
•
•
•
Microchip’s MCP6H71/2/4 family of operational
amplifiers (op amps) has a wide supply voltage range
of 3.5V to 12V and rail-to-rail output operation. This
family is unity gain stable and has a gain bandwidth
product of 2.7 MHz (typical). These devices operate
with a single-supply voltage as high as 12V, while only
drawing 480 µA/amplifier (typical) of quiescent current.
•
•
•
•
•
Input Offset Voltage: ±1 mV (typical)
Quiescent Current: 480 µA (typical)
Common Mode Rejection Ratio: 103 dB (typical)
Power Supply Rejection Ratio: 105 dB (typical)
Rail-to-Rail Output
Supply Voltage Range:
- Single-Supply Operation: 3.5V to 12V
- Dual-Supply Operation: ±1.75V to ±6V
Gain Bandwidth Product: 2.7 MHz (typical)
Slew Rate: 2 V/µs (typical)
Unity Gain Stable
Extended Temperature Range: -40°C to +125°C
No Phase Reversal
The MCP6H71/2/4 family is offered in single
(MCP6H71), dual (MCP6H72) and quad (MCP6H74)
configurations. All devices are fully specified in
extended temperature range from -40°C to +125°C.
Package Types
MCP6H71
SOIC
Applications:
•
•
•
•
Automotive Power Electronics
Industrial Control Equipment
Battery Powered Systems
Sensor Conditioning
NC 1
8 NC
VOUTA 1
8 VDD
VIN– 2
7 VDD
VINA– 2
7 VOUTB
VIN+ 3
6 VOUT
5 NC
VINA+ 3
6 VINB–
5 VINB+
VSS 4
VSS 4
MCP6H72
2x3 TDFN
MCP6H71
2x3 TDFN
Design Aids:
•
•
•
•
•
MCP6H72
SOIC
SPICE Macro Models
FilterLab® Software
MAPS (Microchip Advanced Part Selector)
Analog Demonstration and Evaluation Boards
Application Notes
NC 1
VIN– 2
VIN+ 3
VSS 4
EP
9
8 NC
VOUTA 1
7 VDD
VINA– 2
6 VOUT VINA+ 3
5 NC
8 VDD
EP
9
VSS 4
7 VOUTB
6 VINB–
5 VINB+
MCP6H74
SOIC, TSSOP
Typical Application
R1
R2
V1
VREF
VDD
MCP6H71
VOUT
VOUTA 1
14 VOUTD
VINA– 2
13 VIND–
VINA+ 3
VDD 4
12 VIND+
11 VSS
VINB+ 5
10 VINC+
VINB– 6
9 VINC–
8 VOUTC
VOUTB 7
V2
* Includes Exposed Thermal Pad (EP); see Table 3-1.
R1
R2
Difference Amplifier
 2012 Microchip Technology Inc.
DS22325B-page 1
MCP6H71/2/4
NOTES:
DS22325B-page 2
 2012 Microchip Technology Inc.
MCP6H71/2/4
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Absolute Maximum Ratings †
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other conditions
above those indicated in the operational listings of this
specification is not implied. Exposure to maximum
rating conditions for extended periods may affect
device reliability.
†† See Section 4.1.2, Input Voltage Limits.
VDD – VSS.......................................................................13.2V
Current at Input Pins......................................................±2 mA
Analog Inputs (VIN+, VIN-)††.............VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ............VSS – 0.3V to VDD + 0.3V
Difference Input Voltage..........................................VDD – VSS
Output Short-Circuit Current...................................continuous
Current at Output and Supply Pins ..............................±65 mA
Storage Temperature.....................................-65°C to +150°C
Maximum Junction Temperature (TJ)...........................+150°C
ESD protection on all pins (HBM; MM) 2 kV; 200V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +12V, VSS = GND, TA = +25°C,
VCM = VDD/2 - 1.4V, VOUT  VDD/2, VL = VDD/2 and RL = 10 kto VL. (Refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset
Input Offset Voltage
Input Offset Drift with Temperature
Power Supply Rejection Ratio
VOS
-4
±1
4
VOS/TA
—
±2.5
—
PSRR
82
105
—
IB
—
10
—
pA
—
400
—
pA
TA = +85°C
TA = +125°C
mV
µV/°C TA = -40°C to +125°C
dB
Input Bias Current and Impedance
Input Bias Current
—
9
25
nA
Input Offset Current
IOS
—
±1
—
pA
Common Mode Input Impedance
ZCM
—
1013||6
—
||pF
ZDIFF
—
1013||6
—
||pF
Common Mode Input Voltage Range
VCMR
VSS – 0.3
—
VDD – 2.5
V
Common Mode Rejection Ratio
CMRR
76
96
—
dB
VCM = -0.3V to 1.0V,
VDD = 3.5V
80
99
—
dB
VCM = -0.3V to 2.5V,
VDD = 5V
80
103
—
dB
VCM = -0.3V to 9.5V,
VDD = 12V
100
120
—
dB
0.2V < VOUT <(VDD –
0.2V)
Differential Input Impedance
Common Mode
Open-Loop Gain
DC Open-Loop Gain (Large Signal)
 2012 Microchip Technology Inc.
AOL
DS22325B-page 3
MCP6H71/2/4
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +12V, VSS = GND, TA = +25°C,
VCM = VDD/2 - 1.4V, VOUT  VDD/2, VL = VDD/2 and RL = 10 kto VL. (Refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
Conditions
VOH
3.490
3.495
—
V
VDD = 3.5V
0.5V input overdrive
4.985
4.993
—
V
VDD = 5V
0.5V input overdrive
11.970
11.980
—
V
VDD = 12V
0.5V input overdrive
—
0.005
0.010
V
VDD = 3.5V
0.5 V input overdrive
—
0.007
0.015
V
VDD = 5V
0.5 V input overdrive
—
0.020
0.030
V
VDD = 12V
0.5 V input overdrive
—
±32
—
mA
VDD = 3.5V
—
±50
—
mA
VDD = 5V
—
±53
—
mA
VDD = 12V
Output
High-Level Output Voltage
Low-Level Output Voltage
Output Short-Circuit Current
VOL
ISC
Power Supply
Supply Voltage
Quiescent Current per Amplifier
VDD
IQ
3.5
—
12
V
Single-Supply operation
±1.75
—
±6
V
Dual-Supply operation
—
480
600
µA
IO = 0, VCM = VDD/4
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +12V, VSS = GND,
VCM = VDD/2 - 1.4V, VOUT  VDD/2, VL = VDD/2, RL = 10 kto VL and CL = 60 pF. (Refer to Figure 1-1).
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
GBWP
—
2.7
—
MHz
Phase Margin
PM
—
57
—
°C
Slew Rate
SR
—
2
—
V/µs
G = +1V/V
Noise
Input Noise Voltage
Eni
—
11
—
µVp-p
f = 0.1 Hz to 10 Hz
Input Noise Voltage Density
Eni
—
28
—
nV/Hz
f = 1 kHz
—
16
—
nV/Hz
f = 10 kHz
Input Noise Current Density
ini
—
1.9
—
fA/Hz
f = 1 kHz
DS22325B-page 4
 2012 Microchip Technology Inc.
MCP6H71/2/4
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +12V and VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 8L-SOIC
JA
—
149.5
—
°C/W
Thermal Resistance, 8L-2x3 TDFN
JA
—
52.5
—
°C/W
Thermal Resistance, 14L-SOIC
JA
—
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
JA
—
100
—
°C/W
Conditions
Temperature Ranges
Note 1
Thermal Package Resistances
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
1.2
Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT (refer to Equation 1-1). Note that VCM is not the
circuit’s common mode voltage ((VP + VM)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
CF
6.8 pF
RG
100 k
VP
G DM = RF  R G
CB1
100 nF
MCP6H7X
VCM =  VP + V DD  2   2
VDD/2
CB2
1 µF
VIN–
VOST = V IN– – V IN+
V OUT =  VDD  2  +  VP – V M  + V OST   1 + G DM 
Where:
GDM = Differential Mode Gain
(V/V)
VCM = Op Amp’s Common Mode
Input Voltage
(V)
 2012 Microchip Technology Inc.
VDD
VIN+
EQUATION 1-1:
VOST = Op Amp’s Total Input Offset
Voltage
RF
100 k
(mV)
VM
RG
100 k
RL
10 k
RF
100 k
CF
6.8 pF
VOUT
CL
60 pF
VL
FIGURE 1-1:
AC and DC Test Circuit for
Most Specifications.
DS22325B-page 5
MCP6H71/2/4
NOTES:
DS22325B-page 6
 2012 Microchip Technology Inc.
MCP6H71/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +12V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
14%
800 Samples
Inputt Offset Voltage (μV)
ntage of Occurances
Percen
16%
12%
10%
8%
6%
4%
2%
4.0
3.0
2.0
1.0
0.0
-1.0
-2.0
-3.0
-4.0
0%
Input Offset Voltage (mV)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage vs.
Common Mode Input Voltage.
45%
Inputt Offset Voltage (μV)
Percentage of Occurances
50%
800 Samples
TA = - 40°C to +125°C
40%
1000
800
TA = +125°C
600
TA = +85°C
TA = +25°C
400
TA = -40°C
200
0
-200
-400
VDD = 5V
-600
Representative Part
-800
-1000
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Common Mode Input Voltage (V)
35%
30%
25%
20%
15%
10%
5%
-24
-21
-18
-15
-12
-9
-6
-3
0
3
6
9
12
15
18
21
24
0%
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
-0.5
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 12V
Representative Part
1.5
3.5
5.5
7.5
9.5
Common Mode Input Voltage (V)
Input Offset Voltage Drift (μV/°C)
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
-0.5
Input Offset Voltage Drift.
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 3.5V
Representative Part
0.0
0.5
1.0
1.5
2.0
Common Mode Input Voltage (V)
FIGURE 2-3:
Input Offset Voltage vs.
Common Mode Input Voltage.
 2012 Microchip Technology Inc.
FIGURE 2-5:
Input Offset Voltage vs.
Common Mode Input Voltage.
Inputt Offset Voltage (μV)
Inputt Offset Voltage (μV)
FIGURE 2-2:
2.5
11.5
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
Representative Part
VDD = 12V
VDD = 5V
VDD = 3.5V
0
2
FIGURE 2-6:
Output Voltage.
4
6
8
10
Output Voltage (V)
12
14
Input Offset Voltage vs.
DS22325B-page 7
MCP6H71/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +12V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
Representative Part
100
0
CM
MRR, PSRR (dB)
-100
-200
-300
TA = +125°C
125 C
TA = +85°C
TA = +25°C
TA = -40°C
-400
-500
-600
0
2
4
6
8
Power Supply Voltage (V)
10
PSRR+
PSRR-
100
100
1000
10000
1k
10k
Frequency (Hz)
FIGURE 2-10:
Frequency.
1,000
100000
100k
1000000
1M
CMRR, PSRR vs.
130
PSRR
CMRR,
C
PSRR (dB)
120
100
10
110
100
90
80
CMRR @ VDD = 12V
@ VDD = 5V
@ VDD = 3.5V
3 5V
70
60
1
50
1.E+0
1
1.E+1
10
1.E+2
100
1.E+3
1k
1.E+4
10k
1.E+5
100k
1.E+6
1M
-50
-25
Frequency (Hz)
FIGURE 2-8:
vs. Frequency.
Input Noise Voltage Density
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-11:
Temperature.
100
125
CMRR, PSRR vs. Ambient
10000
10n
FIGURE 2-9:
Input Noise Voltage Density
vs. Common Mode Input Voltage.
DS22325B-page 8
0.1
0.1p
Ambient Temperature (°C)
125
11
115
1
3
5
7
9
Common Mode Input Voltage (V)
105
-1
Input Offset Current
95
8
1
1p
85
f = 10 kHz
VDD = 12 V
10
10
10p
75
12
65
14
Input Bias Current
100
100p
55
16
VDD = 12 V
1000
1n
35
18
25
Input Bias and Offset Currents
(A)
20
Input Noise
N
Voltage Density
(nV/Hz)
Representative Part
CMRR
10
10
12
FIGURE 2-7:
Input Offset Voltage vs.
Power Supply Voltage.
Input Noise
N
Voltage Density
(nV/Hz)
120
110
100
90
80
70
60
50
40
30
20
45
Input O
Offset Voltage (uV)
200
FIGURE 2-12:
Input Bias, Offset Currents
vs. Ambient Temperature.
 2012 Microchip Technology Inc.
MCP6H71/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +12V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
120
10000
10n
Ope
en-Loop Gain (dB)
Inpu
ut Bias Current (A)
TA = +125°C
1000
1n
100
100p
TA = +85°C
10
10p
VDD = 12 V
1p
1
2
4
6
8
10
Common Mode Input Voltage (V)
-30
80
-60
Open-Loop Phase
60
-90
40
-120
20
-150
150
0
-180
1.0E+00
1
12
FIGURE 2-13:
Input Bias Current vs.
Common Mode Input Voltage.
1.0E+01
1.0E+02
1.0E+03
1.0E+05
10
100
1k 1.0E+04
10k 100k
Frequency (Hz)
FIGURE 2-16:
Frequency.
-210
1.0E+07
1M 10M
1.0E+06
Open-Loop Gain, Phase vs.
160
DC-Open Loop Gain (dB)
700
Qu
uiescent Current
(uA/Amplifier)
100
-20
0
600
VDD = 12V
VDD = 5V
VDD = 3.5V
500
400
300
150
140
130
120
110
100
VSS + 0.2V < VOUT < VDD - 0.2V
90
80
200
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
3
125
FIGURE 2-14:
Quiescent Current vs.
Ambient Temperature.
700
140
600
130
500
400
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
40°C
300
200
5
7
9
11
Power Supply Voltage (V)
13
FIGURE 2-17:
DC Open-Loop Gain vs.
Power Supply Voltage.
Ch
hannel to Channel
Separation
S
(dB)
Quiescent
Q
Current
(uA/Amplifier)
0
Open-Loop Gain
Ope
en-Loop Phase (°)
100000
100n
100
120
110
100
90
Input Referred
80
0
70
0
2
4
6
8
10
Power Supply Voltage (V)
FIGURE 2-15:
Quiescent Current vs.
Power Supply Voltage.
 2012 Microchip Technology Inc.
12
100
100
1k
1000
10k
100k
10000
100000
Frequency (Hz)
1M
100000
FIGURE 2-18:
DC Open-Loop Gain vs.
Output Voltage Headroom.
DS22325B-page 9
MCP6H71/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +12V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
Output Short Circuit Current
(mA)
140
Ch
hannel to Channel
Separation
S
(dB)
130
120
110
100
90
Input Referred
80
70
1k
1000
10k
100k
10000
100000
Frequency (Hz)
180
4.0
160
Gain Bandwidth Product
140
3.0
120
2.5
100
2.0
80
1.5
60
1.0
40
Phase Margin
20
VDD = 3.5V
0.0
160
140
120
2.5
100
2.0
80
1.5
60
0.5
VDD = 12V
Phase Margin
0.0
40
20
0
-50 -25 0
25 50 75 100 125
Ambient Temperature (°C)
FIGURE 2-21:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
DS22325B-page 10
2
4
6
8
10
12
VDD = 12V
10
VDD = 5V
VDD = 3.5V
1
FIGURE 2-23:
Frequency.
Output Voltage
V
Headroom (mV)
180
4.0
1.0
10
0
1000
1k
Phase
P
Margin (°)
Gain
n Bandwidth Product
(MHz)
4.5
3.0
10
0.1
FIGURE 2-20:
Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
Gain Bandwidth Product
20
FIGURE 2-22:
Output Short Circuit Current
vs. Power Supply Voltage.
-25
0
25 50 75 100 125
Ambient Temperature (°C)
3.5
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40
C
40°C
30
0
0
-50
40
100
Ph
hase Margin (°)
Gain Bandwidth
B
Product
(MHz)
4.5
0.5
50
Power Supply Voltage (V)
FIGURE 2-19:
Channel-to-Channel
Separation vs. Frequency (MCP6H72/4 only).
3.5
60
1M
100000
Outputt Voltage Swing (VP-P)
100
100
70
10000
10k
100000
100k
Frequency (Hz)
1000000
1M
10000000
10M
Output Voltage Swing vs.
1000
VDD = 12V
100
10
1
0.1
0.01
VOL - VSS
VDD - VOH
0.1
1
10
Output Current (mA)
100
FIGURE 2-24:
Output Voltage Headroom
vs. Output Current.
 2012 Microchip Technology Inc.
MCP6H71/2/4
Output Voltage
V
Headroom (mV)
Output Voltage
V
Headroom (mV)
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5V to +12V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
1000
VDD = 5V
100
VOL - VSS
10
VDD - VOH
1
0.1
0.01
0.1
1
10
Output Current (mA)
VDD = 3.5V
100
VOL - VSS
VDD - VOH
1
0.10
1.00
Output Current (mA)
VOL - VSS
5
4
VDD - VOH
3
2
VDD = 5V
1
0
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-28:
Output Voltage Headroom
vs. Ambient Temperature.
10.00
FIGURE 2-26:
Output Voltage Headroom
vs. Output Current.
8
7
VDD - VOH
6
5
4
VOL - VSS
3
2
VDD = 3.5V
1
0
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-29:
Output Voltage Headroom
vs. Ambient Temperature.
2.5
12
10
2.0
Slew
S
Rate (V/μs)
Output Voltage
V
Headroom (mV)
6
-50
Output Voltage
V
Headroom (mV)
Output Voltage
V
Headroom (mV)
1000
0.1
0.01
7
100
FIGURE 2-25:
Output Voltage Headroom
vs. Output Current.
10
8
VOL - VSS
8
6
VDD - VOH
4
2
1.5
Falling Edge, VDD = 12V
Rising Edge, VDD = 12V
1.0
0.5
VDD = 12V
0
0.0
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-27:
Output Voltage Headroom
vs. Ambient Temperature.
 2012 Microchip Technology Inc.
-50
-25
FIGURE 2-30:
Temperature.
0
25
50
75
Ambient Temperature (°C)
100
125
Slew Rate vs. Ambient
DS22325B-page 11
MCP6H71/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5 V to +12 V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
9
3.0
8
Outtput Voltage (V)
Slew
S
Rate (V/μs)
2.5
Falling Edge, VDD = 5V
Rising Edge, VDD = 5V
2.0
1.5
1.0
Falling Edge, VDD = 3.5V
Ri i Edge,
Rising
Ed
VDD = 3.5V
3 5V
0.5
7
6
5
4
3
VDD = 12 V
G = +1 V/V
2
1
0.0
-50
-25
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-31:
Temperature.
100
0
125
Slew Rate vs. Ambient
Time (5 μs/div)
FIGURE 2-34:
Pulse Response.
Large Signal Non-Inverting
9
VDD = 12 V
G = +1 V/V
Outp
put Voltage (V)
Outputt Voltage (20 mv/div)
10
8
VDD = 12 V
G = -1 V/V
7
6
5
4
3
2
1
0
Time (5 μs/div)
Time (0.4 μs/div)
FIGURE 2-32:
Pulse Response.
Small Signal Non-Inverting
FIGURE 2-35:
Response.
Large Signal Inverting Pulse
VDD = 12 V
G = -1 V/V
Time (0.4 μs/div)
FIGURE 2-33:
Response.
DS22325B-page 12
Small Signal Inverting Pulse
11
Input, Outp
put Voltages (V)
Outputt Voltage (20 mv/div)
13
VOUT
9
7
VIN
5
3
1
VDD = 12 V
G = +2 V/V
-1
Time (0.1 ms/div)
FIGURE 2-36:
The MCP6H71/2/4 Shows
No Phase Reversal.
 2012 Microchip Technology Inc.
MCP6H71/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +3.5 V to +12 V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT  VDD/2,
VL = VDD/2, RL = 10 kto VL and CL = 60 pF.
1m
1000
1.00E-03
100μ
1.00E-05
1μ
100
1.00E-06
-IIN (A)
Clo
osed Loop Output
Impedance
I
(:)
1.00E-04
10μ
GN:
101 V/V
11 V/V
1 V/V
10
100n
1.00E-07
10n
1.00E-08
1n
1.00E-09
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
100
100p
1.00E-10
10p
1.00E-11
1p
1.00E-12
1
1.0E+02
100
1.0E+03
1k
1.0E+04
1.0E+05
10k
100k
Frequency (Hz)
1.0E+06
1M
FIGURE 2-37:
Closed-Loop Output
Impedance vs. Frequency.
 2012 Microchip Technology Inc.
1.0E+07
10M
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
VIN (V)
FIGURE 2-38:
Measured Input Current vs.
Input Voltage (below VSS).
DS22325B-page 13
MCP6H71/2/4
NOTES:
DS22325B-page 14
 2012 Microchip Technology Inc.
MCP6H71/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6H71
MCP6H72
MCP6H74
SOIC
2x3 TDFN
SOIC
2x3 TDFN
SOIC,
TSSOP
Symbol
Description
6
6
1
1
1
VOUT, VOUTA
Analog Output (op amp A)
2
2
2
2
2
VIN–, VINA–
Inverting Input (op amp A)
3
3
3
3
3
VIN+, VINA+
Non-inverting Input (op amp A)
7
7
8
8
4
VDD
—
—
5
5
5
VINB+
Non-inverting Input (op amp B)
—
—
6
6
6
VINB–
Inverting Input (op amp B)
Positive Power Supply
—
—
7
7
7
VOUTB
Analog Output (op amp B)
—
—
—
—
8
VOUTC
Analog Output (op amp C)
—
—
—
—
9
VINC–
Inverting Input (op amp C)
—
—
—
—
10
VINC+
Non-Inverting Input (op amp C)
Negative Power Supply
4
4
4
4
11
VSS
—
—
—
—
12
VIND+
Non-Inverting Input (op amp D)
—
—
—
—
13
VIND–
Inverting Input (op amp D)
—
—
—
—
14
VOUTD
Analog Output (op amp D)
1, 5, 8
1, 5, 8
—
—
—
NC
No Internal Connection
—
9
—
9
—
EP
Exposed Thermal Pad (EP);
must be connected to VSS.
3.1
Analog Outputs
The output pins are low-impedance voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 3.5V to 12V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts can be used in single-supply
operation or dual-supply operation. Also, VDD will need
bypass capacitors.
3.4
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (JA).
 2012 Microchip Technology Inc.
DS22325B-page 15
MCP6H71/2/4
NOTES:
DS22325B-page 16
 2012 Microchip Technology Inc.
MCP6H71/2/4
4.0
APPLICATION INFORMATION
The MCP6H71/2/4 family of op amps are manufactured
using Microchip’s state-of-the-art CMOS process and
are specifically designed for low-power, high-precision
applications.
4.1
VDD
D1
D2
V1
VOUT
Inputs
4.1.1
MCP6H7X
V2
PHASE REVERSAL
The MCP6H71/2/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-36 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2
INPUT VOLTAGE LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”).
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions, and to minimize the input bias
current (IB).
FIGURE 4-2:
Inputs.
Protecting the Analog
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS), as shown in Figure 2-38.
4.1.3
INPUT CURRENT LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute
Maximum Ratings †”).
Figure 4-3 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
currents in or out of the input pins (and the ESD diodes,
D1 and D2). The diode currents will go through either
VDD or VSS.
VDD
VDD Bond
Pad
D1
VIN+
Bond
Pad
Input
Stage
Bond
VIN–
Pad
D2
V1
R1
MCP6H7X
VOUT
V2
R2
VSS Bond
Pad
FIGURE 4-1:
Structures.
R3
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
Simplified Analog Input ESD
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go well above VDD. Their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
overvoltage (beyond VDD) events. Very fast ESD
events (that meet the specification) are limited so that
damage does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-2 shows one approach to protecting these
inputs.
R1 >
FIGURE 4-3:
Inputs.
4.1.4
Protecting the Analog
NORMAL OPERATION
The inputs of the MCP6H71/2/4 op amps connect to a
differential PMOS input stage. It operates at a low
common mode input voltage (VCM), including ground.
With this topology, the device operates with a VCM up
to VDD – 2.5V and 0.3V below VSS (refer to Figures 2-3
through 2-5). The input offset voltage is measured at
VCM = VSS – 0.3V and VDD – 2.5V to ensure proper
operation.
For a unity gain buffer, VIN must be maintained below
VDD – 2.5V for correct operation.
 2012 Microchip Technology Inc.
DS22325B-page 17
MCP6H71/2/4
4.2
Rail-to-Rail Output
1000
4.3
Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases, and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1V/V) is the
most sensitive to capacitive loads, all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = + 1V/V), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
with no capacitance load.
VDD = 12 V
RL = 10 k
Reco
ommended R ISO (:)
The output voltage range of the MCP6H71/2/4 op amps
is 0.020V (typical) and 11.980V (typical) when
RL = 10 k is connected to VDD/2 and VDD = 12V.
Refer to Figures 2-24 through 2-29 for more
information.
100
1
10p
100p
1n
10n
0.1μ 1.E-06
1μ
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
Normalized Load Capacitance; CL/GN (F)
FIGURE 4-5:
Recommended RISO Values
for Capacitive Loads.
4.4
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor can be shared
with other analog parts.
4.5
–
VIN
MCP6H7X
+
RISO
VOUT
CL
FIGURE 4-4:
Output Resistor, RISO
Stabilizes Large Capacitive Loads.
Figure 4-5 gives the recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., -1V/V gives GN = +2V/V).
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6H71/2/4 SPICE macro
model are helpful.
GN:
1 V/V
2 V/V
t 5 V/V
10
Unused Op Amps
An unused op amp in a quad package (MCP6H74)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp, and the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
¼ MCP6H74 (A)
¼ MCP6H74 (B)
VDD
R1
VDD
VDD
R2
VREF
R2
V REF = VDD  -------------------R1 + R2
FIGURE 4-6:
DS22325B-page 18
Unused Op Amps.
 2012 Microchip Technology Inc.
MCP6H71/2/4
4.6
PCB Surface Leakage
4.7
In applications where low-input bias current is critical,
PCB surface leakage effects need to be considered.
Surface leakage is caused by humidity, dust or other
contamination on the board. Under low-humidity conditions, a typical resistance between nearby traces is
1012. A 15V difference would cause 15 pA of current
to flow, which is greater than the MCP6H71/2/4 family’s
bias current at +25°C (10 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
Guard Ring
VIN– VIN+
VSS
4.7.1
Application Circuits
DIFFERENCE AMPLIFIER
The MCP6H71/2/4 op amps can be used in current
sensing applications. Figure 4-8 shows a resistor
(RSEN) that converts the sensor current (ISEN) to
voltage, as well as a difference amplifier that amplifies
the voltage across the resistor while rejecting common
mode noise. R1 and R2 must be well matched to obtain
an acceptable Common Mode Rejection Ratio
(CMRR). Moreover, RSEN should be much smaller than
R1 and R2 in order to minimize the resistive loading of
the source.
To ensure proper operation, the op amp common mode
input voltage must be kept within the allowed range.
The reference voltage (VREF) is supplied by a
low-impedance source. In single-supply applications,
VREF is typically VDD/2.
.
R1
R2
VREF
VDD
FIGURE 4-7:
for Inverting Gain.
1.
2.
Example Guard Ring Layout
Non-Inverting Gain and Unity-Gain Buffer:
a.Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b.Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
Common mode input voltage.
Inverting Gain and Transimpedance Gain
Amplifiers (convert current to voltage, such as
photo detectors):
a.Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b.Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
 2012 Microchip Technology Inc.
RSEN
VOUT
ISEN
MCP6H71
R1
R2
RSEN << R1, R2
R2
VOUT =  V1 – V 2   ------ + V REF
 R 1
FIGURE 4-8:
High-Side Current Sensing
Using Difference Amplifier.
DS22325B-page 19
MCP6H71/2/4
4.7.2
ACTIVE FULL-WAVE RECTIFIER
The MCP6H71/2/4 family of op amps can be used in
applications such as an active full-wave rectifier, as
shown in Figure 4-9. The amplifier and feedback loops
in this active voltage rectifier circuit eliminate the diode
drop problem that exists in a passive voltage rectifier.
This circuit behaves as a voltage follower (the output
follows the input) as long as the input signal is more
positive than the reference voltage. If the input signal is
more negative than the reference voltage, however, the
circuit behaves as an inverting amplifier with a
Gain = -1V/V. Therefore, the output voltage will always
be above the reference voltage, regardless of the input
signal. The reference voltage (VREF) is supplied by a
low-impedance source. In single-supply applications,
VREF is typically VDD/2.
4.7.3
TRIANGLE WAVES GENERATOR
The MCP6H71/2/4 family of op amps can be used in
function generation applications, such as a triangle
waves generator, as shown in Figure 4-10.
The triangle waves generator consists of an integrator
and one comparator, connected in a positive feedback
loop. This approach is based on the simple fact that
integration of a constant voltage results in a linear
ramp. The op amp is configured as an integrator using
R1 and C1 to provide the triangular output, and the
Schmitt triggers are designed with R2 and R3 to change
the state corresponding to the desired peak voltages of
the triangular wave output. The reference voltage
(VREF) is supplied by a low-impedance source. In
single-supply applications, VREF is typically VDD/2.
R
VIN
R2
C1
R
R3
–
R
R/2
R
Op Amp B
VOUT
+
½
MCP6H72
VREF
+
-
R1
½
MCP6H72
VREF
D1
T1 T2
D2
VOUT
½
MCP6H72
Vo+
Vo-
–
VREF
+
Op Amp A
+
½
-Vo- R3
MCP6H72
-Vo+ R3
Input
Output
-Vo+
R 1C 1
VREF
[V/s]
time
DS22325B-page 20
R2
VREF
FIGURE 4-10:
FIGURE 4-9:
-Vo[V/s]
R 1C 1
R2
Triangle Waves Generator.
time
Active Full-Wave Rectifier.
 2012 Microchip Technology Inc.
MCP6H71/2/4
5.0
DESIGN AIDS
Microchip Technology Inc. provides the basic design
tools needed for the MCP6H71/2/4 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6H71/2/4
op amp is available on the Microchip web site at
www.microchip.com. The model was written and tested
in PSpice, owned by Orcad (Cadence®). For other
simulators, translation may be required.
The model covers a wide aspect of the op amp’s
electrical specifications. Not only does the model cover
voltage, current and resistance of the op amp, but it
also covers the temperature and noise effects on the
behavior of the op amp. The model has not been
verified outside the specification range listed in the op
amp data sheet. The model behaviors under these
conditions cannot be guaranteed to match the actual
op amp performance.
Moreover, the model is intended to be an initial design
tool. Bench testing is a very important part of any
design and cannot be replaced with simulations. Also,
simulation results using this macro model need to be
validated by comparing them to the data sheet
specifications and characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab software is an innovative software
tool that simplifies analog active filter (using op amps)
design. Available at no cost from the Microchip web site
at www.microchip.com/filterlab, the FilterLab design
tool provides full schematic diagrams of the filter circuit
with component values. It also outputs the filter circuit
in SPICE format, which can be used with the macro
model to simulate actual filter performance.
5.3
MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
on the Microchip web site at www.microchip.com/maps,
MAPS is an overall selection tool for Microchip’s product
portfolio that includes analog, memory, MCUs and DSCs.
Using this tool, you can define a filter to sort features for
a parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for data sheets, purchases and sampling of
Microchip parts.
 2012 Microchip Technology Inc.
5.4
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are designed
to help you achieve faster time to market. For a complete listing of these boards and their corresponding
user’s guides and technical information, visit the
Microchip web site: www.microchip.com/analogtools.
Some boards that are especially useful include:
• MCP6XXX Amplifier Evaluation Board 1
• MCP6XXX Amplifier Evaluation Board 2
• MCP6XXX Amplifier Evaluation Board 3
• MCP6XXX Amplifier Evaluation Board 4
• Active Filter Demo Board Kit
• 5/6-Pin SOT-23 Evaluation Board, part number
VSUPEV2
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
part number SOIC8EV
5.5
Application Notes
The following Microchip analog design note and application notes are available on the Microchip web site at
www.microchip.com/appnotes, and are recommended
as supplemental reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
• AN1297: “Microchip’s Op Amp SPICE Macro
Models”’ DS01297
• AN1332: “Current Sensing Circuit Concepts and
Fundamentals”’ DS01332
These application notes and others are listed in:
• “Signal Chain Design Guide”, DS21825
DS22325B-page 21
MCP6H71/2/4
NOTES:
DS22325B-page 22
 2012 Microchip Technology Inc.
MCP6H71/2/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead SOIC (150 mil.) (MCP6H71, MCP6H72)
Example:
MCP6H71E
3
SN e^^1232
256
Example:
8-Lead 2x3 TDFN (MCP6H71, MCP6H72)
Part Number
Code
MCP6H71T-E/MNY
ABC
MCP6H72T-E/MNY
ABD
14-Lead SOIC (150 mil) (MCP6H74)
ABC
232
25
Example:
MCP6H74
E/SL
1232256
14-Lead TSSOP (MCP6H74)
XXXXXXXX
YYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
6H74E/ST
1232
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2012 Microchip Technology Inc.
DS22325B-page 23
MCP6H71/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22325B-page 24
 2012 Microchip Technology Inc.
MCP6H71/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2012 Microchip Technology Inc.
DS22325B-page 25
MCP6H71/2/4
&
!"#$%
! "# $% &"' "" ($ ) %
*++&&&! !+ $
DS22325B-page 26
 2012 Microchip Technology Inc.
MCP6H71/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2012 Microchip Technology Inc.
DS22325B-page 27
MCP6H71/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22325B-page 28
 2012 Microchip Technology Inc.
MCP6H71/2/4
&
' ( )*+,--./ !"0'(%
! "# $% &"' "" ($ ) %
*++&&&! !+ $
 2012 Microchip Technology Inc.
DS22325B-page 29
MCP6H71/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22325B-page 30
 2012 Microchip Technology Inc.
MCP6H71/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2012 Microchip Technology Inc.
DS22325B-page 31
MCP6H71/2/4
&
! "# $% &"' "" ($ ) %
*++&&&! !+ $
DS22325B-page 32
 2012 Microchip Technology Inc.
MCP6H71/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2012 Microchip Technology Inc.
DS22325B-page 33
MCP6H71/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22325B-page 34
 2012 Microchip Technology Inc.
MCP6H71/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2012 Microchip Technology Inc.
DS22325B-page 35
MCP6H71/2/4
NOTES:
DS22325B-page 36
 2012 Microchip Technology Inc.
MCP6H71/2/4
APPENDIX A:
REVISION HISTORY
Revision B (December 2012)
The following is the list of modifications:
• Updated the VDD – VSS value in the Absolute
Maximum Ratings † section.
Revision A (October 2012)
• Original Release of this Document.
 2012 Microchip Technology Inc.
DS22325B-page 37
MCP6H71/2/4
NOTES:
DS22325B-page 38
 2012 Microchip Technology Inc.
MCP6H71/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-X
/XX
Device
Temperature
Range
Package
Device:
MCP6H71:
MCP6H71T:
MCP6H72:
MCP6H72T:
MCP6H74:
MCP6H74T:
Single Op Amp
Single Op Amp (Tape and Reel)
(SOIC and 2x3 TDFN)
Dual Op Amp
Dual Op Amp (Tape and Reel)
(SOIC and 2x3 TDFN)
Quad Op Amp
Quad Op Amp (Tape and Reel)
(SOIC and TSSOP)
Temperature Range:
E
= -40°C to +125°C (Extended)
Package:
MNY* = Plastic Dual Flat, No Lead, (2x3 TDFN),
8-lead (TDFN)
SN
= Lead Plastic Small Outline (150 mil Body),
8-lead (SOIC)
SL
= Plastic Small Outline, (150 mil Body),
14-lead (SOIC)
ST
= Plastic Thin Shrink Small Outline (150 mil Body),
14-lead (TSSOP)
Examples:
a)
MCP6H71-E/SN:
b)
MCP6H71T-E/SN:
c)
MCP6H71T-E/MNY:
d)
MCP6H72-E/SN:
e)
MCP6H72T-E/SN:
f)
MCP6H72T-E/MNY:
g)
MCP6H74-E/SL:
h)
MCP6H74T-E/SL:
i)
MCP6H74-E/ST:
j)
MCP6H74T-E/ST:
Extended Temp.,
8LD SOIC pkg.
Tape and Reel,
Extended Temp.,
8LD SOIC pkg.
Tape and Reel,
Extended Temp.,
8LD 2x3 TDFN pkg.
Extended Temp.,
8LD SOIC pkg.
Tape and Reel,
Extended Temp.,
8LD SOIC pkg.
Tape and Reel,
Extended Temp.,
8LD 2x3 TDFN pkg.
Extended Temp.,
14LD SOIC pkg.
Tape and Reel,
Extended Temp.,
14LD SOIC pkg.
Extended Temp.,
14LD TSSOP pkg.
Tape and Reel,
Extended Temp.,
14LD TSSOP pkg.
* Y = Nickel palladium gold manufacturing designator. Only
available on the TDFN package.
 2012 Microchip Technology Inc.
DS22325B-page 39
MCP6H71/2/4
NOTES:
DS22325B-page 40
 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-756-6
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22325B-page 41
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS22325B-page 42
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
11/29/12
 2012 Microchip Technology Inc.