ON MC74HCT574ANG Octal 3-state noninverting d flip-flop with lsttl-compatible input Datasheet

MC74HCT574A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT574A is identical in pinout to the LS574. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The Output Enable input does not affect the states
of the flip−flops, but when Output Enable is high, all device outputs
are forced to the high−impedance state. Thus, data may be stored even
when the outputs are not enabled.
The HCT574A is identical in function to the HCT374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
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MARKING
DIAGRAMS
PDIP−20
N SUFFIX
CASE 738
1
•
•
Output Drive Capability: 15 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 286 FETs or 71.5 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
MC74HCT574AN
AWLYYWWG
1
20
SOIC−20
DW SUFFIX
CASE 751D
Features
•
•
•
•
•
•
20
1
HCT574A
AWLYYWWG
1
20
TSSOP−20
DT SUFFIX
CASE 948E
1
HCT
574A
ALYWG
G
1
A
WL, L
YY, Y
WW, W
G or G
=
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 10
1
Publication Order Number:
MC74HCT574A/D
MC74HCT574A
OUTPUT
ENABLE
D0
1
2
D1
3
VCC
D0
19
Q0
D1
18
Q1
20
D2
DATA
INPUTS
D2
4
17
Q2
D3
5
16
Q3
D4
6
15
Q4
D5
7
14
Q5
D6
8
13
Q6
D7
9
12
Q7
10
11
CLOCK
GND
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
Figure 1. Pin Assignment
Internal Gate Count*
Value
Units
71.5
ea
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
0.0075
pJ
Speed Power Product
19
18
4
17
5
16
6
15
7
14
8
13
9
12
Q0
Q1
Q2
Q3
Q4
NONINVERTING
OUTPUTS
Q5
Q6
Q7
11
PIN 20 = VCC
PIN 10 = GND
1
Figure 2. Logic Diagram
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Design Criteria
2
3
*Equivalent to a two−input NAND gate.
FUNCTION TABLE
Inputs
OE
L
L
L
H
Output
Clock
D
Q
L,H,
X
H
L
X
X
H
L
No Change
Z
X = don’t care
Z = high impedance
ORDERING INFORMATION
Package
Shipping†
PDIP−20
(Pb−Free)
18 Units / Box
MC74HCT574ADWG
SOIC−20 WIDE
(Pb−Free)
38 Units / Rail
MC74HCT574ADWR2G
SOIC−20 WIDE
(Pb−Free)
1000 Tape & Reel
MC74HCT574ADTR2G
TSSOP−20*
2500 Tape & Reel
Device
MC74HCT574ANG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HCT574A
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MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 secs
(Plastic DIP or SOIC Package)
Plastic DIP†
SOIC Package†
_C
260
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − Plastic DIP: – 10 mW/_C from 65_ to 125_C
− SOIC Package: – 7 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Supply Voltage (Referenced to GND)
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC Input Voltage, Output Voltage
(Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 3)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
– 55 to
25_C
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Input Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOH
Minimum High−Level Output Voltage
Vin = VIH or VIL
|Iout| v 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
Vin = VIH or VIL
|Iout| v 6.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout| v 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout| v 6.0 mA
4.5
0.26
0.33
0.4
Symbol
VOL
Parameter
Maximum Low−Level Output Voltage
Test Conditions
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply Current
(per Package)
Vin = VCC or GND
Iout = 0 mA
5.5
4.0
40
160
mA
IOZ
Maximum Three−State Leakage
Current
Vin = VIL or VIH (Note 1)
Vout = VCC or GND
5.5
− 0.5
– 5.0
– 10
mA
Additional Quiescent Supply Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 mA
DICC
1. Output in high−impedance state.
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3
5.5
≥ – 55_C
25_C to 125_C
2.9
2.4
mA
MC74HCT574A
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
– 55 to
25_C
v 85_C
v 125_C
Unit
fMAX
Maximum Clock Frequency (50% Duty Cycle) (Figures 3 and 6)
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 3 and 6)
30
38
45
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
28
35
42
ns
tPZH,
tPZL
Maximum Propagation Delay Time, Output Enable to Q
(Figures 4 and 7)
28
35
42
ns
tTLH,
Maximum Output Transition Time, Any Output
(Figures 3, 4 and 6)
12
15
18
ns
Maximum Input Capacitance
10
10
10
pF
tTHL
Cin
Typical @ 25°C, VCC = 5.0 V
CPD
58
Power Dissipation Capacitance (Per Flip−Flop)*
pF
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
* Used to determine the no−load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC .
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to 25_C
v 85_C
Figure
Min
tsu
Minimum Setup Time, Data to Clock
5
10
13
15
ns
th
Minimum Hold Time, Clock to Data
5
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
3
15
Maximum Input Rise and Fall Times
3
Symbol
tr, If
Parameter
Max
Min
v 125_C
Max
Min
19
Max
Unit
22
500
ns
500
500
ns
EXPANDED LOGIC DIAGRAM
D0
2
CLOCK
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
11
C
D
C
Q
ENABLE
OUTPUT
D1
3
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
Q
1
19
Q0
18
Q1
17
16
Q2
Q3
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4
15
Q4
14
Q5
13
Q6
12
Q7
MC74HCT574A
SWITCHING WAVEFORMS
tr
CLOCK
tf
3.0 V
2.7 V
1.3 V
0.3 V
tw
3.0 V
OUTPUT
ENABLE
GND
GND
tPZL
1/fmax
tPHL
tPLH
Q
1.3 V
Q
90%
1.3 V
10%
tTLH
HIGH
IMPEDANCE
1.3 V
tPZH
Q
tPLZ
tPHZ
10%
VOL
90%
VOH
1.3 V
HIGH
IMPEDANCE
tTHL
Figure 3.
Figure 4.
TEST POINT
OUTPUT
VALID
DEVICE
UNDER
TEST
3.0 V
1.3 V
DATA
GND
tsu
CL*
th
3.0 V
1.3 V
GND
CLOCK
*Includes all probe and jig capacitance
Figure 5.
Figure 6. Test Circuit
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
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5
MC74HCT574A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
−A−
20
11
1
10
B
L
C
−T−
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
20 PL
0.25 (0.010)
0.25 (0.010)
M
T A
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
M
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
11
X 45 _
E
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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6
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74HCT574A
PACKAGE DIMENSIONS
20X
0.15 (0.006) T U
2X
L
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
PIN 1
IDENT
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
K
K1
SECTION N−N
0.25 (0.010)
N
10
M
0.15 (0.006) T U
S
N
A
−V−
F
DETAIL E
−W−
C
G
D
H
0.100 (0.004)
−T− SEATING
DETAIL E
SOLDERING FOOTPRINT
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
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