ASAHI KASEI AKM CONFIDENTIAL = Target Spec = [AK4703] AK4703 AV SCART switch GENERAL DESCRIPTION The AK4703 offers the ideal features for digital set-top-box systems. The AK4703 includes the audio switches, video switches, video filters, etc. designed primarily for digital set-top-box systems. The AK4703 is offered in a space saving 64-pin LQFP package. FEATURES Analog switches for SCART Audio section THD+N: −86dB (@2Vrms) Dynamic Range: 96dB (@2Vrms) Six Analog Inputs Full Differential Stereo Input for Decoder DAC Two Stereo Input (TV & VCR SCART) Five Analog Outputs Two Stereo Outputs (TV & VCR SCART) One Mono Output (Modulator) Pop Noise Free Circuit for Power on/off Video section Integrated LPF: −35dB@27MHz 75ohm driver 6dB Gain for Outputs Four CVBS/Y inputs (ENCx2, TV, VCR) Three CVBS/Y outputs (RF, TV, VCR) Three R/C inputs (ENCx2, VCR), Two R/C output (TV, VCR) Bi-directional control for VCR-Chroma/Red Two G and B inputs (ENC, VCR), One G and B outputs (TV) TV/VCR input monitor Loop-through Mode for standby Auto-Startup Mode for power saving SCART pin#TBD(Fast Blanking), pin#TBD(Slow Blanking) Control Power supply 5V+/−5% and 12V+/−5% Low Power Dissipation / Low Power Standby Mode Package 64pin LQFP Rev. 0.1 2004/03 -1- AKM CONFIDENTIAL ASAHI KASEI [AK4703] Block Diagram VCOM5 VCOMR VCOML MONOOUT LIN MSEL AMPL AINL+ TVOUTL AINLAMP AINR- TVOUTR AINR+ MONO VCOM12 AMPR TV1-0 RIN VD VP VCRINL VSS VCRINR TVINL VCROUTL VCROUTR TVINR VMONO SCK Register SDA Control VCR1-0 Bias REFI VVSS PDN Audio Block Rev. 0.1 2004/03 -2- AKM CONFIDENTIAL ASAHI KASEI ( Typical connection ) [AK4703] ( Typical connection ) VVD1 VVD2 6dB RFV 6dB TVVOUT RF Mod VVSS ENC CVBS/Y ENCV ENC Y ENCY VCR CVBS/Y VCRVIN TV CVBS TVVIN ENC R/C ENCRC ENC C VCR R/C 6dB ENCC TVRC TV SCART VCRRC ENC G/CVBS ENCG VCR G VCRG ENC B ENCB VCR B VCRB 6dB TVG 6dB TVB Monitor 6dB VCRVOUT VCR SCART 6dB VCRC Video Block ( Typical connection ) VCR FB ( Typical connection ) VCRFB 2V 6dB TVFB 0V TV SCART 0/ 6/ 12V TVSB VCRSB VCR SCART 0/ 6/ 12V Monitor INT Video Blanking Block Rev. 0.1 2004/03 -3- ASAHI KASEI AKM CONFIDENTIAL [AK4703] Ordering Guide AK4703VQ −10 ∼ +70°C 64pin LQFP (0.5mm pitch) Pin Layout TBD Rev. 0.1 2004/03 -4- AKM CONFIDENTIAL ASAHI KASEI [AK4703] PIN/FUNCTION (TBD) No. 1 2 3 Pin Name VCRC VVSS TVVOUT I/O O O 4 VVD2 - 5 6 7 TVRC TVG TVB O O O 8 VVD1 - 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB INT VCRSB TVSB VCRINR VCRINL TVINR TVINL TBD VCROUTR VCROUTL TVOUTR TVOUTL I I I I I I I I I I I I O I/O O I I I I O O O O Function Chrominance Output Pin for VCR Video Ground Pin, 0V Composite/Luminance Output Pin for TV Video Power Supply Pin #2, 5V Normally connected to VVSS with a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic cap. Red/Chrominance Output Pin for TV Green Output Pin for TV Blue Output Pin for TV Video Power Supply Pin #1, 5V Normally connected to VVSS with a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic cap. Blue Input Pin for Encoder Green Input Pin for Encoder Red/Chrominance Input Pin1 for Encoder Chrominance Input Pin2 for Encoder Composite/Luminance Input Pin1 for Encoder Composite/Luminance Input Pin2 for Encoder Composite/Luminance Input Pin for TV Composite/Luminance Input Pin for VCR Fast Blanking Input Pin for VCR Red/Chrominance Input Pin for VCR Green Input Pin for VCR Blue Input Pin for VCR Interrupt Pin for Video Blanking Slow Blanking Input/Output Pin for VCR Slow Blanking Output Pin for TV Rch VCR Audio Input Pin Lch VCR Audio Input Pin Rch TV Audio Input Pin Lch TV Audio Input Pin Rch Analog Output Pin1 Lch Analog Output Pin1 Rch Analog Output Pin2 Lch Analog Output Pin2 Pin layout is TBD. Rev. 0.1 2004/03 -5- AKM CONFIDENTIAL ASAHI KASEI [AK4703] PIN/FUNCTION (TBD, Continued) No. 33 Pin Name VSS I/O - 34 VD 35 36 37 38 39 40 41 42 43 44 LIN AMPL AINL+ AINL− RIN AMPR AINR+ AINR− SCL SDA 45 PDN I 46 47 48 49 RFV VCRVOUT TVFB MONOOUT O O O O 50 VP - 51 VCOM5 O 52 VCOM12 O 53 54 55 56 57 58 59 60 61 62 63 64 VCOMO REFI TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD O I I O I I I O I I I I/O Function Ground Pin, 0V Power Supply Pin, 5V Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic cap. Lch Input Pin Lch Feed back Resistor Output Pin Lch Positive Analog Input Pin Lch Negative Analog Input Pin Rch Input Pin Rch Feed back Resistor Output Pin Rch Positive Analog Input Pin Rch Negative Analog Input Pin Control Data Clock Pin Control Data Pin Power-Down Mode Pin When at “L”, the AK4703 is in the power-down mode and is held in reset. The AK4703 should always be reset upon power-up. Composite Output Pin for RF modulator Composite/Luminance Output Pin for VCR Fast Blanking Output Pin for TV MONO Analog Output Pin Power Supply Pin, 12V Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic cap. Common Voltage Pin Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic cap. Audio Common Voltage Pin Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic cap. The caps affect the settling time of audio bias level. Common Voltage Output Pin TBD Note: All input pins should not be left floating. Pin layout is TBD. Rev. 0.1 2004/03 -6- AKM CONFIDENTIAL ASAHI KASEI [AK4703] ABSOLUTE MAXIMUM RATINGS (VSS = VVSS = 0V; Note 1) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Video Input Voltage Audio Input Voltage (except LIN, RIN, AINL+/−, AINR+/− pins) Audio Input Voltage (except LIN, RIN, AINL+/−, AINR+/− pins) Ambient Operating Temperature Storage Temperature Symbol VD VVD1 VVD2 VP |VSS − VVSS| (Note 2) IIN VIND VINV min −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 max 6.0 6.0 6.0 14 0.3 ±10 VD+0.3 VVD1+0.3 Units V V V V V mA V V VINA −0.3 VP+0.3 V VINA −0.3 VD+0.3 V Ta Tstg −10 −65 70 150 °C °C Note 1. All voltages with respect to ground. Note 2. VSS and VVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS = VVSS = 0V; Note 1) Parameter Power Supply Symbol VD VVD1=VVD2 VP min 4.75 4.75 11.4 typ 5.0 5.0 12 max 5.25 5.25 12.6 Units V V V Note 3. Analog output voltage scales with the voltage of VD. AOUT (typ@0dB) = 2Vrms × VD/5. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. ELECTRICAL CHARACTERISTICS (Ta = 25°C; VP = 12V, VD = 5V; VVD1 = VVD2 = 5V) Power Supplies min typ Power Supply Current Normal Operation (PDN = “H”) (Note 4) TBD VD TBD VVD1+VVD2 TBD VP Power-Down Mode (PDN = “L”) (Note 5) 10 VD 10 VVD1+VVD2 10 VP max Units TBD TBD TBD mA mA mA 100 100 100 µA µA µA Note 4. STBY bit = “L”, All video outputs active. No signal, no load for A/V switches. Note 5. All digital inputs are held at VD or VSS. Rev. 0.1 2004/03 -7- ASAHI KASEI AKM CONFIDENTIAL DIGITAL CHARACTERISTICS (Ta = 25°C; VD = 4.75 ∼ 5.25V) Parameter Symbol min High-Level Input Voltage VIH 2.0 Low-Level Input Voltage VIL Low-Level Output Voltage VOL (SDA pin: Iout= 3mA, INT pin: Iout= 1mA) Input Leakage Current Iin - [AK4703] typ - max 0.8 Units V V - 0.4 V - ±10 µA ANALOG CHARACTERISTICS (AUDIO) (Ta = 25°C; VP = 12V, VD = 5V; VVD1 = VVD2 = 5V; Signal Frequency = 1kHz; Measurement frequency = 20Hz ∼ 20kHz; RL ≥4.5kΩ; 0dB=2Vrms output; unless otherwise specified) Parameter min typ max Units Analog Input: (TVINL/TVINR/VCRINL/VCRINR pins) Analog Input Characteristics Input Voltage 2 Vrms Input Resistance 100 150 kΩ Analog Input: (LIN/RIN pins) Analog Input Characteristics Input Voltage 1 Vrms Input Resistance 40 60 kΩ (Note 6) Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR/MONOOUT pins) Analog Output Characteristics THD+N (at 2Vrms output) (Note 7) dB −86 −80 92 96 dB Dynamic Range (−60dB Output, A-weighted) (Note 7) S/N (A-weighted) (Note 7) 92 96 dB Interchannel Isolation (Note 7, 8) 80 90 dB Interchannel Gain Mismatch (Note 7, 8) 0.3 dB Gain Drift 200 ppm/°C Load Resistance (AC-Lord, Note 10) TVOUTL/R, VCROUTL/R, MONOOUT 4.5 kΩ Output Voltage (Note 9, 10) 1.85 2 2.15 Vrms Power Supply Rejection (PSR) (Note 11) 50 dB Note 6. Measured by Audio Precision System Two Cascade. Note 7. Analog In to TVOUT. Path : AINL+/− (AINR+/−) → TVOUTL (TVOUTR) Note 8. Between TVOUTL and TVOUTR with analog inputs (AINL/R+/−) 1kHz/0dB. Note 9. THD+N : −80dB(min. at 2Vrns). Note 10. Analog input voltage by LIN/RIN pins (0dB). Stereo output (typ@0dBFS) = 2Vrms × VD/5. Do not output signals over 3Vrms. Note 11. The PSR is applied to VD with 1kHz, 100mV. FILTER CHARACTERISTICS (Ta = 25°C; VP = 11.4 ∼ 12.6V, VD = 4.75 ∼ 5.25V, VVD1 = VVD2 = 4.75 ∼ 5.25V) Parameter Symbol min typ LPF FR Frequency Response 0 ∼ 20.0kHz ± 0.5 Rev. 0.1 max Units - dB 2004/03 -8- AKM CONFIDENTIAL ASAHI KASEI [AK4703] ANALOG CHARACTERISTICS (VIDEO) (Ta = 25°C; VP = 12V, VD = 5V; VVD1 = VVD2 = 5V; unless otherwise specified.) Parameter Conditions min Sync Tip Clamp Voltage at output pin. Chrominance Bias Voltage at output pin. Gain Input = 0.3Vp-p, 100kHz 5.5 Interchannel Gain Mismatch TVRC, TVG, TVB. Input = 0.3Vp-p, 100kHz. −0.3 Frequency Response Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz. at 12MHz. −1.0 at 27MHz. Group Delay Distortion At 4.43MHz with respect to 1MHz. Input Impedance Chrominance input (internally biased) 40 Input Signal f = 100kHz, maximum with distortion < 1.0%, gain = 6dB. Load Resistance (Note 12) 150 Load Capacitance C1 (Note 12) C2 (Note 12) Dynamic Output Signal f = 100kHz, maximum with distortion < 1.0% Y/C Crosstalk f = 4.43MHz, 1Vp-p input. Among TVVOUT, TVRC, VCRVOUT and VCRC outputs. S/N Reference Level = 0.7Vp-p, CCIR 567 weighting. BW = 15kHz to 5MHz. Differential Gain 0.7Vpp 5steps modulated staircase. chrominance &burst are 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. chrominance &burst are 280mVpp, 4.43MHz. typ 0.7 2.2 6 - 60 TBD 15 - Units V V dB dB dB dB dB ns kΩ - 1.5 Vpp - - 400 15 3 Ω pF pF Vpp −50 - dB 74 - dB TBD - % TBD - Degree −3 −35 max 6.5 0.3 0.5 Note 12. Refer the Figure 1. R1 75 ohm Video Signal Output R2 75 ohm C1 C2 max: 15pF max: 400pF Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2. Rev. 0.1 2004/03 -9- ASAHI KASEI AKM CONFIDENTIAL SWITCHING CHARACTERISTICS (Ta = 25°C; VP = 11.4 ∼ 12.6V, VD = 4.75 ∼ 5.25V, VVD1 = VVD2 = 4.75 ∼ 5.25V; CL = 20pF) Parameter Symbol min typ max Control Interface Timing (I2C Bus): 400 fSCL SCL Clock Frequency 1.3 tBUF Bus Free Time Between Transmissions 0.6 tHD:STA Start Condition Hold Time (prior to first clock pulse) 1.3 tLOW Clock Low Time 0.6 tHIGH Clock High Time 0.6 tSU:STA Setup Time for Repeated Start Condition 0 SDA Hold Time from SCL Falling (Note 13) tHD:DAT 0.1 tSU:DAT SDA Setup Time from SCL Rising 0.3 tR Rise Time of Both SDA and SCL Lines 0.3 tF Fall Time of Both SDA and SCL Lines 0.6 tSU:STO Setup Time for Stop Condition 50 0 tSP Pulse Width of Spike Noise Suppressed by Input Filter Reset Timing PDN Pulse Width (Note 14) tPD 150 [AK4703] Units kHz µs µs µs µs µs µs µs µs µs µs ns ns Note 13. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 14. The AK4703 should be reset by PDN pin = “L” upon power up. Note 15. I2C is a registered trademark of Philips Semiconductors. Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips. Rev. 0.1 2004/03 - 10 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] Timing Diagram VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start I2C Bus mode Timing tPD PDN VIL Power-down Timing Rev. 0.1 2004/03 - 11 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] OPERATION OVERVIEW 1. System Reset and Power-down options The AK4703 should be reset once by bringing PDN pin = “L” upon power-up. The AK4703 has several operation modes. The PDN pin, AUTO bit, BIAS bit, STBY bit and AMP bit control operation modes as shown in Table 1 and Table 2 Mode 0 PDN pin “L” AUTO bit * STBY bit * BIAS bit * AMPPD bit * 1 “H” 1 * * * 2 3 “H” “H” 0 0 1 1 1 0 * * 4 “H” 0 0 1 1 5 “H” 0 0 1 0 6 “H” 0 0 0 1 7 “H” 0 0 0 0 Mode Full Power-down Auto Startup mode (Power-on Default) Standby & Mute Standby Mute (AMP power down) Mute (AMP operation) Normal operation (AMP power down & Analog input) Normal operation (AMP operation) Table 1. Operation Mode Settings (*: Don’t Care) Register Control Not available Mode 0 1 Full Power-down Auto Startup mode (Power-on Default) 2 Standby & Mute 3 Standby Mute (AMP power down) Mute (AMP operation) Normal operation (AMP power down & Analog input) Normal operation (AMP operation) 4 5 6 7 No video input Video input (**) Audio Bias Level Video Output TVFB, TVSB VCRSB Power down Hi-Z Hi-Z Pull-down (*) Active Active (***) Active Active Power down Active Available Power down Hi-Z / Active Active (****) (*): Internally pulled down by 120kΩ (typ) resistor. (**): Video input to TVVIN or VCRVIN. (***): VCRC outputs 0V for termination. (****): TVOUTL/R are muted by Mute bit in the default state. Table 2. Status of each operation modes Rev. 0.1 2004/03 - 12 - ASAHI KASEI AKM CONFIDENTIAL [AK4703] Full Power-down Mode The AK4703 should be reset once by bringing PDN pin = “L” upon power-up. PDN pin: Power down pin L: Device power down. H: Normal operation. Auto Startup Mode After when the PDN pin is set to “H”, the AK4703 is in the auto startup mode. In this mode, all blocks except for the video detection circuit are powered down. Once the video detection circuit detects video signal from TVVIN pin or VCRVIN pin, the AK4703 goes to the stand-by mode automatically and sends “H” pulse via INT pin. To exit the auto startup mode, set the AUTO bit to “0”. AUTO bit (00H D3): Auto startup bit 0: Auto startup disable. (Manual startup) 1: Auto startup enable. (Default) AMP Power-down Mode The internal AMP block can be powered-down by AMPPD bit. When AMPPD bit =”1”, the internal AMP block is powered-down. AMPPD bit (00H D2): AMP power-down bit 0: Normal operation. 1: AMP power-down. (Default) Bias Mode When the BIAS bit = “1”, the bias voltage on the audio output goes to GND level. Bringing BIAS bit to “0” changes this bias voltage smoothly from GND to VP/2 by 2sec (typ.). This removes the huge click noise related the sudden change of bias voltage at power-on. The change of BIAS bit from “1” to “0” also makes smooth transient from VP/2 to GND by 2sec (typ). This removes the huge click noise related the sudden change of bias voltage at power-off. BIAS bit (00H D1): Bias-off bit 0: Normal operation. 1: Set the audio bias to GND. (Default) Standby Mode When the AUTO bit = BIAS bit = “0” and the STBY bit = “1”, the AK4703 is forced into TV-VCR loop through mode. In this mode, the sources of TVOUTL/R and MONOOUT pins are fixed to VCRINL/R pins; the sources of VCROUTL/R are fixed to TVINL/R pins respectively. All register values themselves are NOT changed by STBY bit = “1”. STBY bit (00H D0): Standby bit 0: Normal operation. 1: Standby mode. (Default) Normal Operation Mode To change analog switches, set the AUTO bit, BIAS bit and STBY bit to “0”. The AK4703 is in power-down mode until PDN pin = “H”. The Figure 2 shows an example of the system timing at the power-down and power-up by PDN pin. Rev. 0.1 2004/03 - 13 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] Typical Operation Sequence (auto setup mode) The Figure 2 shows an example of the system timing at auto setup mode. PDN pin Low Power Mode TVVIN don’t care VCRVIN don’t care TVVOUT, VCRVOUT No Signal Signal in No Signal No Signal Hi-Z Audio out (DC) Low Power Mode Low Power Mode Signal in No Signal Signal in Active (loop-through) Hi-Z No Signal Active (loop-through) Active (loop-through) don’t care don’t care Hi-Z Active (loop-through) (GND) Figure 2. Typical operating sequence (auto setup mode) Typical Operation Sequence (except auto setup mode) The Figure 3 shows an example of the system timing at auto setup mode. PDN pin AUTO bit BIAS bit STBY bit TV-Source select “Stand-by“ “Mute” “1” (default) “1” (default) “0” “0” “1” “1” (default) fixed to VCR in(Loop-through) “Stand-by“ “0” VCR in (default) “1” “0” AMP “1” VCR in (2) offset calibration TV out VCR in VCR in (1) Notes: (1) Mute the analog outputs externally if click noise (1) adversely affects the system. (2) In case of the CAL bit = “1”, the offset calibration is always executed when the source of TVOUTL/R pins are switched to AMP after the STBY bit is changed to “0”. To disable this function, set the CAL bit = “0”. Figure 3. Typical operating sequence (except auto setup mode) Rev. 0.1 2004/03 - 14 - ASAHI KASEI AKM CONFIDENTIAL [AK4703] 2. Audio Block Switch Control The AK4703 has switch matrixes designed primarily for SCART routing. Those are controlled via the control register as shown in, Table 3, Table 4 and Table (Please refer to the Block Diagram). (01H: D1-D0) TV1 TV0 Source of TVOUTL/R 0 0 AMP 0 1 VCRIN (Default) 1 0 Mute 1 1 LIN/RIN Table 3. TVOUT Switch Configuration (01H: D2-D0) MSEL TV1 TV0 Source of MONOOUT 0 0 0 AMP (L+R)/2 0 0 1 AMP (L+R)/2 0 1 0 AMP (L+R)/2 0 1 1 (Reserved) 1 0 0 AMP (L+R)/2 1 0 1 VCRIN (L+R)/2 1 1 0 Mute 1 1 1 (LIN+RIN)/2 Table 4. MONOOUT Switch Configuration (01H: D5-D4) VCR1 VCR0 Source of VCROUTL/R 0 0 AMP 0 1 TVIN (Default) 1 0 Mute 1 1 (Reserved) Table 5. VCROUT Switch Configuration Rev. 0.1 2004/03 - 15 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] 3. Video Block Video Switch Control The AK4703 has switches for TV, VCR and RF modulator. Each switch can be controlled via registers independently. When AUTO bit = “1” or STBY bit = “1”, these switches setting is ignored and set to fixed configuration (loop-through mode). Please refer the auto setup mode and standby mode. (04H: D2-D0) Source of Source of Source of TVVOUT pin TVRC pin TVG pin 000 (Hi-Z) (Hi-Z) (Hi-Z) 001 ENCV pin ENCRC pin ENCG pin 010 ENCV pin ENCRC pin Hi-Z 011 ENCY pin ENCC pin Hi-Z 100 VCRVIN pin VCRRC pin VCRG pin 101 TVVIN pin (Hi-Z) (Hi-Z) 110 111 Table 6. TV video output (Please refer notes) Mode VTV2-0 bit Shutdown Encoder CVBS /RGB Encoder Y/C 1 Encoder Y/C 2 VCR (default) TV CVBS (Reserved) (Reserved) Source of TVB pin (Hi-Z) ENCB pin (Hi-Z) (Hi-Z) VCRB pin (Hi-Z) - (04H: D5-D3) Source of VCRVOUT pin Shutdown 000 (Hi-Z) Encoder CVBS or Y/C 1 001 ENCV pin Encoder CVBS or Y/C 2 010 ENCY pin TV CVBS (default) 011 TVVIN pin VCR 100 VCRVIN pin (Reserved) 101 (Reserved) 110 (Reserved) 111 Table 7. VCR video output (Please refer notes) Mode VVCR2-0 bit (04H: D7-D6) Mode Encoder CVBS1 Source of VCRC pin (Hi-Z) ENCRC pin ENCC pin (Hi-Z) VCRRC pin - VRF1-0 bit 00 Source of RFV pin ENCV pin ENCG pin Encoder CVBS2 01 (Note 2) VCR (Default) 10 VCRVIN pin Shutdown 11 (Hi-Z) Table 8. RF video output Note 1. When input the video signal via ENCRC pin or VCRRC pin, set CLAMP1-0 bits respectively. Note 2. When VTV2-0 bit = “001”, TVG bit = “1” and VRF1-0 bit = “01”, RFV pin output is same as TVG pin output (Encoder G). Rev. 0.1 2004/03 - 16 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] Video Output Control (05H: D6-D0) Each video output can be set to Hi-Z individually via control registers. These settings are ignored when the AUTO bit = “1”. When the CIO bit = “1”, the VCRC pin outputs 0V even if the VCRC bit = “0”. When the CIO bit = “0”, the VCRC pin follows the setting of VCRC bit. Please refer the “Red/Chroma Bi-directional Control for VCR SCART”. TVV: TVVOUT output control TVR: TVRCOUT output control TVG: TVGOUT output control TVB: TVBOUT output control VCRV: VCRVOUT output control VCRC: VCRC output control TVFB: TVFB output control 0: Hi-Z. (Default) 1: Active. Red/Chroma Bi-directional Control for VCR SCART (05H: D7, D5) The 4703 supports the bi-directional Red/Chroma signal on the VCR SCART. (CIO bit & VCRC bit) #15 pin 75 VCRC pin VCRRC pin VCR SCART 0.1u (AK4703) Figure 5. Red/Chroma Bi-directional Control CIO bit VCRC bit State of VCRC pin 0 0 Hi-z (default) 0 1 Active 1 0 Connected to GND 1 1 Connected to GND Table 9. Red/Chroma Bi-directional Control Rev. 0.1 2004/03 - 17 - ASAHI KASEI AKM CONFIDENTIAL [AK4703] Clamp and DC-restore circuit control (06H: D6-D5, D3-D2) Each CVBS and Y input has the sync tip clamp circuit. The sync tip voltage at each output is 0.7V (typ). This corresponds 0.35V (typ) at the SCART connector when matched by 75Ω resistors. The CLAMP1-0 bits select the input circuit for ENCRC pin (Encoder Red/Chroma) and VCRRC pin (VCR Red/Chroma) respectively. VCLP1-0 bits select the source of DC-restore circuit. CLAMP1: Encoder Red/Chroma (ENCRC pin) input clamp control 0: DC restore clamp active (for RED signal. Default) 1: Biased (for Chroma signal.) CLAMP0: VCR R/C (VCRRC pin) input clamp control 0: DC restore clamp active (for RED signal) 1: Biased (for Chroma signal. Default.) VCLP1-0: DC restore source control When the AUTO bit = “1”, the source is fixed to VCRVIN. VCLP1 bit VCLP0 bit Sync Source of DC Restore 0 0 ENCV (Default) 0 1 ENCY 1 0 VCRVIN 1 1 (Reserved) Table 10. DC restore source control Rev. 0.1 2004/03 - 18 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] 4. Blanking Control The AK4703 supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV/VCR SCART. Input/Output Control for Fast/Slow Blanking FB1-0: TV Fast Blanking output control (07H: D1-D0) FB1 bit FB0 bit TVFB pin Output Level 0 0 0V (Default) 0 1 4V 1 0 Same as VCR FB input (4V/0V) 1 1 (Reserved) Table 11. TV Fast Blanking output (Note: minimum load is 150Ω) SBT1-0: TV Slow Blanking output control (07H: D3-D2) SBT1 bit SBT0 bit TVSB pin Output Level 0 0 < 2V (Default) 0 1 5V <, < 7V 1 0 (Reserved) 1 1 10V < Table 12. TV Slow Blanking output (Note: minimum load is 10kΩ) SBV1-0: VCR Slow Blanking output control (07H: D5-D4) SBV1 bit SBV0 bit VCRSB pin Output Level 0 0 < 2V (Default) 0 1 5V <, < 7V 1 0 (Reserved) 1 1 10V < Table 13. VCR Slow Blanking output (Note: minimum load is 10kΩ) SBIO1-0: TV/VCR Slow Blanking I/O control (07H: D7-D6) SBIO1 bit SBIO0 bit 0 0 0 1 1 0 1 1 VCRSB pin Direction TVSB pin Direction Output Output (Controlled by SBV1-0 bits) (Controlled by SBT1-0 bits) (Reserved) (Reserved) Input Output (Stored in SVCR1-0 bits) (Controlled by SBT1-0 bits) Input Output (Stored in SVCR1-0 bits) (Same output as VCR SB) Table 14. TV/VCR Slow Blanking I/O control Rev. 0.1 (Default) 2004/03 - 19 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] 5. Monitor Options and INT function Monitor Options (08H: D4-D0) The AK4703 has several monitors for the input DC level of VCR slow blanking, the input DC level of VCR fast blanking and signals input to TVVIN or VCRVIN pins. SVCR1-0 bits, FVCR bit, VCMON bit and TVMON bit are reflected to these values. SVCR1-0: VCR Slow blanking status monitor SVCR1-0 bits reflect the voltage at VCRSB pin only when the VCRSB is in the input mode. When the VCRSB is in the output mode, SVCR1-0 bits hold previous value. VCRSB pin input level SVCR1 bit SVCR0 bit < 2V 0 0 4.5 to 7V 0 1 (Reserved) 1 0 9.5 < 1 1 Table 15. VCR Slow Blanking monitor FVCR: VCR Fast blanking input level monitor This bit is enabled when TVFB bit = “1”. VCRFB pin input level FVCR bit < 0.4V 0 1V < 1 Table 16. VCR Fast Blanking monitor (Typical threshold is 0.7V) VCMON: VCR input monitor 0: No video signal detected via VCRVIN pin. 1: Detects video signal via VCRVIN pin. TVMON: TV input monitor 0: No video signal detected via TVVIN pin. 1: Detects video signal via TVVIN pin. Rev. 0.1 2004/03 - 20 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] INT Function and Mask Options (09H: D3-D1) Changes of the 08H status can be monitored via the INT pin. The INT pin is the open drain output and goes “L” for 2µs (typ.) when the status of 08H is changed. This pin should be connected to VD (typ. 5V) through 10kΩ resistor. MVC bit, MTV bit, MFVCR bit and MSVCR bit control the reflection of the status change of these monitors onto the INT pin from report to prevent to masks each monitor. MVC: VCR input monitor mask AUTO bit 0 0 1 MVC bit 0 1 0 Reflection of the change of VCMON bit to INT pin Reflect NOT reflect (e.g. masked) Reflect 1 1 Reflect (Default ) Table 17. Reflection of VCMON change MTV: TV input monitor mask AUTO bit 0 0 1 MTV bit 0 1 0 Reflection of the change of TVMON bit to INT pin Reflect NOT reflect (e.g. masked) Reflect 1 1 Reflect (Default ) Table 18. Reflection of TVMON change MFVCR: FVCR Monitor mask 0: Change of MFVCR is reflected to INT pin. (Default) 1: Change of MFVCR is NOT reflected to INT pin. MSVCR: SVCR1-0 Monitor mask 0: Change of SVCR1-0 is reflected to INT pin. (Default) 1: Change of SVCR1-0 is NOT reflected to INT pin. Rev. 0.1 2004/03 - 21 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] 6. Control Interface I2C-bus Control Mode 1. WRITE Operations Figure 6 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 12). After the START condition, a slave address is sent. This address is 7bits long followed by an eighth bit that is a data direction bit (R/W). The most significant seven bits of the slave address are fixed as “0010001”. If the slave address match that of the AK4703, the AK4703 generates the acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 13). A “1” for R/W bit indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. The second byte consists of the address for control registers of the AK4703. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 8). The data after the second byte contain control data. The format is MSB first, 8bits (Figure 9). The AK4703 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 12). The AK4703 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4703 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 09H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 14) except for the START and the STOP condition. S T A R T SDA S S T O P R/W= “0” Slave Address Sub Address(n) A C K Data(n+x) Data(n+1) Data(n) A C K A C K A C K A C K P A C K Figure 6. Data transfer sequence at the I2C-bus mode 0 0 1 0 0 0 1 R/W A2 A1 A0 D2 D1 D0 Figure 7. The first byte 0 0 0 A4 A3 Figure 8. The second byte D7 D6 D5 D4 D3 Figure 9. Byte structure after the second byte Rev. 0.1 2004/03 - 22 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] 2. READ Operations Set R/W bit = “1” for READ operations. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 09H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The AK4703 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. 2-1. CURRENT ADDRESS READ The AK4703 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4703 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4703 discontinues transmission. S T A R T SDA S S T O P R/W= “1” Slave Address Data(n+1) Data(n) A C K A C K Data(n+x) Data(n+2) A C K A C K A C K P A C K Figure 10. CURRENT ADDRESS READ 2-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start condition, slave address (R/W bit = “0”) and then the register address to read. After the register’s address is acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to “1”. Then the AK4703 generates an acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4703 discontinues transmission. S T A R T SDA S S T A R T R/W= “0” Slave Address Sub Address(n) A C K S A C K S T O P R/W= “1” Slave Address Data(n) A C K Data(n+x) Data(n+1) A C K A C K A C K P A C K Figure 11. RANDOM ADDRESS READ Rev. 0.1 2004/03 - 23 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] SDA SCL S P start condition stop condition Figure 12. START and STOP conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 13. Acknowledge on the I2C-bus SDA SCL data line stable; data valid change of data allowed Figure 14. Bit transfer on the I2C-bus Rev. 0.1 2004/03 - 24 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H Register Name Control Switch Reserved Zerocross Video switch Video output enable Video volume/clamp S/F Blanking control S/F Blanking monitor Monitor mask D7 0 MUTE 0 0 VRF1 CIO 0 SBIO1 0 0 D6 0 0 0 VMONO VRF0 TVFB VCLP1 SBIO0 0 0 D5 0 VCR1 0 0 VVCR2 VCRC VCLP0 SBV1 0 0 D4 0 VCR0 0 0 VVCR1 VCRV 0 SBV0 TVMON MTV D3 AUTO MONO 0 0 VVCR0 TVB CLAMP1 SBT1 VCMON MVC D2 AMPPD 0 0 ZERO VTV2 TVG CLAMP0 SBT0 FVCR MFVCR D1 BIAS TV1 0 ZTM1 VTV1 TVR 0 FB1 SVCR1 MSVCR D0 STBY TV0 0 ZTM0 VTV0 TVV 0 FB0 SVCR0 0 When the PDN pin goes “L”, the registers are initialized to their default values. While the PDN pin = “H”, all registers can be accessed. Do not write any data to the register over 09H. Rev. 0.1 2004/03 - 25 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] Register Definitions Addr 00H Register Name Control R/W Default D7 0 D6 0 D5 0 D4 0 0 0 0 0 D3 AUTO D2 AMPPD D1 BIAS D0 STBY 1 1 1 1 R/W STBY: Standby control 0: Normal Operation 1: Standby Mode (Default). All registers are not initialized. DAC : Powered down and timings are reset. Source of TVOUT : fixed to VCRIN, Source of VCROUT : fixed to TVIN, Source of MONOOUT : fixed to VCRIN, Source of TVVOUT : fixed to VCRVIN (or Hi-Z), Source of TVRC : fixed to VCRRC (or Hi-Z), Source of TVG : fixed to VCRG (or Hi-Z), Source of TVB : fixed to VCRB (or Hi-Z), Source of VCRVOUT : fixed to TVVIN (or Hi-Z), Source of VCRC : fixed to Hi-Z or VSS (controlled by CIO bit). BIAS: Audio output control 0: Normal operation 1: ALL Audio outputs to GND (Default) AMPPD: AMP power down control 0: Normal operation 1: AMP power down (Default) AUTO: Auto startup bit 0: Auto startup disable (Manual startup). 1: Auto startup enable (Default). Note: When the SBIO1 bit = “1”(Default = “0”), the change of AUTO bit may cause a “L” pulse on INT pin. Rev. 0.1 2004/03 - 26 - AKM CONFIDENTIAL ASAHI KASEI Addr 01H Register Name Switch R/W Default D7 MUTE D6 0 D5 VCR1 D4 VCR0 1 0 0 1 [AK4703] D3 MONO R/W 0 D2 0 D1 TV1 D0 TV0 0 0 1 TV1-0: TVOUTL/R pins source switch 00: AMP 01: VCRINL/R pins (Default) 10: MUTE 11: LIN/RIN MONO: Mono select for TVOUTL/R pins 0: Stereo. (Default) 1: Mono. (L+R)/2 VCR1-0: VCROUTL/R pins source switch 00: AMP 01: TVINL/R pins (Default) 10: MUTE 11: Reserved MUTE: Mute switch 0: Normal operation 1: Mute (Default) When Mute bit = “1”, TVOUTL/R outputs VCOM voltage after TVOUTL/R output is zero-crossing. Addr 02H Register Name Selector R/W Default D7 0 D6 0 D5 0 D4 0 0 0 0 0 D3 0 D2 MSEL D1 0 D0 0 0 1 0 0 R/W MSEL: Selector for MONOOUT pin 0: Mixed output of AMP 1: Mixed output of TV1-0 switch (Default) Rev. 0.1 2004/03 - 27 - AKM CONFIDENTIAL ASAHI KASEI Addr 03H Register Name Zerocross R/W Default D7 0 VMONO D6 D5 0 D4 0 0 0 0 0 [AK4703] D3 0 D2 ZERO D1 ZTM1 D0 ZTM0 0 1 0 0 R/W ZTM1-0: The time length control of zero-cross timeout 00: typ. 10ms (Default) 01: typ. 20ms 10: typ. 40ms 11: typ. 80ms ZERO: Zero-cross detection enable for TVOUT output 0: Disable The TVOUT outputs VCOM voltage immediately without zero-cross when MUTE bit is “1”. 1: Enable (Default) The TVOUT outputs VCOM voltage when timeout or zero-cross before timeout when MUTE bit is “1”. VMONO: Mono select for VCROUTL/R pins 0: Stereo. (Default) 1: Mono. (L+R)/2 Addr 04H Register Name Video switch R/W Default D7 VRF1 D6 VRF0 D5 VVCR2 1 0 0 D4 D3 VVCR1 VVCR0 R/W 1 1 D2 VTV2 D1 VTV1 D0 VTV0 1 0 0 VTV2-0: Selector for TV video output Please refer the Table 6. VVCR2-0: Selector for VCR video output Please refer the Table 7. VRF1-0: Selector for RFV pin output Please refer the Table 8. Rev. 0.1 2004/03 - 28 - AKM CONFIDENTIAL ASAHI KASEI Addr 05H Register Name Output Enable R/W Default D7 CIO D6 TVFB D5 VCRC 0 0 0 D4 D3 VCRV TVB R/W 0 0 [AK4703] D2 TVG D1 TVR D0 TVV 0 0 0 D2 CLAMP0 D1 0 D0 0 1 0 0 TVV: TVVOUT output control TVR: TVRCOUT output control TVG: TVGOUT output control TVB: TVBOUT output control VCRV: VCRVOUT output control VCRC: VCRC output control (Please refer the Table 9) TVFB: TVFB output control 0: Hi-Z (Default) 1: Active. When the CIO pin = “H”, the VCRC pin is connected to GND even if VCRC bit = “0”. When the CIO pin = “L”, the VCRC pin follows the setting of VCRC bit. CIO: VCRC pin I/O control Please refer the Table 9. Addr 06H Register Name Video volume R/W Default D7 0 D6 VCLP1 D5 VCLP0 0 0 0 D4 0 D3 CLAMP1 R/W 0 0 CLAMP1: Encoder R/Chroma (ENCRC pin) input clamp control 0: DC restore clamp active (for RED signal. Default) 1: Biased (for Chroma signal.) CLAMP0: VCR R/C (VCRC pin) input clamp control 0: DC restore clamp active (for RED signal) 1: Biased (for Chroma signal. Default.) VCLP1-0: DC restore source control 00: ENCV pin (Default) 01: ENCY pin 10: VCRVIN pin 11: (Reserved) When the AUTO bit = “1”, the source is fixed to VCRVIN pin. Rev. 0.1 2004/03 - 29 - AKM CONFIDENTIAL ASAHI KASEI Addr 07H Register Name S/F Blanking R/W Default D7 SBIO1 D6 SBIO0 D5 SBV1 0 0 0 D4 D3 SBV0 SBT1 R/W 0 0 [AK4703] D2 SBT0 D1 FB1 D0 FB0 0 0 0 FB1-0: TV Fast Blanking output control (for TVFB pin) 00: 0V (Default) 01: 4V 10: follow VCR FB input (4V/0V) 11: (Reserved) SBT1-0: TV Slow Blanking output control (for TVSB pin. minimum load is 10kΩ.) 00: < 2V (Default) 01: 5V <, < 7V 10: (Reserved) 11: 10V < SBV1-0: VCR Slow Blanking output control (for VCRSB pin. minimum load is 10kΩ.) 00: < 2V (default) 01: 5V <, < 7V 10: (Reserved) 11: 10V < SBIO1-0: TV/VCR Slow Blanking I/O control (Please refer the Table 14.) Rev. 0.1 2004/03 - 30 - AKM CONFIDENTIAL ASAHI KASEI Addr 08H Register Name SB/FB monitor R/W Default D7 0 D6 0 D5 0 0 0 0 D4 D3 TVMON VCMON READ 0 0 [AK4703] D2 FVCR D1 SVCR1 D0 SVCR0 0 0 0 SVCR1-0: VCR Slow blanking status monitor SVCR1-0 bits reflect the voltage at VCRSB pin only when the VCRSB is in the input mode. When the VCRSB is in the output mode, SVCR1-0 bits hold previous value. VCRSB pin input level SVCR1 bit SVCR0 bit < 2V 0 0 4.5 to 7V 0 1 (Reserved) 1 0 9.5 < 1 1 Table 19. VCR Slow Blanking monitor FVCR: VCR Fast blanking input level monitor This bit is enabled when TVFB bit = “1”. VCRFB pin input level FVCR bit < 0.4V 0 1V < 1 Table 20. VCR Fast Blanking monitor (Typical threshold is 0.7V) VCMON: VCR input monitor 0: No video signal detected via VCRVIN pin. 1: Detects video signal via VCRVIN pin. TVMON: TV input monitor 0: No video signal detected via TVVIN pin. 1: Detects video signal via TVVIN pin. Rev. 0.1 2004/03 - 31 - AKM CONFIDENTIAL ASAHI KASEI Addr 09H Register Name Monitor mask R/W Default D7 0 D6 0 D5 0 D4 MTV 0 0 0 0 D3 MVC R/W 1 [AK4703] D2 MFVCR D1 MSVCR D0 0 0 0 0 MSVCR: SVCR1-0 bits Monitor mask 0: The INT pin reflects the change of SVCR1-0 bit. (Default) 1: The INT pin does not reflect the change of SVCR1-0 bits. MFVCR: FVCR Monitor mask 0: The INT pin reflects the change of MFVCR bit. (Default) 1: The INT pin does not reflect the change of MFVCR bit. MVC: VCR input monitor mask Please refer the Table 17. MTV: TV input monitor mask Please refer the Table 18. Rev. 0.1 2004/03 - 32 - ASAHI KASEI AKM CONFIDENTIAL [AK4703] SYSTEM DESIGN TBD Figure 15. Typical Connection Diagram Rev. 0.1 2004/03 - 33 - ASAHI KASEI AKM CONFIDENTIAL [AK4703] Grounding and Power Supply Decoupling VD, VP, VVD1, VVD2, VSS and VVSS should be supplied from analog supply unit with low impedance and be separated from system digital supply. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor should be attached to these pins to eliminate the effects of high frequency noise. The 0.1µF ceramic capacitor should be placed as near to VD (VP, VVD1, VVD2) as possible. Voltage Reference Each DVCOM/PVCOM are signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor should be attached to these VCOM pins to eliminate the effects of high frequency noise. No load current may be drawn from these VCOM pins. All signals, especially clocks, should be kept away from these VCOM pins in order to avoid unwanted coupling into the AK4703. Analog Audio Outputs The analog outputs are also single-ended and centered on 5.6V(typ.). The output signal range is typically 2Vrms (typ@VD=5V). Rev. 0.1 2004/03 - 34 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] External Circuit Example Analog Audio Input pin 300ohm (Cable) MONOIN TVINL/R VCRINL/R AMPL/R 0.47µF Analog Audio Output pin MONOOUT TVOUTL/R VCROUTL/R 300ohm 10µF (Cable) Total > 4.5kohm Analog Video Input pin 75ohm (Cable) ENCV, ENCY, VCRVIN, TVVIN, ENCRC, ENCC, VCRRC, ENCG, VCRG, ENCB, VCRB 0.1µF 75ohm Analog Video Output pin TVVOUT, TVRC TVG, TVR, RFV VCRVOUT, VCRC 75ohm (Cable) max 400pF max 15pF Rev. 0.1 75ohm 2004/03 - 35 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] Slow Blanking pin TVSB VCRSB (Cable) 400ohm (max 500ohm) max 3nF (with 400ohm) min: 10k ohm Fast Blanking Input pin VCRFB 75ohm (Cable) 75ohm Fast Blanking Output pin 75ohm TVFB (Cable) 75ohm Rev. 0.1 2004/03 - 36 - AKM CONFIDENTIAL ASAHI KASEI [AK4703] PACKAGE TBD Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate Rev. 0.1 2004/03 - 37 - ASAHI KASEI AKM CONFIDENTIAL [AK4703] MARKING TBD XXXXXXXX: Date code identifier IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Rev. 0.1 2004/03 - 38 -