HI-8588-10
ARINC 429 LINE RECEIVER
July 2006
DESCRIPTION
PIN CONFIGURATION
The HI-8588-10 ARINC 429 bus interface receiver is similar to the HI-8588 with the exception that it allows an external 10 Kohm resistor in series with each ARINC input without affecting the ARINC input thresholds. The product is
especially useful in applications where lightning protection
circuitry is also required. In addition, the test inputs force
both of the outputs to zero instead of open circuit. The analog/digital CMOS product requires only a 5 volt supply and
is available in a 8-pin SOIC package.
Each side of the ARINC bus must be connected through a
10 Kohm series resistor in order for the chip to detect the
correct ARINC levels. The typical 10 volt differential signal
is translated and input to a window comparator and latch.
The comparator levels are set so that with the external
10 Kohm resistors they are just below the standard 6.5 volt
minimum ARINC data threshold and just above the standard 2.5 volt maximum ARINC null threshold.
The TESTA and TESTB inputs bypass the analog inputs for
testing purposes. Also if TESTA and TESTB are both taken
high, the digital outputs are forced to zero.
See Holt Application Note AN-300 for more information on
lightning protection.
FEATURES
!
!
!
!
!
!
VCC - 1
TESTA - 2
7 - ROUTB
RINB - 3
6 - ROUTA
RINA - 4
5 - GND
HI-8588PSI-10, HI-8588PST-10 & HI-8588PSM-10
8 - PIN PLASTIC NARROW BODY SOIC
SUPPLY VOLTAGES
vcc = 5.0V ± 5%
FUNCTION TABLE
RECEIVER
RINA
RINB
TESTA
TESTB
-1.25V to 1.25V
-1.25V to 1.25V
0
0
0
0
-3.25V to -6.5V
3.25V to 6.5V
0
0
0
1
3.25V to 6.5V
-3.25V to -6.5V
0
0
1
0
X
X
0
1
0
1
X
X
1
0
1
0
X
X
1
1
0
0
ARINC 429 line receiver interface in a
small outline package
Lightning protection simplified with the
ability to add 10 Kohm external series
resistors
8 - TESTB
ROUTA ROUTB
PIN DESCRIPTION TABLE
Receiver input hystersis at least 2 volts
PIN
Test inputs bypass analog inputs and
force digital outputs to an one, zero or
null state
Plastic and ceramic package options surface mount and DIP
SYMBOL
FUNCTION
DESCRIPTION
1
VCC
SUPPLY
5 VOLT SUPPLY
2
TESTA
LOGIC INPUT
CMOS
3
RINB
ARINC INPUT
RECEIVER B INPUT
4
RINA
ARINC INPUT
RECEIVER A INPUT
5
GND
POWER
GROUND
6
ROUTA
LOGIC OUTPUT
RECEIVER CMOS OUTPUT A
7
ROUTB
LOGIC OUTPUT
RECEIVER CMOS OUTPUT B
8
TESTB
LOGIC INPUT
CMOS
Mil processing available
(DS8588-10, Rev. C)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/06
HI-8588-10
FUNCTIONAL DESCRIPTION
RECEIVER
between VCC and Ground. The nominal settings correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V.
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each require 35KW of resistance of which 25KW is internal to the chip. The series resistance is connected to level translators whose resistance
to Ground is typically 10KW. In order for the voltage translation not to be adversely affected, an external 10KW series
resister must be added to each ARINC input. The
HI-8588-10 device is typically chosen for applications
where external series resistors are required in its lightning
protection circuitry.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. Unlike the HI-8588, if TESTA and TESTB
are both One, the HI-8588-10 outputs are pulled low instead of being tri-stated. This allows the digital outputs
of a transmitter to be connected to the test inputs through
control logic for self-test purposes.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differential signal is compared to levels derived from a divider
TEST
ONE
S
Q
ROUTA
LATCH
TESTA
R
TESTB
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
NULL
TEST
ZERO
S
Q
ROUTB
LATCH
TESTA
R
TESTB
NULL
FIGURE 1 - RECEIVER BLOCK DIAGRAM
5V
1
HARDWIRE
OR
DRIVE FROM LOGIC
2
{
8
10KW
APPLICATION INFORMATION
4
TESTA
ROUTA
TESTB
ROUTB
6
7
3
10KW
RXD1
RXD0
HI-8588-10
RINA
ARINC
Channel
Figure 2 shows a possible application of the
HI-8588-10 interfacing an ARINC receive
channel to the HI-6010 which in turn interfaces to an 8-bit bus.
VCC
HI-6010
RINB GND
5
15V
1
6
ARINC
Channel
7
SLP1.5
V+
TXAOUT
TX1IN
HI-8586
TX0IN
TXBOUT
GND
4
V-
5
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
8 BIT BUS
8
3
2
TXD1
TXD0
HI-8588-10
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Voltages referenced to Ground
Supply voltages
VCC...................................................7V
Supply Voltages
VCC........................................5V ± 5%
ARINC input - pins 3 & 4
Voltage at either pin......+29V to -29V
Temperature Range
Industrial Screening........-40°C to +85°C
Hi-Temp Screening.......-55°C to +125°C
Military Screening.........-55°C to +125°C
DC current per input pin................ ±10mA
Power dissipation at 25°C
plastic DIP............0.7W
ceramic DIP..........0.5W
NOTE: Stresses above absolute maximum
ratings or outside recommended operating conditions may cause permanent damage to the
device. These are stress ratings only. Operation at the limits is not recommended.
Solder Temperature ........275°C for 10 sec
Storage Temperature........-65°C to +150°C
DC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 5.0V UNLESS OTHERWISE STATED
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
diff. volt. thru 10KW, pins 3 & 4
6.5
-
10
-
13
2.5
5.0
volts
volts
volts
3.5
-
-
1.5
volts
volts
30
19
75
40
-
Kohm
Kohm
-
-
0.1
0.1
mA
mA
3.6
-1.6
5.6
-0.8
-
mA
mA
-
2.3
6.3
mA
ARINC input voltage
one or zero
null
common mode
V DIN
V NIN
VCOM
logic input voltage
high
low
V IH
V IL
ARINC input resistance
RINA to RINB
RINA or RINB to Gnd or VCC
R DIFF
R SUP
supplies floating & series 10KW
logic input current
source
sink
I IH
I IL
V IN = 0 V
V IN = 5 V
logic output drive current
one
zero
I OH
I OL
V = 4.6V
OH
VOL = 0.4V
I CC1
pins 2, 8 = 0V; pins 3, 4 open
Current drain
operating
"
"
"
with respect to Ground
"
"
HOLT INTEGRATED CIRCUITS
3
"
HI-8588-10
AC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE, VCC = 5.0V UNLESS OTHERWISE STATED
PARAMETERS
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNITS
Receiver propagation delay
Output high to low
Output low to high
t phlr
t plhr
-
600
600
-
ns
ns
Receiver output transition times
Output high to low
Output low to high
t fr
t rr
-
50
50
80
80
ns
ns
Input capacitance (1)
ARINC differential
ARINC single ended to Ground
Logic
CAD
CAS
C IN
-
5
-
10
10
10
pF
pF
pF
defined in Figure 3, C L= 50pF
Notes: 1. Guaranteed but not tested
10V
VDIFF
pin 4 - pin 3
0V
-10V
t plhr
t rr
t phlr
5V
0V
90%
pin 6
10%
t plhr
t phlr
t fr
5V
0V
pin 7
FIGURE 3 - RECEIVER TIMING
ORDERING INFORMATION
HI - 8588 xx x x - 10
PART
NUMBER
Blank
F
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
NO
T
-55°C TO +125°C
T
NO
M
-55°C TO +125°C
M
YES
PART
NUMBER
PD
PS
CR
PACKAGE
DESCRIPTION
8 PIN PLASTIC DIP (not available with “M” flow)
8 PIN PLASTIC NARROW BODY SOIC
8 PIN CERDIP (not available Pb-free)
HOLT INTEGRATED CIRCUITS
4
HI-8588-10 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN PLASTIC DIP
Package Type: 8P
.385 ±.015
(4.699 ±.381)
.250 ± .010
(6.350 ±.254)
.100 ±.010
(3.540 ±.254)
.300 ±.010
(7.620 ±.254)
7° TYP.
.025 ±.010
(.635 ± .254)
.135 ±.015
(3.429 ±.381)
.1375 ±.0125
(3.493 ±.318)
.0115 ±.0035
(.292 ±.089)
.055 ±.010
(1.397 ±.254)
.019 ±.002
(.483 ±.102)
.335 ±.035
(8.509 ±.889)
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB
(Narrow Body)
Package Type: 8HN
.1935 ± .0035
(4.915 ± .085)
.0086 ± .0012
(.2184 ± .0305)
.236 ± .008
(5.994 ± .203)
PIN 1
.1535 ± .0035
(3.90 ± .09)
.0165 ± .0035
(.4191 ± .0889)
Detail A
.055 ± .005
(1.397 ± .127)
0° to 8°
.050 ± .010
(1.27 ± .254)
.033 ± .017
(.8382 ± .4318)
Detail A
HOLT INTEGRATED CIRCUITS
5
.0069 ± .0029
(.1753 ± .0737)
HI-8588-10 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN CERDIP
Package Type: 8D
.380 ±.004
(9.652 ±.102)
.005 MIN.
(.127 MIN.)
.248 ±.003
(6.299 ±.076)
.039 ±.006
(.991 ±.154)
.100 ±.008
(2.540 ±.203)
.015 MIN.
(.381 MIN.)
.200 MAX.
(5.080 MAX.)
.314 ±.003
(7.976 ±.076)
Base Plane
.010 ±.006
(.254 ±.152`)
Seating Plane
.163 ±.037
(4.140 ±.940)
.056 ±.006
(1.422 ±.152)
.018 ±.006
(.457 ±.152)
HOLT INTEGRATED CIRCUITS
6
.350 ±.030
(8.890 ±.762)