Sony CXG1030N Power amplifier for ph Datasheet

CXG1030N
Power Amplifier for PHS
Description
The CXG1030N is a power amplifier for PHS. This
IC is designed using the Sony’s GaAs J-FET process
and operates at a single power supply.
Features
• Output power
21 dBm
• Positive power supply
3.0 V
• Low current consumption
170 mA
• High power gain
39 dB Typ.
• Small mold package 16-pin SSOP
16 pin SSOP (Plastic)
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VDD
6
V
• Voltage between gate and source
Vgs0
1.5
V
• Drain current
IDD
500
mA
• Power dissipation
PD
3
W
• Channel temperature
Tch
175
°C
• Operating temperature Top
–35 to +85
°C
• Storage temperature
Tstg –65 to +150 °C
Structure
GaAs J-FET MMIC
Electrical Characteristics
VDD=3.0 V, VCTL=2.0 V, f=1.90 GHz
Item
∗1 Current consumption
∗1 Gate voltage adjustment value
Output power
∗2 Power gain
∗2 Adjacent channel leak power ratio
(600 kHz ±100 kHz)
(Ta=25 °C)
Symbol
IDD
VGG2
POUT
GP
Min.
0
21
36
ACPR600
Typ.
170
0.4
Max.
0.8
Unit
mA
V
dBm
dB
–54
dBc
39
–59
∗1 Values where VGG1 and VGG2 are adjusted so that IDD becomes 170 mA when 21.0 dBm is output.
∗2 When 21.0 dBm is output.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E96706-TE
CXG1030N
Block Diagram
Pin Configuration
VDD1
VDD2
1
VDD3
RFIN
RFOUT
VGG1
VCTL VGG2
16
GND
GND
RFIN
VGG1
GND
VCTL
VDD1
GND
GND
VGG2
VDD2
GND
GND
RFOUT
VDD3
GND
Gate Bias Circuit
VGG2
Gate adjustment pin
1kΩ
VGG1
Recommended Current Adjustment Method
(1) VGG2/PIN separate adjustment
(VGG2 adjustment 1)
(PIN adjustment 1)
(VGG2 adjustment 2)
(PIN adjustment 2)
When the RF input
(PIN) is off, the current
consumption (IDD) is
adjusted to 170 mA.
The output power
(POUT) is adjusted
to 21.0 dBm.
The current
consumption (IDD)
is finely adjusted to
170 mA.
The output power
(POUT) is finely
adjusted to 21.0 dBm.
Variation of IDD and
POUT due to adjustment
IDD=170±20 mA
POUT=21.0 dBm
IDD=170 mA
POUT=21.0±0.2 dBm
IDD=170±5 mA
POUT=21.0 dBm
(2) Simple adjustment
(IDD read)
(VGG2 setting)
(PIN adjustment)
When the RF input (PIN)
is off, the gate voltage
(VGG2) is set to 0.4 V
and IDD is read.
The formula∗1 where
VGG2=f (IDD: VGG2=0.4 V)
is used to set VGG2.
The output power (POUT)
is adjusted to 21.0 dBm.
Variation of IDD and POUT
due to adjustment
∗1 e.g. VGG2=a-b × IDD
—2—
IDD=170±5 mA
POUT=21.0 dBm
CXG1030N
Recommended Evaluation Circuit
VGG2
VCTL
3.0V
C2
C2
GND
100Ω
Variable
resistor RV
10kΩ (Max.)
1kΩ
L4
L1
RFIN
C2
C1
C2
C1
RFOUT
C1
L5
C4
L2
C2
6.8kΩ
1kΩ
180Ω
L3
C3
Via Hole
GND
Glass fabric-base epoxy board
GND for the overall back side
Dimension : 5cm × 5cm
Thickness : 0.2mm
C2
VDD
C1=100pF
L1=18nH
Recommended Gate Bias Circuit and
Circuit Characteristics
C2=1nF
L2=10nH
C3=10nF
L3=1.8nH
C4=1pF
L4=3.9nH
L5=2.7nH
(V)
VGG2
3.0V
100Ω
6.8kΩ
RV1
RV2
VGG2
1kΩ
0.5
Variable
resistor RV
10kΩ (Max.)
180Ω
0
5
10
RV1 (V)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—3—
CXG1030N
Example of Representative Characteristics (Ta=25 °C)
POUT, ACPR vs. PIN
25
–40
20
–45
POUT
15
–50
ACPR
10
–55
5
–60
0
–65
–5
–45
ACPR-Adjacent channel leak
power ratio (dBc) (600kHz offset)
POUT-Output power (dBm)
VDD=3.0V, VCTL=2.0V, VGG=const.,
IDD=170mA (@POUT=21.0dBm)
–70
–40
–35
–30
–25
–20
–15
–10
–5
–54
41
–55
–56
40
Gp-Power gain (dB)
–57
–58
39
–59
38
Gain
ACPR
–60
–61
–62
37
–63
–64
36
–65
–66
35
110 120 130 140 150 160 170 180 190 200 210 220 230
IDD-Current consumption (mA)
VDD=3.0V, VCTL=2.0V, PIN=–18.0dBm,
VGG=const., IDD=170mA (@POUT=21.0dBm)
23
–54
–55
–56
–57
–58
–59
–60
–61
–62
–63
–64
–65
–66
–67
–68
–69
–70
22
POUT
ACPR
21
20
19
2.0
2.5
3.0
3.5
4.0
4.5
VDD-Drain voltage (V)
—4—
5.0
5.5
ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset)
VDD=3.0V, VCTL=2.0V, POUT=21.0dBm,
VGG=var.
POUT, ACPR vs. VDD
POUT-Output power (dBm)
Gp, ACPR vs. IDD
ACPR-Adjacent channel leak power ratio (dBc) (600kHz offset)
PIN-Input power (dBm)
CXG1030N
Unit : mm
16PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
∗5.0 ± 0.1
0.1
16
9
A
1
+ 0.1
0.22 – 0.05
6.4 ± 0.2
∗4.4 ± 0.1
8
+ 0.05
0.15 – 0.02
0.65 ± 0.12
0.1 ± 0.1
0.5 ± 0.2
Package Outline
0° to 10°
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
: PALLADIUM PLATING
This product uses PdPPF
PACKAGE
(Palladium Pre-Plated Lead Frame).
STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SSOP-16P-L01
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
EIAJ CODE
SSOP016-P-0044
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
0.1g
JEDEC CODE
—5—
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