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LM3478, LM3478Q-Q1
SNVS085W – JULY 2000 – REVISED DECEMBER 2014
LM3478x/-Q1 High-Efficiency Low-Side N-Channel Controller for Switching Regulator
1 Features
3 Description
•
The LM3478 is a versatile Low-Side N-Channel
MOSFET controller for switching regulators. It is
suitable for use in topologies requiring a low side
MOSFET, such as boost, flyback, SEPIC, etc.
Moreover, the LM3478 can be operated at extremely
high switching frequency in order to reduce the
overall solution size. The switching frequency of the
LM3478 can be adjusted to any value between 100
kHz and 1 MHz by using a single external resistor.
Current mode control provides superior bandwidth
and transient response, besides cycle-by-cycle
current limiting. Output current can be programmed
with a single external resistor.
1
•
•
•
•
•
•
•
LM3478Q-Q1 in VSSOP-8 package is AEC-Q100
Qualified and Manufactured on an Automotive
Grade Flow
8-lead VSSOP-8 and SOIC-8 packages
Internal Push-Pull Driver With 1-A Peak Current
Capability
Current Limit and Thermal Shutdown
Frequency Compensation Optimized With a
Capacitor and a Resistor
Internal Soft Start
Current Mode Operation
Undervoltage Lockout With Hysteresis
2 Applications
•
•
•
•
•
•
•
•
•
Distributed Power Systems
Battery Chargers
Offline Power Supplies
Telecom Power Supplies
Automotive Power Systems
Wide Supply Voltage Range of 2.97 V to 40 V
100-kHz to 1-MHz Adjustable Clock Frequency
±2.5% (Over Temperature) Internal Reference
10-µA Shutdown Current (Over Temperature)
The LM3478 has built in features such as thermal
shutdown, short-circuit protection, over voltage
protection, etc. Power saving shutdown mode
reduces the total supply current to 5 µA and allows
power supply sequencing. Internal soft-start limits the
inrush current at start-up.
Device Information(1)
PART NUMBER
LM3478
LM3478Q-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm x 3.91 mm
VSSOP (8)
3.00 mm x 3.00 mm
VSSOP (8)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical High Efficiency Step-Up (Boost) Converter
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3478, LM3478Q-Q1
SNVS085W – JULY 2000 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings - LM3478 ............................................
ESD Ratings - LM3478Q-Q1 ...................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
Documentation Support .......................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision V (February 2013) to Revision W
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 4
•
Deleted Thermal Resistance parameter from Electrical Characteristics ............................................................................... 6
Changes from Revision U (February 2013) to Revision V
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 1
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SNVS085W – JULY 2000 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
8-Lead VSSOP-8 Package
3 Pins
Top View
8-Lead SOIC-8
3 Pins
Top View
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
ISEN
1
I
Current sense input pin. Voltage generated across an external sense resistor is fed into this pin.
COMP
2
I
Compensation pin. A resistor, capacitor combination connected to this pin provides compensation for the
control loop.
FB
3
I
Feedback pin. The output voltage should be adjusted using a resistor divider to provide 1.26 V at this pin.
AGND
4
G
Analog ground pin.
PGND
5
G
Power ground pin.
DR
6
O
Drive pin. The gate of the external MOSFET should be connected to this pin.
FA/SD
7
I
Frequency adjust and Shutdown pin. A resistor connected to this pin sets the oscillator frequency. A high
level on this pin for longer than 30 µs will turn the device off. The device will then draw less than 10µA from
the supply.
VIN
8
P
Power Supply Input pin.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1)
MIN
MAX
UNIT
45
V
–0.4< V
V FB < 7
V
–0.4 < VFA/SD
VFA/SD< 7
V
1
A
+150
°C
Vapor Phase (60 s)
215
°C
Infrared (15 s)
260
°C
Input Voltage
FB Pin Voltage
FA/SD Pin Voltage
Peak Driver Output Current
(<10µs)
Power Dissipation
Internally Limited
Junction Temperature
Lead Temperature
–0.4 ≤ VDR
DR Pin Voltage
VDR ≤ 8
V
500
mV
150
°C
ISEN Pin Voltage
Tstg
(1)
−65
Storage temperature
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings - LM3478
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
UNIT
±2000
±750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings - LM3478Q-Q1
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±2000
Other pins
±750
Corner pins (1, 4, 5, and 8)
±750
Charged device model (CDM), per
AEC Q100-011
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply Voltage
Junction Temperature Range
Switching Frequency
4
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NOM
MAX
UNIT
2.97 ≤ VIN
VIN ≤ 40
V
−40 ≤ TJ
TJ ≤ +125
°C
100 ≤ FSW
FSW ≤ 1
MHz
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6.5 Thermal Information
LM3478
THERMAL METRIC (1)
LM3478-Q1
D
DCK
DCK
3 PINS
3 PINS
3 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
157.2
157.2
157.2
RθJC(top)
Junction-to-case (top) thermal resistance
49.9
49.9
49.9
RθJB
Junction-to-board thermal resistance
77.1
77.1
77.1
ψJT
Junction-to-top characterization parameter
4.7
4.7
4.7
ψJB
Junction-to-board characterization parameter
75.8
75.8
75.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.6 Electrical Characteristics
Unless otherwise specified, VIN = 12V, RFA = 40kΩ, TJ = 25°C
PARAMETER
TEST CONDITIONS
VCOMP = 1.4V, 2.97 ≤ VIN ≤ 40V
VFB
Feedback Voltage
ΔVLINE
Feedback Voltage Line
Regulation
2.97 ≤ VIN ≤ 40V
ΔVLOAD
Output Voltage Load
Regulation
IEAO Source/Sink
VUVLO
Input Undervoltage
Lock-out
−40°C ≤ TJ ≤ 125°C
VUV(HYS)
Input Undervoltage
Lock-out Hysteresis
VCOMP = 1.4V, 2.97 ≤ VIN ≤ 40V, −40°C
≤ TJ ≤ 125°C
MIN
TYP
MAX
1.2416
1.26
1.2843
1.228
1.292
0.001
2.85
2.97
170
−40°C ≤ TJ ≤ 125°C
130
RFA = 40KΩ
210
400
Nominal Switching
Frequency
RDS1 (ON)
Driver Switch On
Resistance (top)
IDR = 0.2A, VIN= 5V
16
RDS2 (ON)
Driver Switch On
Resistance (bottom)
IDR = 0.2A
4.5
VDR (max)
Maximum Drive Voltage
Swing (1)
VIN < 7.2V
VIN
VIN ≥ 7.2V
7.2
Dmax
Maximum Duty Cycle (2)
Tmin (on)
Minimum On Time
ISUPPLY
Supply Current (nonswitching)
IQ
Quiescent Current in
Shutdown Mode
VSENSE
Current Sense
Threshold Voltage
VIN = 5V
135
VIN = 5V, −40°C ≤ TJ ≤ 125°C
125
VSC
Short-Circuit Current
Limit Sense Voltage
VIN = 5V
(2)
(3)
(4)
RFA = 40KΩ, −40°C ≤ TJ ≤ 125°C
350
V
%/V
±0.5
Fnom
(1)
UNIT
440
%/A
V
mV
kHz
Ω
V
100%
325
−40°C ≤ TJ ≤ 125°C
See
(3)
See
(3)
210
600
2.7
, −40°C ≤ TJ ≤ 125°C
VFA/SD = 5V
(4)
VFA/SD = 5V
125°C
(4)
3.3
, VIN = 5V
mA
5
, VIN = 5V, −40°C ≤ TJ ≤
VIN = 5V, −40°C ≤ TJ ≤ 125°C
ns
10
156
180
190
343
250
415
µA
mV
mV
The voltage on the drive pin, VDR is equal to the input voltage when input voltage is less than 7.2 V. VDR is equal to 7.2 V when the
input voltage is greater than or equal to 7.2 V.
The limits for the maximum duty cycle can not be specified since the part does not permit less than 100% maximum duty cycle
operation.
For this test, the FA/SD pin is pulled to ground using a 40-K resistor.
For this test, the FA/SD pin is pulled to 5 V using a 40-K resistor.
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Electrical Characteristics (continued)
Unless otherwise specified, VIN = 12V, RFA = 40kΩ, TJ = 25°C
PARAMETER
VSL
Internal Compensation
Ramp Voltage
VSL ratio
VSL/VSENSE
Output Over-voltage
Protection (with respect
to feedback voltage) (5)
VOVP
TEST CONDITIONS
MIN
VIN = 5V, −40°C ≤ TJ ≤ 125°C
52
VIN = 5V
TYP
92
132
0.30
0.49
VCOMP = 1.4V
32
50
VCOMP = 1.4V, −40°C ≤ TJ ≤ 125°C
25
78
VSSOP Package, −40°C ≤ TJ ≤ 125°C
85
Error Amplifier
Transconductance
Gm
AVOL
Error Amplifier Voltage
Gain
Error Amplifier Output
Current (Source/ Sink)
IEAO
60
VCOMP = 1.4V, −40°C ≤ TJ ≤ 125°C
20
VCOMP = 1.4V, IEAO = 100µA
(Source/Sink)
600
VCOMP = 1.4V, IEAO = 100µA
(Source/Sink), −40°C ≤ TJ ≤ 125°C
365
Error Amplifier Output
Voltage Swing
110
800
mV
1000
µS
VCOMP = 1.4V, IEAO = 100µA
(Source/Sink)
1265
38
V/V
VCOMP = 1.4V, IEAO = 100µA
(Source/Sink), −40°C ≤ TJ ≤ 125°C
26
Source, VCOMP = 1.4V, VFB = 0V
80
Source, VCOMP = 1.4V, VFB = 0V, −40°C
≤ TJ ≤ 125°C
50
−100
Sink, VCOMP = 1.4V, VFB = 1.4V, −40°C
≤ TJ ≤ 125°C
VEAO
mV
100
VCOMP = 1.4V
Sink, VCOMP = 1.4V, VFB = 1.4V
mV
78
SOIC Package, −40°C ≤ TJ ≤ 125°C
Output Over-Voltage
Protection Hysteresis (5)
UNIT
0.70
VSSOP Package
SOIC Package
VOVP(HYS)
MAX
44
110
180
−140
−85
Upper Limit, VFB = 0V, COMP Pin =
Floating
140
µA
−180
−185
µA
2.2
V
Upper Limit, VFB = 0V, COMP Pin =
Floating, −40°C ≤ TJ ≤ 125°C
1.8
Lower Limit, VFB = 1.4V
2.4
0.56
Lower Limit, VFB = 1.4V, −40°C ≤ TJ ≤
125°C
0.2
1.0
V
TSS
Internal Soft-Start Delay
VFB = 1.2V, VCOMP = Floating
4
ms
Tr
Drive Pin Rise Time
Cgs = 3000pf, VDR = 0 to 3V
25
ns
Tf
Drive Pin Fall Time
Cgs = 3000pf, VDR = 0 to 3V
25
ns
Shutdown threshold
(6)
Output = High
1.27
Output = High, −40°C ≤ TJ ≤ 125°C
VSD
1.4
Output = Low
0.65
Output = Low, −40°C ≤ TJ ≤ 125°C
ISD
Shutdown Pin Current
IFB
Feedback Pin Current
TSD
Tsh
(5)
(6)
6
0.3
VSD = 5V
−1
VSD = 0V
+1
V
V
µA
15
nA
Thermal Shutdown
165
°C
Thermal Shutdown
Hysteresis
10
°C
The over-voltage protection is specified with respect to the feedback voltage. This is because the over-voltage protection tracks the
feedback voltage. The overvoltage protection threshold is given by adding the feedback voltage, VFB to the over-voltage protection
specification.
The FA/SD pin should be pulled to VIN through a resistor to turn the regulator off. The voltage on the FA/SD pin must be above the
maximum limit for Output = High to keep the regulator off and must be below the limit for Output = Low to keep the regulator on.
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6.7 Typical Characteristics
Unless otherwise specified, VIN = 12V, TJ = 25°C.
Figure 1. IQ vs Input Voltage (Shutdown)
Figure 2. ISupply vs Input Voltage (Non-Switching)
Figure 3. ISupply vs VIN (Switching)
Figure 4. Switching Frequency vs RFA
Figure 5. Frequency vs Temperature
Figure 6. Drive Voltage vs Input Voltage
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12V, TJ = 25°C.
8
Figure 7. Current Sense Threshold vs Input Voltage
Figure 8. COMP Pin Voltage vs Load Current
Figure 9. Efficiency vs Load Current (3.3-V Input and 12-V
Output)
Figure 10. Efficiency vs Load Current (5-V Input and 12-V
Output)
Figure 11. Efficiency vs Load Current (9-V Input and 12-V
Output)
Figure 12. Efficiency vs Load Current (3.3-V Input and 5-V
Output)
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12V, TJ = 25°C.
Figure 13. Error Amplifier Gain
Figure 14. Error Amplifier Phase
Figure 15. COMP Pin Source Current vs Temperature
Figure 16. Short Circuit Sense Voltage vs Input Voltage
Figure 17. Compensation Ramp vs Compensation Resistor
Figure 18. Shutdown Threshold Hysteresis vs Temperature
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12V, TJ = 25°C.
Figure 19. Duty Cycle vs Current Sense Voltage
10
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7 Detailed Description
7.1 Overview
The LM3478 device uses a fixed frequency, Pulse Width Modulated (PWM) current mode control architecture.
The Functional Block Diagram shows the basic functionality. In a typical application circuit, the peak current
through the external MOSFET is sensed through an external sense resistor. The voltage across this resistor is
fed into the ISEN pin. This voltage is fed into the positive input of the PWM comparator. The output voltage is also
sensed through an external feedback resistor divider network and fed into the error amplifier negative input
(feedback pin, FB). The output of the error amplifier (COMP pin) is added to the slope compensation ramp and
fed into the negative input of the PWM comparator. At the start of any switching cycle, the oscillator sets the RS
latch using the switch logic block. This forces a high signal on the DR pin (gate of the external MOSFET) and the
external MOSFET turns on. When the voltage on the positive input of the PWM comparator exceeds the negative
input, the RS latch is reset and the external MOSFET turns off.
The voltage sensed across the sense resistor generally contains spurious noise spikes, as shown in Figure 20.
These spikes can force the PWM comparator to reset the RS latch prematurely. To prevent these spikes from
resetting the latch, a blank-out circuit inside the IC prevents the PWM comparator from resetting the latch for a
short duration after the latch is set. This duration is about 325 ns and is called the blanking interval and is
specified as minimum on-time in the Electrical Characteristics section. Under extremely light-load or no-load
conditions, the energy delivered to the output capacitor when the external MOSFET in on during the blanking
interval is more than what is delivered to the load. An over-voltage comparator inside the LM3478 prevents the
output voltage from rising under these conditions. The over-voltage comparator senses the feedback (FB pin)
voltage and resets the RS latch. The latch remains in reset state until the output decays to the nominal value.
Blank-Out prevents false
reset
PWM Comparator resets
the RS latch
92 mV
typ
+
PWM
Comparator
Oscillator Sets
the RS Latch
325 ns Blank-Out time
Figure 20. Basic Operation of the PWM Comparator
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7.2 Functional Block Diagram
VIN
FA/SD
Fixed Frequency
Detect
Oscillator
Softstart
internal slope
compensation
Under Voltage
Lockout
LDO
1.26V Reference
COMP
7.2V
internal Vcc
Gm
Error
Amplifier
PWM
DR
FB
Q
S
DRIVER
logic
Isen
Vfb+Vovp
OVP
325mV
AGND
slope compensation
ramp adjust current
source
R
Short Circuit
Comparator
THERMAL
LIMIT
(165°C)
PGND
7.3 Feature Description
7.3.1 Overvoltage Protection
The LM3478 has over voltage protection (OVP) for the output voltage. OVP is sensed at the feedback pin (pin 3).
If at anytime the voltage at the feedback pin rises to VFB+ VOVP, OVP is triggered. See Electrical Characteristics
section for limits on VFB and VOVP.
OVP will cause the drive pin to go low, forcing the power MOSFET off. With the MOSFET off, the output voltage
will drop. The LM3478 will begin switching again when the feedback voltage reaches VFB + (VOVP - VOVP(HYS)).
See Electrical Characteristics for limits on VOVP(HYS).
OVP can be triggered if the unregulated input voltage crosses 7.2 V, the output voltage will react as shown in
Figure 21. The internal bias of the LM3478 comes from either the internal LDO as shown in the block diagram or
the voltage at the Vin pin is used directly. At Vin voltages lower than 7.2 V the internal IC bias is the Vin voltage
and at voltages above 7.2V the internal LDO of the LM3478 provides the bias. At the switch over threshold at 7.2
V a sudden small change in bias voltage is seen by all the internal blocks of the LM3478. The control voltage
shifts because of the bias change, the PWM comparator tries to keep regulation. To the PWM comparator, the
scenario is identical to a step change in the load current, so the response at the output voltage is the same as
would be observed in a step load change. Hence, the output voltage overshoot here can also trigger OVP. The
LM3478 will regulate in hysteretic mode for several cycles, or may not recover and simply stay in hysteretic
mode until the load current drops or Vin is not crossing the 7.2 V threshold anymore. Note that the output is still
regulated in hysteretic mode.
12
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Feature Description (continued)
Depending on the requirements of the application, there is some influence one has over this effect. The threshold
of 7.2 V can be shifted to higher voltages by adding a resistor in series with VIN. In case VIN is right at the
threshold of 7.2 V, the threshold could cross over and over due to some slight ripple on VIN. To minimize the
effect on the output voltage one can filter the VIN pin with an RC filter.
VIN (V)
7.2V
t
VFB (V)
OVP
(1.31V)
1.26V
t
Figure 21. The Feedback Voltage Experiences an Oscillation if the Input Voltage crosses the 7.2-V
Internal Bias Threshold
7.3.2 Slope Compensation Ramp
The LM3478 uses a current mode control scheme. The main advantages of current mode control are inherent
cycle-by-cycle current limit for the switch and simpler control loop characteristics. It is also easy to parallel power
stages using current mode control since current sharing is automatic. However, current mode control has an
inherent instability for duty cycles greater than 50%, as shown in Figure 22.
A small increase in the load current causes the switch current to increase by ΔI0. The effect of this load change
is ΔI1.
The two solid waveforms shown are the waveforms compared at the internal pulse width modulator, used to
generate the MOSFET drive signal. The top waveform with the slope Se is the internally generated control
waveform VC. The bottom waveform with slopes Sn and Sf is the sensed inductor current waveform VSEN.
Voltage
VC
PWM Comparator
Waveforms
Se
'I0
VSEN
'I2
Sn
Sf
'I1
Time
Figure 22. Sub-Harmonic Oscillation for D>0.5 and Compensation Ramp to Avoid Sub-Harmonic
Oscillation
Sub-harmonic Oscillation can be easily understood as a geometric problem. If the control signal does not have
slope, the slope representing the inductor current ramps up until the control signal is reached and then slopes
down again. If the duty cycle is above 50%, any perturbation will not converge but diverge from cycle to cycle
and causes sub-harmonic oscillation.
It is apparent that the difference in the inductor current from one cycle to the next is a function of Sn, Sf and Se as
shown in Equation 1.
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Feature Description (continued)
'In =
Sf - Se
'I
Sn + Se n-1
(1)
Hence, if the quantity (Sf - Se)/(Sn + Se) is greater than 1, the inductor current diverges and sub-harmonic
oscillation results. This counts for all current mode topologies. The LM3478 has some internal slope
compensation VSL which is enough for many applications above 50% duty cycle to avoid sub-harmonic
oscillation .
For boost applications, the slopes Se, Sf and Sn can be calculated with Equation 2, Equation 3, and Equation 4.
Se = VSL x fs
(2)
Sf = Rsen x (VOUT - VIN)/L
(3)
Sn = VIN x Rsen/L
(4)
When Se increases, then the factor that determines if sub-harmonic oscillation will occur decreases. When the
duty cycle is greater than 50%, and the inductance becomes less, the factor increases.
For more flexibility, slope compensation can be increased by adding one external resistor, RSL, in the ISEN's path.
Figure 23 shows the setup. The externally generated slope compensation is then added to the internal slope
compensation of the LM3478. When using external slope compensation, the formula for Se becomes:
Se = (VSL + (K x RSL)) x fs
(5)
A typical value for factor K is 40 µA.
The factor changes with switching frequency. Figure 24 is used to determine the factor K for individual
applications and Equation 6 gives the factor K.
K = ΔVSL / RSL
(6)
It is a good design practice to only add as much slope compensation as needed to avoid sub-harmonic
oscillation. Additional slope compensation minimizes the influence of the sensed current in the control loop. With
very large slope compensation the control loop characteristics are similar to a voltage mode regulator which
compares the error voltage to a saw tooth waveform rather than the inductor current.
DR
Q
LM3478
ISEN
RSL
RSEN
Figure 23. Adding External Slope Compensation
14
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Figure 24. External Slope Compensation
ΔVSL vs RSL
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Feature Description (continued)
7.3.3 Frequency Adjust/Shutdown
The switching frequency of the LM3478 can be adjusted between 100 kHz and 1 MHz using a single external
resistor. This resistor must be connected between FA/SD pin and ground, as shown in Figure 25. To determine
the value of the resistor required for a desired switching frequency, refer to Typical Characteristics or use
Equation 7:
RFA = 4.503 x 1011 x fS- 1.26
(7)
Figure 25. Frequency Adjust
The FA/SD pin also functions as a shutdown pin. If a high signal (>1.35 V) appears on the FA/SD pin, the
LM3478 stops switching and goes into a low current mode. The total supply current of the IC reduces to less
than 10 µA under these conditions. Figure 26 shows implementation of the shutdown function when operating in
frequency adjust mode. In this mode a high signal for more than 30 us shuts down the IC. However, the voltage
on the FA/SD pin should be always less than the absolute maximum of 7 V to avoid any damage to the device.
Figure 26. Shutdown Operation in Frequency Adjust Mode
7.3.4 Short-Circuit Protection
When the voltage across the sense resistor measured on the ISEN pin exceeds 343 mV, short circuit current limit
protection gets activated. A comparator inside the LM3478 reduces the switching frequency by a factor of 5 and
maintains this condition until the short is removed. In normal operation the sensed current will trigger the power
MOSFET to turn off. During the blanking interval the PWM comparator will not react to an over current so that
this additional 343 mV current limit threshold is implemented to protect the device in a short circuit or severe
overload condition.
7.4 Device Functional Modes
The device is set to run as soon as the input voltage crosses above the UVLO set point and at a frequency set
according to the FA/SD pin pulldown resistor. If the FA/SD pin is pulled high, the LM3481 enters shut-down
mode.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM3478 may be operated in either the continuous conduction mode (CCM) or the discontinuous current
conduction mode (DCM). The following applications are designed for the CCM operation. This mode of operation
has higher efficiency and usually lower EMI characteristics than the DCM.
8.2 Typical Applications
8.2.1 Typical High Efficiency Step-Up (Boost) Converter
Figure 27. Typical High Efficiency Step-Up (Boost) Converter Schematic
The boost converter converts a low input voltage into a higher output voltage. The basic configuration for a boost
converter is shown in Figure 28. In the CCM (when the inductor current never reaches zero at steady state), the
boost regulator operates in two states. In the first state of operation, MOSFET Q is turned on and energy is
stored in the inductor. During this state, diode D is reverse biased and load current is supplied by the output
capacitor, COUT.
In the second state, MOSFET Q is off and the diode is forward biased. The energy stored in the inductor is
transferred to the load and the output capacitor. The ratio of the switch on time to the total period is the duty
cycle D as shown in Equation 8.
D = 1 - (Vin / Vout)
(8)
Including the voltage drop across the MOSFET and the diode the definition for the duty cycle is shown in
Equation 9.
D = 1 - ((Vin - Vq)/(Vout + Vd))
(9)
Vd is the forward voltage drop of the diode and Vq is the voltage drop across the MOSFET when it is on.
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Typical Applications (continued)
A.
First Cycle Operation
B.
Second Cycle of Operation
Figure 28. Simplified Boost Converter
8.2.1.1 Design Requirements
To properly size the components for the application, the designer needs the following parameters: input voltage
range, output voltage, output current range, and required switching frequency. These four main parameters affect
the choices of component available to achieve a proper system behavior.
For the power supply, the input impedance of the supply rail should be low enough that the input current
transient does not drop below the UVLO value. The factors determining the choice of inductor used should be
the average inductor current, and the inductor current ripple. If the switching frequency is set high, the converter
can be operated with very small inductor values. The maximum current that can be delivered to the load is set by
the sense resistor, RSEN. Current limit occurs when the voltage generated across the sense resistor equals the
current sense threshold voltage, VSENSE. Also, a resistor RSL adds additional slope compensation, if required.
The following sections describe the design requirements for a typical LM3478 boost application.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Power Inductor Selection
The inductor is one of the two energy storage elements in a boost converter. Figure 29 shows how the inductor
current varies during a switching cycle. The current through an inductor is quantified using Equation 10, which
shows the relationship of L, IL and VL.
(10)
The important quantities in determining a proper inductance value are IL (the average inductor current) and ΔIL
(the inductor current ripple). If ΔIL is larger than IL, the inductor current will drop to zero for a portion of the cycle
and the converter will operate in the DCM. All the analysis in this datasheet assumes operation in the CCM. To
operate in the CCM, the following condition must be met by using Equation 11.
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Typical Applications (continued)
(11)
Choose the minimum IOUT to determine the minimum inductance value. A common choice is to set ΔIL to 30% of
IL. Choosing an appropriate core size for the inductor involves calculating the average and peak currents
expected through the inductor. Use Equation 12, Equation 13, and Equation 14 to the peak inductor current in a
boost converter.
ILPEAK = Average IL(max) + ΔIL(max)
Average IL(max) = Iout / (1-D)
ΔIL(max) = D x Vin / (2 x fs x L)
(12)
(13)
(14)
An inductor size with ratings higher than these values has to be selected. If the inductor is not properly rated,
saturation will occur and may cause the circuit to malfunction.
The LM3478 can be set to switch at very high frequencies. When the switching frequency is high, the converter
can be operated with very small inductor values. The LM3478 senses the peak current through the switch which
is the same as the peak inductor current as calculated in the previous equation.
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Typical Applications (continued)
IL (A)
VIN
L
VIN VOUT
L
'iL
IL_AVG
t (s)
D*Ts
Ts
(a)
ID (A)
VIN - V OUT
L
ID_AVG
=IOUT_AVG
t (s)
D*Ts
Ts
(b)
ISW (A)
VIN
L
ISW_AVG
t (s)
D*Ts
Ts
(C)
Figure 29. Inductor Current and Diode Current
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Typical Applications (continued)
8.2.1.2.2 Programming the Output Voltage
The output voltage can be programmed using a resistor divider between the output and the FB pin. The resistors
are selected such that the voltage at the FB pin is 1.26 V. Pick RF1 (the resistor between the output voltage and
the feedback pin) and RF2 (the resistor between the feedback pin and ground) can be selected using the
following equation,
RF2 = (1.26 V x RF1) / (Vout - 1.26 V)
(15)
A 100-pF capacitor may be connected between the feedback and ground pins to reduce noise.
8.2.1.2.3 Setting the Current Limit
The maximum amount of current that can be delivered to the load is set by the sense resistor, RSEN. Current limit
occurs when the voltage that is generated across the sense resistor equals the current sense threshold voltage,
VSENSE. When this threshold is reached, the switch will be turned off until the next cycle. Limits for VSENSE are
specified in the electrical characteristics section. VSENSE represents the maximum value of the internal control
signal VCS as shown in Figure 30. This control signal, however, is not a constant value and changes over the
course of a period as a result of the internal compensation ramp (VSL). Therefore the current limit threshold will
also change. The actual current limit threshold is a function of the sense voltage (VSENSE) and the internal
compensation ramp:
RSEN x ISWLIMIT = VCSMAX = VSENSE - (D x VSL)
(16)
Where ISWLIMIT is the peak switch current limit, defined by Equation 17.
120
VSL
DUTY CYCLE (%)
100
80
VSENSE
60
FS = 500 kHz
40
20
FS =
250 kHz
0
0.000 0.100
0.200
0.300
0.400
0.500
CURRENT SENSE VOLTAGE (V)
Figure 30. Current Sense Voltage vs Duty Cycle
Figure 30 shows how VCS (and current limit threshold voltage) change with duty cycle. The curve is equivalent to
the internal compensation ramp slope (Se) and is bounded at low duty cycle by VSENSE, shown as a dotted line.
As duty cycle increases, the control voltage is reduced as VSL ramps up. The graph also shows the short circuit
current limit threshold of 343 mV (typical) during the 325 ns (typical) blanking time. For higher frequencies this
fixed blanking time obviously occupies more duty cycle, percentage wise. Since current limit threshold varies with
duty cycle, the use Equation 17 to select RSEN and set the desired current limit threshold:
VSENSE - (D x VSL)
RSEN =
ISWLIMIT
(17)
The numerator of Equation 17 is VCS, and ISWLIMIT using Equation 18.
ISWLIMIT =
20
IOUT
+
(D x VIN)
(1-D) (2 x fS x L)
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(18)
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Typical Applications (continued)
To avoid false triggering, the current limit value should have some margin above the maximum operating value,
typically 120%. Values for both VSENSE and VSL are specified in Electrical Characteristics. However, calculating
with the limits of these two specs could result in an unrealistically wide current limit or RSEN range. Therefore,
Equation 19 is recommended, using the VSL ratio value given in Electrical Characteristics.
VSENSE - (D x VSENSE x VSLratio)
RSEN =
ISWLIMIT
(19)
RSEN is part of the current mode control loop and has some influence on control loop stability. Therefore, once
the current limit threshold is set, loop stability must be verified. As described in the slope compensation section,
Equation 20 must hold true for a current mode converter to be stable.
Sf - Se < Sn + Se
(20)
To verify that this equation holds true, use Equation 21.
2 x VSL x fS x L
RSEN <
Vo - (2 x VIN)
(21)
If the selected RSEN is greater than this value, additional slope compensation must be added to ensure stability,
as described in the section below.
8.2.1.2.4 Current Limit with External Slope Compensation
RSL is used to add additional slope compensation when required. It is not necessary in most designs and RSL
should be no larger than necessary. Select RSL according to Equation 22.
RSEN x (Vo - 2VIN)
- VSL
2 x fS x L
RSL >
40 PA
(22)
Where RSEN is the selected value based on current limit. With RSL installed, the control signal includes additional
external slope to stabilize the loop, which will also have an effect on the current limit threshold. Therefore, the
current limit threshold must be re-verified, as illustrated in Equation 23, Equation 24, and Equation 25 below.
VCS = VSENSE – (D x (VSL + ΔVSL))
(23)
Where ΔVSL is the additional slope compensation generated as discussed in the slope compensation ramp
section and calculated using Equation 24.
ΔVSL = 40 µA x RSL
(24)
This changes the equation for current limit (or RSEN) as shown in Equation 25.
VSENSE - (D x(VSL + 'VSL))
ISWLIMIT =
RSEN
(25)
The RSEN and RSL values may have to be calculated iteratively in order to achieve both the desired current limit
and stable operation. In some designs RSL can also help to filter noise on the ISEN pin.
If the inductor is selected such that ripple current is the recommended 30% value, and the current limit threshold
is 120% of the maximum peak, a simpler method can be used to determine RSEN. Equation 26 below will provide
optimum stability without RSL, provided that the above 2 conditions are met.
VSENSE
RSEN =
Vo - Vi
xD
ISWLIMIT +
L x fS
(26)
8.2.1.2.5 Power Diode Selection
Observation of the boost converter circuit shows that the average current through the diode is the average load
current, and the peak current through the diode is the peak current through the inductor. The diode should be
rated to handle more than its peak current. The peak diode current can be calculated using Equation 27.
ID(Peak) = IOUT/ (1−D) + ΔIL
(27)
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Typical Applications (continued)
Thermally the diode must be able to handle the maximum average current delivered to the output. The peak
reverse voltage for boost converters is equal to the regulated output voltage. The diode must be capable of
handling this voltage. To improve efficiency, a low forward drop schottky diode is recommended.
8.2.1.2.6 Power MOSFET Selection
The drive pin of the LM3478 must be connected to the gate of an external MOSFET. The drive pin (DR) voltage
depends on the input voltage (see Typical Characteristics). In most applications, a logic level MOSFET can be
used. For very low input voltages, a sub logic level MOSFET should be used. The selected MOSFET has a great
influence on the system efficiency. The critical parameters for selecting a MOSFET are:
1. Minimum threshold voltage, VTH(MIN)
2. On-resistance, RDS(ON)
3. Total gate charge, Qg
4. Reverse transfer capacitance, CRSS
5. Maximum drain to source voltage, VDS(MAX)
The off-state voltage of the MOSFET is approximately equal to the output voltage. Vds(max) must be greater
than the output voltage. The power losses in the MOSFET can be categorized into conduction losses and
switching losses. RDS(ON) is needed to estimate the conduction losses, Pcond:
Pcond = I2 x RDS(ON) x D
(28)
The temperature effect on the RDS(ON) usually is quite significant. Assume 30% increase at hot.
For the current I in Equation 28 the average inductor current may be used.
Especially at high switching frequencies the switching losses may be the largest portion of the total losses.
The switching losses are very difficult to calculate due to changing parasitics of a given MOSFET in operation.
Often the individual MOSFET's data sheet does not give enough information to yield a useful result. Equation 29
and Equation 30 give a rough idea how the switching losses are calculated:
PSW =
ILmax x Vout
2
x fSW x (tLH + tHL)
(29)
RdrOn
Qgs
x
tLH = Qgd +
Vdr - Vgsth
2
(30)
8.2.1.2.7 Input Capacitor Selection
Due to the presence of an inductor at the input of a boost converter, the input current waveform is continuous
and triangular as shown in Figure 29. The inductor ensures that the input capacitor sees fairly low ripple currents.
However, as the input capacitor gets smaller, the input ripple goes up. The RMS current in the input capacitor is
given using Equation 31.
(31)
The input capacitor should be capable of handling the RMS current. Although the input capacitor is not as critical
in a boost application, low values can cause impedance interactions. Therefore a good quality capacitor should
be chosen in the range of 10 µF to 20 µF. If a value lower than 10 µF is used, then problems with impedance
interactions or switching noise can affect the LM3478. To improve performance, especially with Vin below 8 volts,
it is recommended to use a 20 Ohm resistor at the input to provide an RC filter. The resistor is placed in series
with the VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 31). A 0.1-µF or 1-µF
ceramic capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the
other side of the resistor at the input power supply.
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Typical Applications (continued)
RIN
VIN
LM3478
CBYPASS
VIN
CIN
Figure 31. Reducing IC Input Noise
8.2.1.2.8 Output Capacitor Selection
The output capacitor in a boost converter provides all the output current when the inductor is charging. As a
result it sees very large ripple currents. The output capacitor should be capable of handling the maximum RMS
current. Equation 32 shows the RMS current in the output capacitor.
(32)
Where
(33)
The ESR and ESL of the capacitor directly control the output ripple. Use capacitors with low ESR and ESL at the
output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer electrolytic,
polymer tantalum, or multi-layer ceramic capacitors are recommended at the output.
For applications that require very low output voltage ripple, a second stage LC filter often is a good solution. Most
of the time it is lower cost to use a small second Inductor in the power path and an additional final output
capacitor than to reduce the output voltage ripple by purely increasing the output capacitor without an additional
LC filter.
8.2.1.2.9 Compensation
For detailed explanation on how to select the right compensation components to attach to the compensation pin
for a boost topology, please see AN-1286 Compensation For The LM3748 Boost Controller SNVA067.
8.2.1.3 Application Curves
Figure 32. Efficiency vs Load Current (9-V In and 12-V Out)
Figure 33. Efficiency vs Load Current (3.3-V In and 5-V
Out)
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Typical Applications (continued)
8.2.2 Typical SEPIC Converter
Figure 34. Typical SEPIC Converter
Since the LM3478 controls a low-side N-Channel MOSFET, it can also be used in SEPIC (Single Ended Primary
Inductance Converter) applications. An example of a SEPIC using the LM3478 is shown in Figure 34. Note that
the output voltage can be higher or lower than the input voltage. The SEPIC uses two inductors to step-up or
step-down the input voltage. The inductors L1 and L2 can be two discrete inductors or two windings of a coupled
inductor since equal voltages are applied across the inductor throughout the switching cycle. Using two discrete
inductors allows use of catalog magnetics, as opposed to a custom inductor. The input ripple can be reduced
along with size by using the coupled windings for L1 and L2.
Due to the presence of the inductor L1 at the input, the SEPIC inherits all the benefits of a boost converter. One
main advantage of a SEPIC over a boost converter is the inherent input to output isolation. The capacitor CS
isolates the input from the output and provides protection against a shorted or malfunctioning load. Hence, the
SEPIC is useful for replacing boost circuits when true shutdown is required. This means that the output voltage
falls to 0V when the switch is turned off. In a boost converter, the output can only fall to the input voltage minus a
diode drop.
The duty cycle of a SEPIC is given using Equation 34.
(34)
In Equation 34, VQ is the on-state voltage of the MOSFET, Q, and VDIODE is the forward voltage drop of the
diode.
8.2.2.1 Design Requirements
To properly size the components for the application, the designer needs the following parameters: input voltage
range, output voltage, output current range, and required switching frequency. These four main parameters affect
the choices of component available to achieve a proper system behavior.
For the power supply, the input impedance of the supply rail should be low enough that the input current
transient does not drop below the UVLO value. The factors determining the choice of inductor used should be
the average inductor current, and the inductor current ripple. If the switching frequency is set high, the converter
can be operated with very small inductor values. The maximum current that can be delivered to the load is set by
the sense resistor, RSEN. Current limit occurs when the voltage generated across the sense resistor equals the
current sense threshold voltage, VSENSE. Also, a resistor RSL adds additional slope compensation, if required.
The following sections describe the design requirements for a typical LM3478 boost application.
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Typical Applications (continued)
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Power MOSFET Selection
As in a boost converter, parameters governing the selection of the MOSFET are the minimum threshold voltage,
VTH(MIN), the on-resistance, RDS(ON), the total gate charge, Qg, the reverse transfer capacitance, CRSS, and the
maximum drain to source voltage, VDS(MAX). The peak switch voltage in a SEPIC is given using Equation 35.
VSW(PEAK) = VIN + VOUT + VDIODE
(35)
The selected MOSFET should satisfy the condition:
VDS(MAX) > VSW(PEAK)
(36)
The peak switch current is given using Equation 37.
(37)
The RMS current through the switch is given using Equation 38.
(38)
8.2.2.2.2 Power Diode Selection
The Power diode must be selected to handle the peak current and the peak reverse voltage. In a SEPIC, the
diode peak current is the same as the switch peak current. The off-state voltage or peak reverse voltage of the
diode is VIN + VOUT. Similar to the boost converter, the average diode current is equal to the output current.
Schottky diodes are recommended.
8.2.2.2.3 Selection of Inductors L1 and L2
Proper selection of inductors L1 and L2 to maintain continuous current conduction mode requires calculations of
the following parameters.
Average current in the inductors can be calculated using Equation 39.
(39)
(40)
IL2AVE = IOUT
Peak to peak ripple current, to calculate core loss if necessary using Equation 41 and Equation 42.
(41)
(42)
Maintaining the condition IL > ΔiL/2 to ensure continuous current conduction yields Equation 43 and Equation 44.
(VIN - VQ)(1-D)
L1 >
2IOUTfS
(43)
(VIN - VQ)D
L2 >
2IOUTfS
(44)
Peak current in the inductor, use Equation 45 and Equation 46 to ensure the inductor does not saturate.
(45)
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Typical Applications (continued)
(46)
IL1PK must be lower than the maximum current rating set by the current sense resistor.
The value of L1 can be increased above the minimum recommended to reduce input ripple and output ripple.
However, once DIL1 is less than 20% of IL1AVE, the benefit to output ripple is minimal.
By increasing the value of L2 above the minimum recommended, ΔIL2 can be reduced, which in turn will reduce
the output ripple voltage:
'VOUT =
(
IOUT
1-D
+
'IL2
2
)
ESR
(47)
where ESR is the effective series resistance of the output capacitor.
If L1 and L2 are wound on the same core, then L1 = L2 = L. All of the previous equations will hold true if the
inductance is replaced by 2L.
8.2.2.2.4 Sense Resistor Selection
The peak current through the switch, ISW(PEAK) can be adjusted using the current sense resistor, RSEN, to provide
a certain output current. Resistor RSEN can be selected using Equation 48
VSENSE - D(VSL + 'VSL)
RSEN =
ISWPEAK
(48)
8.2.2.2.5 Sepic Capacitor Selection
The selection of the SEPIC capacitor, CS, depends on the RMS current. The RMS current of the SEPIC
capacitor is given by Equation 49.
(49)
The SEPIC capacitor must be rated for a large ACrms current relative to the output power. This property makes
the SEPIC much better suited to lower power applications where the RMS current through the capacitor is
relatively small (relative to capacitor technology). The voltage rating of the SEPIC capacitor must be greater than
the maximum input voltage. There is an energy balance between CS and L1, which can be used to determine
the value of the capacitor. Equation 50 shows the basic energy balance.
(50)
where
(51)
is the ripple voltage across the SEPIC capacitor, and
(52)
is the ripple current through the inductor L1. The energy balance equation can be solved using Equation 53 to
provide a minimum value for CS.
(53)
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Typical Applications (continued)
8.2.2.2.6 Input Capacitor Selection
Similar to a boost converter, the SEPIC has an inductor at the input. Hence, the input current waveform is
continuous and triangular. The inductor ensures that the input capacitor sees fairly low ripple currents. However,
as the input capacitor gets smaller, the input ripple goes up. The RMS current in the input capacitor is given
using Equation 54.
(54)
The input capacitor should be capable of handling the RMS current. Although the input capacitor is not as critical
in a boost application, low values can cause impedance interactions. Therefore a good quality capacitor should
be chosen in the range of 10µF to 20µF. If a value lower than 10 µF is used, then problems with impedance
interactions or switching noise can affect the LM3478. To improve performance, especially with VIN below 8 volts,
TI recommends that the user uses a 20Ω resistor at the input to provide a RC filter. The resistor is placed in
series with the VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 31). A 0.1-µF or 1µF ceramic capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the
other side of the resistor with the input power supply.
8.2.2.2.7 Output Capacitor Selection
The output capacitor of the SEPIC sees very large ripple currents (similar to the output capacitor of a boost
converter). The RMS current through the output capacitor is given using Equation 55.
IRMS =
2
ISWPK2 - ISWPK ('IL1 + 'IL2)+ ('IL1 + 'IL2) (1-D) - IOUT2
3
(55)
The ESR and ESL of the output capacitor directly control the output ripple. Use low capacitors with low ESR and
ESL at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer
electrolytic and polymer tantalum, Sanyo-OSCON, or multi-layer ceramic capacitors are recommended at the
output for low ripple.
8.2.2.3 Application Curves
Figure 35. Efficiency vs Load Current (3.3-V In and 12-V
Out)
Figure 36. Efficiency vs Load Current (5-V In and 12-V Out)
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9 Power Supply Recommendations
The LM3478 is designed to operate from various DC power supply including a car battery. If so, VIN input should
be protected from reversal voltage and voltage dump over 40 volts. The impedance of the input supply rail
should be low enough that the input current transient does not cause drop below VIN UVLO level. If the input
supply is connected by using long wires, additional bulk capacitance may be required in addition to normal input
capacitor.
10 Layout
10.1 Layout Guidelines
Good board layout is critical for switching controllers. First the ground plane area must be sufficient for thermal
dissipation purposes and second, appropriate guidelines must be followed to reduce the effects of switching
noise. Switching converters are very fast switching devices. In such devices, the rapid increase of input current
combined with the parasitic trace inductance generates unwanted Ldi/dt noise spikes. The magnitude of this
noise tends to increase as the output current increases. This parasitic spike noise may turn into electromagnetic
interference (EMI), and can also cause problems in device performance. Therefore, care must be taken in layout
to minimize the effect of this switching noise. The current sensing circuit in current mode devices can be easily
affected by switching noise. This noise can cause duty cycle jittering which leads to increased spectral noise.
Although the LM3478 has 325 ns blanking time at the beginning of every cycle to ignore this noise, some noise
may remain after the blanking time.
The most important layout rule is to keep the AC current loops as small as possible. Figure 37 shows the current
flow of a boost converter. The top schematic shows a dotted line which represents the current flow during onstate and the middle schematic shows the current flow during off-state. The bottom schematic shows the currents
we refer to as AC currents. They are the most critical ones since current is changing in very short time periods.
The dotted lined traces of the bottom schematic are the once to make as short as possible.
The PGND and AGND pins have to be connected to the same ground very close to the IC. To avoid ground loop
currents, attach all the grounds of the system only at one point.
A ceramic input capacitor should be connected as close as possible to the Vin pin and grounded close to the
GND pin.
For more information about layout in switch mode power supplies please refer to AN-1229 Simple Switcher PCB
Layout Guidelines, SNVA054.
Figure 37. Current Flow in a Boost Application
28
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LM3478, LM3478Q-Q1
www.ti.com
SNVS085W – JULY 2000 – REVISED DECEMBER 2014
Rs
GND
Rsn
Rc
COUT3
Cc
COUT2
COUT1
Cc2
Rfbb
Cff
Rfbt
10.2 Layout Example
Csn
OUTPUT+
LM3478
Cbyp
D1
Rbyp
Rfa
L1
Rdr
Q1
SW_TP
Q1
SD
INPUT+
GND
CIN1
CIN2
See evaluation modules for more detailed examples.
Figure 38. Typical Layout for a Boost Converter
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LM3478, LM3478Q-Q1
SNVS085W – JULY 2000 – REVISED DECEMBER 2014
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• AN-1286 Compensation for the LM3748 Boost Controller SNVA067
• AN-1229 Simple Switcher PCB Layout Guidelines SNVA054
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM3478
Click here
Click here
Click here
Click here
Click here
LM3478Q-Q1
Click here
Click here
Click here
Click here
Click here
11.3 Trademarks
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM3478MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
L3478
MA
LM3478MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
L3478
MA
TBD
Call TI
Call TI
LM3478MM
NRND
VSSOP
DGK
8
1000
-40 to 125
S14B
LM3478MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM
& no Sb/Br)
-40 to 125
S14B
LM3478MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM
& no Sb/Br)
-40 to 125
S14B
LM3478QMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SSFB
LM3478QMMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SSFB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2015
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM3478MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM3478MM
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3478MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3478MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3478QMM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3478QMMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3478MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM3478MM
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM3478MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM3478MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LM3478QMM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM3478QMMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
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