TI CDCLVC1102 3.3 v and 2.5 v lvcmos high-performance clock buffer family Datasheet

CDCLVC11xx
www.ti.com
SCAS895 – MAY 2010
3.3 V and 2.5 V LVCMOS High-Performance Clock Buffer Family
Check for Samples: CDCLVC11xx
FEATURES
1
•
•
•
•
•
High-Performance 1:2, 1:3, 1:4, 1:6, 1:8, 1:10,
1:12 LVCMOS Clock Buffer Family
Very Low Pin-to-Pin Skew < 50 ps
Very Low Additive Jitter < 100 fs
Supply Voltage: 3.3 V or 2.5 V
fmax = 250 MHz for 3.3 V
fmax = 180 MHz for 2.5 V
CLKIN
LV
CMOS
LV
CMOS
Y0
LV
CMOS
Y1
LV
CMOS
Y2
LV
CMOS
Y3
•
•
•
LV
CMOS
•
•
Operating Temperature Range: –40°C to 85°C
Available in 8-, 14-, 16-, 20-, 24-Pin TSSOP
Package (all pin compatible)
APPLICATIONS
•
General Purpose Communication, Industrial
and Consumer Applications
CLKIN 1
1G 2
Y0 3
GND 4
VDD 5
Y4 6
GND 7
Y6 8
VDD 9
Y9 10
GND 11
Y11 12
CDCLVC
CDCLVC
CDCLVC
1102
1103
1104
CDCLVC
1106
CDCLVC
1108
CDCLVC
1110
CDCLVC
1112
24
23
22
21
20
19
18
17
16
15
14
13
Y1
Y3
VDD
Y2
GND
Y5
VDD
Y7
Y8
GND
Y 10
VDD
Yn
1G
DESCRIPTION
The CDCLVC11xx is a modular, high-performance, low-skew, general purpose clock buffer family from Texas
Instruments.
The whole family is designed with a modular approach in mind. It is intended to round up TI's series of LVCMOS
clock generators.
There are 7 different fan-out variations, 1:2 to 1:12, available. All of the devices are pin compatible to each other
for easy handling.
All family members share the same high performing characteristics like low additive jitter, low skew, and wide
operating temperature range.
The CDCLVC11xx supports an asynchronous output enable control (1G) which switches the outputs into a low
state when 1G is low. Also, versions with synchronized enable control for glitch free switching and three-state
outputs are planned in future device options.
The CDCLVC11xx operate in a 2.5 V and 3.3 V environment and are characterized for operation from –40°C to
85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CDCLVC11xx
SCAS895 – MAY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE OPTIONS
CLKIN
1G
Y0
GND
1
2
3
4
CLKIN
1G
Y0
GND
1
2
3
4
CDCLVC1103
CLKIN
1G
Y0
GND
1
2
3
4
CDCLVC1104
CDCLVC1102
8
7
6
5
Y1
NC
VDD
NC
8
7
6
5
Y1
NC
VDD
Y2
8
7
6
5
Y1
Y3
VDD
Y2
CLKIN
1G
Y0
GND
VDD
Y4
GND
1
2
3
4
5
6
7
CLKIN
1G
Y0
GND
VDD
Y4
GND
Y6
1
2
3
4
5
6
7
8
CDCLVC1106
CDCLVC1108
14
13
12
11
10
9
8
Y1
Y3
VDD
Y2
GND
Y5
VDD
16
15
14
13
12
11
10
9
Y1
Y3
VDD
Y2
GND
Y5
VDD
Y7
CLKIN 1
1G 2
Y0 3
GND 4
VDD 5
Y4 6
GND 7
Y6 8
VDD 9
Y 9 10
CLKIN 1
1G 2
Y0 3
GND 4
VDD 5
Y4 6
GND 7
Y6 8
VDD 9
Y 9 10
GND 11
Y 11 12
CDCLVC 1110
20
19
18
17
16
15
14
13
12
11
Y1
Y3
VDD
Y2
GND
Y5
VDD
Y7
Y8
GND
CDCLVC 1112
24
23
22
21
20
19
18
17
16
15
14
13
Y1
Y3
VDD
Y2
GND
Y5
VDD
Y7
Y8
GND
Y 10
VDD
PIN FUNCTIONS
DEVICES
LVCMOS
CLOCK INPUT
CLOCK OUTPUT
ENABLE
LVCMOS CLOCK OUTPUT
SUPPLY
VOLTAGE
GROUND
CLKIN
1G
Y0, Y1, … Y11
VDD
GND
CDCLVC1102
1
2
3, 8
6
4
CDCLVC1103
1
2
3, 8, 5
6
4
CDCLVC1104
1
2
3, 8, 5, 7
6
4
CDCLVC1106
1
2
3, 14, 11, 13, 6, 9
5, 8, 12
4, 7, 10
CDCLVC1108
1
2
3, 16, 13, 15, 6, 11, 8, 9
5, 10, 14
4, 7, 12
CDCLVC1110
1
2
3, 20, 17, 19, 6, 15, 8, 13, 10
5, 9, 14, 18
4, 7, 11, 16
CDCLVC1112
1
2
3, 24, 21, 23, 6, 19, 8, 17, 16, 10, 14, 12
5, 9, 13, 18, 22
4, 7, 11, 15, 20
OUTPUT LOGIC TABLE
INPUTS
CLKIN
2
OUTPUTS
1G
Yn
X
L
L
L
H
L
H
H
H
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CDCLVC11xx
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SCAS895 – MAY 2010
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE / UNIT
VDD
Supply voltage range
VIN
Input voltage range
VO
Output voltage range
IIN
Input current
±20 mA
IO
Continuous output current
±50 mA
TJ
Maximum junction temperature
TST
Storage temperature range
(1)
(2)
–0.5 V to 4.6 V
(2)
–0.5 V to VDD + 0.5 V
(2)
–0.5 V to VDD + 0.5 V
125°C
–65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This value is limited to 4.6 V maximum.
THERMAL INFORMATION
DCDLVC1102/03/04
CDCLVC1106
CDCLVC1108
CDCLVC11010
PW
PW
PW
PW
PW
8 PINS
14 PINS
16 PINS
20 PINS
24 PINS
149.4
112.6
108.4
83.0
87.9
69.4
48.0
33.6
32.3
26.5
THERMAL METRIC (1)
Junction-to-ambient thermal resistance (2)
qJA
qJC(top)
(1)
(2)
(3)
Junction-to-case(top) thermal resistance
(3)
CDCLVC1112
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage range
VIL
Low-level input voltage
VIH
High-level input voltage
Vth
Input threshold voltage
tr / tf
Input slew rate
MIN
NOM
MAX
3.3 V supply
3.0
3.3
3.6
2.5 V supply
2.3
2.5
2.7
VDD = 3.0 V to 3.6 V
VDD/2 – 600
VDD = 2.3 V to 2.7 V
VDD/2 – 400
VDD = 3.0 V to 3.6 V
VDD/2 + 600
VDD = 2.3 V to 2.7 V
VDD/2 + 400
VDD = 2.3 V to 3.6 V
1
V
mV
mV
VDD/2
1.8
UNIT
mV
4
tw
Minimum pulse width at
CLKIN
VDD = 3.0 V to 3.6 V
VDD = 2.3 V to 2.7 V
2.75
fCLK
LVCMOS clock Input
Frequency
VDD = 3.0 V to 3.6 V
DC
250
VDD = 2.3 V to 2.7 V
DC
180
TA
Operating free-air temperature
–40
85
V/ns
ns
MHz
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°C
3
CDCLVC11xx
SCAS895 – MAY 2010
www.ti.com
DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
MIN TYP (1)
MAX
1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V
6
10
mA
1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 2.7 V
3
6
mA
60
µA
PARAMETER
CONDITION
UNIT
OVERALL PARAMETERS FOR ALL VERSIONS
IDD
Static device current (2)
IPD
Power down current
1G = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V or 2.7 V
Power dissipation capacitance
per output (3)
VDD = 3.3 V; f = 10 MHz
6
pF
VDD = 2.5 V; f = 10 MHz
4.5
pF
CPD
Input leakage current at 1G
II
Input leakage current at CLKIN
ROUT Output impedance
fOUT
Output frequency
±8
VI = 0 V or VDD, VDD = 3.6 V or 2.7 V
± 25
VDD = 3.3 V
Ω
45
VDD = 2.5 V
µA
Ω
60
VDD = 3.0 V to 3.6 V
DC
250
MHz
VDD = 2.3 V to 2.7 V
DC
180
MHz
OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V
VOH
High-level output voltage
VOL
Low-level output voltage
VDD = 3 V, IOH = –0.1 mA
2.9
VDD = 3 V, IOH = –8 mA
2.5
VDD = 3 V, IOH = –12 mA
2.2
VDD = 3 V, IOL = 0.1 mA
0.1
VDD = 3 V, IOL = 8 mA
0.5
VDD = 3 V, IOL = 12 mA
0.8
tPLH,
tPHL
Propagation delay
CLKIN to Yn
tsk(o)
Output skew
Equal load of each output
tr/tf
Rise and fall time
20%–80% (VOH - VOL)
tDIS
Output disable time
tEN
Output enable time
tsk(p)
Pulse skew ;
tPLH(Yn) – tPHL(Yn)
To be measured with input duty cycle of 50%
(4)
V
V
0.8
2.0
ns
50
ps
0.3
0.8
ns
1G to Yn
6
ns
1G to Yn
6
ns
180
ps
tsk(pp) Part-to-part skew
Under equal operating conditions for two parts
0.5
ns
tjitter
12kHz…20 MHz, fOUT = 250 MHz
100
fs
(1)
(2)
(3)
(4)
4
Additive jitter rms
All typical values are at respective nominal VDD. For switching characteristics, outputs are terminated to 50 Ω to VDD/2 (see Figure 1).
For dynamic IDD over frequency see Figure 8 and Figure 9.
This is the formula for the power dissipation calculation (see Figure 8 and the Power Consideration section).
Ptot = Pstat + Pdyn + PCload [W]
Pstat = VDD × IDD [W]
Pdyn = CPD × VDD2 × ƒ [W]
PCload = Cload × VDD2 × ƒ × n [W]
n = Number of switching output pins
tsk(p) depends on output rise- and fall-time (tr/tf). The output duty-cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse-width of output waveform and tperiod is 1/fOUT.
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SCAS895 – MAY 2010
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
CONDITION
MIN TYP (1)
MAX
UNIT
OUTPUT PARAMETERS FOR VDD = 2.5 V ± 0.2 V
VDD = 2.3 V, IOH = –0.1 mA
2.2
VDD = 2.3 V, IOH = –8 mA
1.7
VOH
High-level output voltage
VOL
Low-level output voltage
tPLH,
tPHL
Propagation delay
CLKIN to Yn
tsk(o)
Output skew
Equal load of each output
tr/tf
Rise and fall time
20%–80% reference point
tDIS
Output disable time
tEN
tsk(p)
V
VDD = 2.3 V, IOL = 0.1 mA
0.1
VDD = 2.3 V, IOL = 8 mA
0.5
V
1.0
2.6
ns
50
ps
0.3
1.2
ns
1G to Yn
10
ns
Output enable time
1G to Yn
10
ns
Pulse skew ;
tPLH(Yn) – tPHL(Yn)
To be measured with input duty cycle of 50%
220
ps
tsk(pp) Part-to-part skew
Under equal operating conditions for two parts
1.2
ns
tjitter
12kHz…20 MHz, fOUT = 180 MHz
350
fs
(5)
Additive jitter rms
(5)
tsk(p) depends on output rise- and fall-time (tr/tf). The output duty-cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is
pulse-width of output waveform and tperiod is 1/fOUT.
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PARAMETERS MEASUREMENT INFORMATION
VDD = 3.3 V or 2.5 V
LVCMOS
Output
ZO = 50 W
R = 50 W
C = 2 pF
parasitic capasitance
from Measurement Equipment
VDD/2
Figure 1. Test Load Circuit
VDD
VDD = 3.3 V or 2.5 V
R= 100 W
LVCMOS
Output
ZO = 50 W
parasitic input capacitance
R= 100 W
Figure 2. Application Load With 50 Ω Line Termination
VDD = 3.3 V or 2.5 V
RS = 10 W (VDD = 3.3 V)
RS = 0 W (VDD = 2.5 V)
LVCMOS
Output
ZO = 50 W
parasitic input capacitance
Figure 3. Application Load With Series Line Termination
VDD / 2
VIN / 2
Yn
1G
VIN / 2
Yn
tDIS
tsk(o)
tEN
Figure 4. tDIS and tEN for Disable Low
6
VDD / 2
Yn+1
tsk(o)
Figure 5. Output Skew tsk(o)
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SCAS895 – MAY 2010
PARAMETERS MEASUREMENT INFORMATION (continued)
V DD / 2
CLKIN
CLKIN
VOH
V DD / 2
Yn
80 % V OH -V OL
Yn
20 % V OH -V OL
V OL
tr
t PLH
tf
t PHL
Note: tsk (p) = | tPLH – t PHL |
Figure 6. Pulse Skew tsk(p) and Propagation Delay
tPLH/tPHL
Figure 7. Rise/Fall Times tr/tf
TYPICAL CHARACTERISTICS
Power Consideration
The following power consideration refers to the device-consumed power consumption only. The device power
consumption is the sum of static power and dynamic power. The dynamic power usage consists of two
components:
1. Power used by the device as it switches states.
2. Power required to charge any output load.
The output load can be capacitive only or capacitive and resistive. The following formula and the power graphs in
Figure 8 and Figure 9 can be used to obtain the power consumption of the device:
Pdev = Pstat + n (Pdyn + PCload)
Pstat = VDD x IDD
Pdyn + PCload = see Figure 8 and Figure 9
where:
VDD = Supply voltage (3.3 V or 2.5 V)
IDD = Static device current (typ 6 mA for VDD = 3.3 V; typ 3 mA for VDD = 2.5 V)
n = Number of switching output pins
Example for Device Power Consumption for CDCLVC1104: 4 outputs are switching, f = 120 MHz, VDD = 3.3 V
and Cload = 2 pF per output:
Pdev = Pstat + n (Pdyn + PCload) = 19.8 mW + 40 mW = 59.8 mW
Pstat = VDD x IDD = 6 mA x 3.3 V = 19.8 mW
n (Pdyn + PCload) = 4 x 10 mW = 40 mW
NOTE
For dimensioning the power supply, the total power consumption needs to be considered.
The total power consumption is the sum of the device power consumption and the power
consumption of the load.
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TYPICAL CHARACTERISTICS (continued)
40
15
VDD = 3.3 V
VDD = 2.5 V
Pdyn + PCload8pF
30
Pdyn + PCload50/2
20
10
Pdyn + PCload2pF
0
0
Device Power Consumption - mW
Device Power Consumption - mW
Pdyn + PCload8pF
Pdyn + PCload50/2
10
5
Pdyn + PCload2pF
0
0
20 40 60 80 100 120 140 160 180 200 220 240
f - Clock Frequency - MHz
Figure 8. Device Power Consumption vs Clock Frequency
(Load 50Ω into VDD/2. 2pF, 8pF; Per Output)
60
80 100 120 140
f - Clock Frequency - MHz
160 180
3
VDD = 2.5 V
Idyn - Dynamic Supply Current - mA
VDD = 3.3 V
Idyn - Dynamic Supply Current - mA
40
Figure 9. Device Power Consumption vs Clock Frequency
(Load 50Ω into VDD/2. 2pF, 8pF; Per Output)
5
4
Idyn = CPD * VDD * f
3
2
1
0
0
20 40 60 80 100 120 140 160 180 200 220 240
f - Clock Frequency - MHz
Figure 10. Dynamic Supply Current vs Clock Frequency
(CPD = 6pF, No Load; Per Output)
8
20
2
Idyn = CPD * VDD * f
1
0
0
20
40
60
80 100 120 140
f - Clock Frequency - MHz
160 180
Figure 11. Dynamic Supply Current vs Clock Frequency
(CPD = 4.5pF, No Load; Per Output)
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Jun-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CDCLVC1102PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCLVC1102PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCLVC1103PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCLVC1103PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
CDCLVC1104PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCLVC1104PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
CDCLVC1106PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCLVC1106PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
CDCLVC1108PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCLVC1108PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
CDCLVC1110PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCLVC1110PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
CDCLVC1112PW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCLVC1112PWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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26-Jun-2010
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCLVC1102PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
CDCLVC1103PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
CDCLVC1104PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
CDCLVC1106PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CDCLVC1108PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CDCLVC1110PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
CDCLVC1112PWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCLVC1102PWR
TSSOP
PW
8
2000
346.0
346.0
29.0
CDCLVC1103PWR
TSSOP
PW
8
2000
346.0
346.0
29.0
CDCLVC1104PWR
TSSOP
PW
8
2000
346.0
346.0
29.0
CDCLVC1106PWR
TSSOP
PW
14
2000
346.0
346.0
29.0
CDCLVC1108PWR
TSSOP
PW
16
2000
346.0
346.0
29.0
CDCLVC1110PWR
TSSOP
PW
20
2000
346.0
346.0
33.0
CDCLVC1112PWR
TSSOP
PW
24
2000
346.0
346.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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