IRF IRF7832Z Hexfet power mosfet Datasheet

PD - 96975A
IRF7832Z
HEXFET® Power MOSFET
Applications
l Synchronous MOSFET for Notebook
Processor Power
l Synchronous Rectifier MOSFET for
Isolated DC-DC Converters
VDSS
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
l 20V VGS Max. Gate Rating
l 100% tested for Rg
RDS(on) max
3.8m:@VGS = 10V
30V
Qg
30nC
A
A
D
S
1
8
S
2
7
D
S
3
6
D
G
4
5
D
SO-8
Top View
Absolute Maximum Ratings
Max.
Units
VDS
Drain-to-Source Voltage
Parameter
30
V
VGS
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
± 20
17
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
160
PD @TA = 25°C
Power Dissipation
2.5
PD @TA = 70°C
Power Dissipation
1.6
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
ID @ TA = 25°C
ID @ TA = 70°C
21
c
A
W
W/°C
°C
0.02
-55 to + 150
Thermal Resistance
Parameter
RθJL
RθJA
g
Junction-to-Ambient fg
Junction-to-Drain Lead
Notes  through
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Typ.
Max.
Units
–––
20
°C/W
–––
50
are on page 10
1
06/30/05
IRF7832Z
Static @ T J = 25°C (unless otherwise specified)
Parameter
Min.
BV DSS
Drain-to-Source Breakdown Voltage
∆ΒV DSS /∆T J
R DS(on)
Typ. Max. Units
V
–––
–––
Breakdown Voltage Temp. Coefficient
–––
0.023
–––
V/°C Reference to 25°C, I D = 1mA
Static Drain-to-Source On-Resistance
–––
3.1
3.8
mΩ
–––
3.7
4.5
Gate Threshold Voltage
1.35
–––
2.35
V
∆V GS(th)
Gate Threshold Voltage Coefficient
–––
-5.5
–––
mV/°C
I DSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
80
–––
–––
–––
30
45
gfs
Qg
Forward Transconductance
Total Gate Charge
V GS = 0V, I D = 250µA
V GS = 10V, ID = 20A
V GS = 4.5V, I D = 16A
V GS(th)
I GSS
Conditions
30
e
e
V DS = V GS , ID = 250µA
V DS = 24V, V GS = 0V
V DS = 24V, V GS = 0V, TJ = 125°C
nA
V GS = 20V
V GS = -20V
S
V DS = 15V, I D = 16A
Q gs1
Pre-Vth Gate-to-Source Charge
–––
7.9
–––
Q gs2
Post-Vth Gate-to-Source Charge
–––
2.6
–––
Q gd
Gate-to-Drain Charge
–––
11
–––
ID = 16A
Q godr
–––
8.5
–––
See Fig. 16
Q sw
Gate Charge Overdrive
Switch Charge (Q gs2 + Q gd)
–––
13.6
–––
Q oss
Output Charge
–––
19
–––
nC
Rg
Gate Resistance
–––
1.2
1.9
Ω
t d(on)
Turn-On Delay Time
–––
14
–––
V DD = 15V, V GS = 4.5V
tr
Rise Time
–––
15
–––
ID = 16A
t d(off)
Turn-Off Delay Time
–––
18
–––
tf
Fall Time
–––
5.6
–––
C iss
Input Capacitance
–––
3860
–––
C oss
Output Capacitance
–––
840
–––
C rss
Reverse Transfer Capacitance
–––
370
–––
V DS = 15V
nC
V GS = 4.5V
V DS = 16V, V GS = 0V
ns
Clamped Inductive Load
pF
V DS = 15V
V GS = 0V
ƒ = 1.0MHz
Avalanche Characteristics
E AS
Parameter
Single Pulse Avalanche Energy
I AR
Avalanche Current
c
d
Typ.
Max.
Units
–––
350
mJ
–––
16
A
Diode Characteristics
Parameter
Min.
Typ. Max. Units
IS
Continuous Source Current
–––
–––
3.1
I SM
(Body Diode)
Pulsed Source Current
–––
–––
160
V SD
(Body Diode)
Diode Forward Voltage
–––
–––
1.0
V
t rr
Reverse Recovery Time
–––
16
24
ns
Q rr
Reverse Recovery Charge
–––
29
44
nC
t on
Forward Turn-On Time
2
c
Conditions
MOSFET symbol
A
showing the
integral reverse
D
G
S
p-n junction diode.
TJ = 25°C, IS = 16A, V GS = 0V
TJ = 25°C, IF = 16A, V DD = 15V
di/dt = 500A/µs
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRF7832Z
1000
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
10
TOP
ID, Drain-to-Source Current (A)
TOP
VGS
10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
2.3V
100
1
0.1
2.3V
0.1
1
10
2.3V
≤60µs PULSE WIDTH
Tj = 25°C
0.01
BOTTOM
10
1000
0.1
V DS, Drain-to-Source Voltage (V)
1
10
100
1000
V DS, Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (Α)
≤60µs PULSE WIDTH
Tj = 150°C
1
100
VGS
10V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
2.3V
100
TJ = 150°C
10
T J = 25°C
1
VDS = 15V
≤60µs PULSE WIDTH
0.1
1
2
3
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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ID = 21A
VGS = 10V
1.5
1.0
0.5
4
-60 -40 -20 0
20 40 60 80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRF7832Z
100000
6.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
ID= 16A
10000
Ciss
Coss
1000
5.0
VGS, Gate-to-Source Voltage (V)
C, Capacitance(pF)
C oss = C ds + C gd
Crss
VDS= 24V
VDS= 15V
4.0
3.0
2.0
1.0
0.0
100
1
10
0
100
1000
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
20
100
40
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
100
T J = 150°C
T J = 25°C
10
30
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1
10msec
10
1
1msec
T A = 25°C
Tj = 150°C
Single Pulse
VGS = 0V
0.1
0.1
0.2
0.4
0.6
0.8
1.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
1.2
0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF7832Z
2.5
VGS(th) Gate threshold Voltage (V)
25
ID, Drain Current (A)
20
15
10
5
2.0
ID = 250µA
1.5
1.0
0.5
0
25
50
75
100
125
-75 -50 -25
150
0
25
50
75 100 125 150
T J , Temperature ( °C )
T A , Ambient Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
100
D = 0.50
0.20
0.10
0.05
0.02
0.01
Thermal Response ( Z thJA )
10
1
τJ
0.1
R1
R1
τJ
τ1
τ1
R2
R2
τ2
τ2
R3
R3
τ3
τC
τ
28.314
16
τ3
Ci= τi/Ri
Ci i/Ri
0.01
Ri (°C/W) τi (sec)
5.6971 0.015296
1.214900
40.40000
PDM
t1
SINGLE PULSE
( THERMAL RESPONSE )
0.001
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJA + TA
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF7832Z
RDS(on), Drain-to -Source On Resistance (m Ω)
10
1600
EAS , Single Pulse Avalanche Energy (mJ)
ID = 21A
ID
TOP
1.0A
1.4A
BOTTOM 16A
1400
8
1200
1000
6
T J = 125°C
4
T J = 25°C
2
800
600
400
200
0
2
4
6
8
10
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
VGS, Gate -to -Source Voltage (V)
Fig 13. Maximum Avalanche Energy
vs. Drain Current
Fig 12. On-Resistance vs. Gate Voltage
Current Regulator
Same Type as D.U.T.
V(BR)DSS
tp
15V
50KΩ
12V
.3µF
DRIVER
L
VDS
.2µF
D.U.T.
D.U.T
RG
+
- VDD
IAS
20V
VGS
tp
A
0.01Ω
+
V
- DS
VGS
I AS
3mA
IG
Fig 14. Unclamped Inductive Test Circuit
and Waveform
ID
Current Sampling Resistors
Fig 15. Gate Charge Test Circuit
LD
VDS
VDS
+
90%
VDD D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 16. Switching Time Test Circuit
6
10%
VGS
td(on)
tr
td(off)
tf
Fig 17. Switching Time Waveforms
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IRF7832Z
D.U.T
Driver Gate Drive
ƒ
+
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 18. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 19. Gate Charge Waveform
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7
IRF7832Z
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgs 2
Qgd
⎞ ⎛
⎞
+⎜I ×
× Vin × f ⎟ + ⎜ I ×
× Vin × f ⎟
ig
ig
⎝
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
8
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
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IRF7832Z
SO-8 Package Outline
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IRF7832Z
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
‚ Starting TJ = 25°C, L = 2.7mH, RG = 25Ω, IAS = 16A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board.
Rθ is measured at T J of approximately 90°C.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.06/05
10
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