FEATURES TYPICAL APPLICATIONS CIRCUIT APPLICATIONS Portable and battery-powered instruments and systems High channel density data acquisition systems Precision analog-to-digital converter (ADC) drivers Voltage reference buffers Portable point of sales terminals Active RFID readers 5V C2 10µF IN+ REF VDD IN– C1 2.7nF AD7980 13391-001 ADA4806-1 R3 20Ω GND Figure 1. Driving the AD7980 with the ADA4806-1 Sleep mode reduces the amplifier quiescent current to 74 µA and provides a fast turn-on time of only 0.45 µs, enabling the use of dynamic power scaling for sample rates approaching 2 MSPS. For additional power savings at lower samples rates, the shutdown mode further reduces the quiescent current to only 2.9 µA. The ADA4806-1 operates over a wide range of supply voltages and is fully specified at supplies of 3 V, 5 V and ±5 V. This amplifier is available in a compact, 8-lead SOT-23 package and is rated to operate over the industrial temperature range of −40°C to +125°C. 3.5 3.0 The ADA4806-1 is a high speed, voltage feedback, rail-to-rail output, single operational amplifier with three power modes: full power mode, sleep mode, and shutdown mode. In full power mode, this amplifier provides a wide bandwidth of 105 MHz at a gain of +1, a fast slew rate 160 V/μs, and excellent dc precision with a low input offset voltage of 125 μV (maximum) and an input offset voltage drift of 1.5 μV/°C (maximum), while con-suming only 500 μA of quiescent current. Despite being a low power amplifier, the ADA4806-1 provides excellent overall performance, making it ideal for low power, high resolution data conversion systems. 2.5 SHUTDOWN MODE 2.0 1.5 1.0 SLEEP MODE 0.5 0 1 10 100 ADC SAMPLE RATE (ksps) 1000 Figure 2. Quiescent Power Dissipation vs. ADC Sample Rate, Using Dynamic Power Scaling for the Two Low Power Modes Table 1. Complementary ADCs to the ADA4806-1 Product AD7980 AD7982 AD7984 1 Rev. 0 VDD C4 100nF C3 0.1µF 5V 0V TO VREF GENERAL DESCRIPTION For data conversion applications where minimizing power dissipation is paramount, the ADA4806-1 offers a method to reduce power by dynamically scaling the quiescent power of the ADC driver with the sampling rate of the system by switching the amplifier to a lower power mode between samples. ADA4806-1 2.5V REF POWER CONSUMPTION (mW) Ultralow supply current Full power mode: 500 µA Sleep mode: 74 µA Shutdown mode: 2.9 µA Dynamic power scaling Turn-on time from shutdown mode: 1.5 µs Turn-on time from sleep mode: 0.45 µs High speed performance with dc precision Input offset voltage: 125 µV maximum Input offset voltage drift: 1.5 µV/°C maximum −3 dB bandwidth: 105 MHz Slew rate: 160 V/ µs Low noise and distortion 5.9 nV/√Hz input voltage noise with 8 Hz 1/f corner −102 dBc/−126 dBc HD2/HD3 at 100 kHz Wide supply range: 2.7 V to 10 V Small package: 8-lead SOT-23 13391-611 Data Sheet 0.2 µV/°C Offset Drift, 105 MHz, Low Power, Multimode, Rail-to-Rail Amplifier ADA4806-1 ADC Power (mW) 4.0 7.0 10.5 Throughput (MSPS) 1 1 1.33 Resolution (Bits) 16 18 18 SNR (dB) 90.51 98 98.5 This SNR value is for the A Grade version of the AD7980. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4806-1* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Design Resources View a parametric search of comparable parts • ADA4806-1 Evaluation Board • • • • Documentation Discussions Data Sheet • ADA4806-1: 0.2 μV/°C Offset Drift, 105 MHz, Low Power, Multimode, Rail-to-Rail Amplifier Data Sheet User Guides • UG-887: Evaluating the ADA4806-1 0.2 μV/°C Offset Drift, 105 MHz Low Power, Multimode, Rail-to-Rail Amplifier Offered in an 8-Lead SOT-23 View all ADA4806-1 EngineerZone Discussions Evaluation Kits Tools and Simulations ADA4806-1 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number • ADA4806-1 SPICE Macro-Model * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. ADA4806-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Amplifier Description................................................................ 18 Applications ....................................................................................... 1 Input Protection ......................................................................... 18 General Description ......................................................................... 1 Shutdown/Sleep Mode Operation............................................ 18 Typical Applications Circuit............................................................ 1 Noise Considerations ................................................................. 19 Revision History ............................................................................... 2 Applications Information .............................................................. 20 Specifications..................................................................................... 3 Slew Enhancement ..................................................................... 20 ±5 V Supply ................................................................................... 3 Effect of Feedback Resistor on Frequency Response ............ 20 5 V Supply...................................................................................... 4 Compensating Peaking in Large Signal Frequency Response... 20 3 V Supply...................................................................................... 6 Absolute Maximum Ratings............................................................ 8 Driving Low Power, High Resolution Successive Approximation Register (SAR) ADCs..................................... 20 Thermal Resistance ...................................................................... 8 Dynamic Power Scaling............................................................. 21 Maximum Power Dissipation ..................................................... 8 Single-Ended to Differential Conversion ................................... 23 ESD Caution .................................................................................. 8 Layout Considerations ............................................................... 23 Pin Configurations and Function Descriptions ........................... 9 Outline Dimensions ....................................................................... 24 Typical Performance Characteristics ........................................... 10 Ordering Guide .......................................................................... 24 Test Circuits ..................................................................................... 17 Theory of Operation ...................................................................... 18 REVISION HISTORY 9/15—Revision 0: Initial Version Rev. 0 | Page 2 of 24 Data Sheet ADA4806-1 SPECIFICATIONS ±5 V SUPPLY VS = ±5 V at TA = 25°C; RF = 0 Ω for G = +1; otherwise, RF = 1 kΩ; RL = 2 kΩ to ground; unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion, HD2/HD3 1 Input Voltage Noise Input Voltage Noise 1/f Corner Frequency 0.1 Hz to 10 Hz Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift 2 Input Bias Current (IB) Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Common Mode Differential Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio (CMRR) SHUTDOWN PIN SHUTDOWN Voltage Low High SHUTDOWN Current Low High Turn-Off Time Turn-On Time Test Conditions/Comments Min Typ Max Unit G = +1, VOUT = 0.02 V p-p G = +1, VOUT = 2 V p-p G = +1, VOUT = 0.02 V p-p G = +1, VOUT = 2 V step G = +2, VOUT = 4 V step G = +1, VOUT = 2 V step G = +2, VOUT = 4 V step 120 40 18 190 250 35 78 MHz MHz MHz V/µs V/µs ns ns fC = 20 kHz, VOUT = 2 V p-p fC = 100 kHz, VOUT = 2 V p-p fC = 20 kHz, VOUT = 4 V p-p, G = +1 fC = 100 kHz, VOUT = 4 V p-p, G = +1 fC = 20 kHz, VOUT = 4 V p-p, G = +2 fC = 100 kHz, VOUT = 4 V p-p, G = +2 f = 100 kHz −114/−140 −102/−128 −109/−143 −93/−130 −113/−142 −96/−130 5.2 8 44 0.7 dBc dBc dBc dBc dBc dBc nV/√Hz Hz nV rms pA/√Hz f = 100 kHz Full power mode Low power mode, SLEEP = −VS TMIN to TMAX, 4 σ Full power mode Low power mode, SLEEP = −VS VOUT = −4.0 V to +4.0 V 107 13 800 0.2 550 3 2.1 111 125 1.5 800 25 50 260 1 VIN, CM = −4.0 V to +4.0 V −5.1 103 Powered down Enabled Powered down Enabled 50% of SHUTDOWN to <10% of enabled quiescent current 50% of SHUTDOWN to >99% of final VOUT Rev. 0 | Page 3 of 24 −1.0 µV µV µV/°C nA nA nA dB 130 MΩ kΩ pF V dB <−1.3 >−0.9 V V +4 +0.2 0.02 1.25 1.0 2.75 µA µA µs 1 3 µs ADA4806-1 Parameter SLEEP PIN SLEEP Voltage Low High SLEEP Current Low High Turn-Off Time (Full Power Mode to Sleep Mode) Turn-On Time (Sleep Mode to Full Power Mode) OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing Short-Circuit Current Linear Output Current Off Isolation Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio (PSRR) Positive Negative 1 2 Data Sheet Test Conditions/Comments Min Powered down Enabled Low Power Mode, SLEEP = −VS Enabled 50% of SLEEP to 30% of enabled quiescent current 50% of SLEEP to >99% of final VOUT −1.0 V V 1.0 240 µA µA ns 450 600 ns 95/100 −4.98 Full power mode Low power mode, SLEEP = −VS SHUTDOWN = −VS ns 85/73 1.4/1.8 ±58 +4.98 V mA mA mA 41 15 dB pF 570 85 7.4 100 100 Unit +0.2 0.02 180 2.7 +VS = +3 V to +5 V, −VS = −5 V +VS = +5 V, −VS = −3 V to −5 V Max <−1.3 >−0.9 VIN = +6 V to −6 V, G = +2 RL = 2 kΩ Sourcing/sinking; full power mode Sourcing/sinking; low power mode, SLEEP = −VS <1% total harmonic distortion (THD) at 100 kHz, VOUT = 2 V p-p VIN = 0.5 V p-p, f = 1 MHz, SHUTDOWN = −VS 30% overshoot Typ 10 625 12 119 122 V µA µA µA dB dB fC is the fundamental frequency. Guaranteed, but not tested. 5 V SUPPLY VS = 5 V at TA = 25°C; RF = 0 Ω for G = +1; otherwise, RF = 1 kΩ; RL = 2 kΩ to midsupply; unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Test Conditions/Comments G = +1, VOUT = 0.02 V p-p G = +1, VOUT = 2 V p-p G = +1, VOUT = 0.02 V p-p G = +1, VOUT = 2 V step G = +2, VOUT = 4 V step G = +1, VOUT = 2 V step G = +2, VOUT = 4 V step Rev. 0 | Page 4 of 24 Min Typ 105 35 20 160 220 35 82 Max Unit MHz MHz MHz V/µs V/µs ns ns Data Sheet Parameter NOISE/DISTORTION PERFORMANCE Harmonic Distortion, HD2/HD3 1 Input Voltage Noise Input Voltage Noise 1/f Corner 0.1 Hz to 10 Hz Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift 2 Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Common Mode Differential Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio SHUTDOWN PIN SHUTDOWN Voltage Low High SHUTDOWN Current Low High Turn-Off Time Turn-On Time SLEEP PIN SLEEP Voltage Low High SLEEP Current Low High Turn-Off Time (Full Power Mode to Sleep Mode) Turn-On Time (Sleep Mode to Full Power Mode) ADA4806-1 Test Conditions/Comments Min fC = 20 kHz, VOUT = 2 V p-p fC = 100 kHz, VOUT = 2 V p-p fC = 20 kHz, G = +2, VOUT = 4 V p-p fC = 100 kHz, G = +2, VOUT = 4 V p-p f = 100 kHz Max −114/−135 −102/−126 −107/−143 −90/−130 5.9 8 54 0.6 f = 100 kHz Full power mode Low power mode, SLEEP = −VS TMIN to TMAX, 4 σ Full power mode Low power mode, SLEEP = −VS VOUT = 1.25 V to 3.75 V Typ 105 10 500 0.2 470 3 0.4 109 dBc dBc dBc dBc nV/√Hz Hz nV rms pA/√Hz 125 1.5 720 50 260 1 VIN, CM = 1.25 V to 3.75 V −0.1 103 Powered down Enabled Powered down Enabled 50% of SHUTDOWN to <10% of enabled quiescent current 50% of SHUTDOWN to >99% of final VOUT −1.0 Powered down Enabled Low power mode, SLEEP = −VS Enabled 50% of SLEEP to 30% of enabled quiescent current 50% of SLEEP to >99% of final VOUT Rev. 0 | Page 5 of 24 µV µV µV/°C nA nA nA dB 133 MΩ kΩ pF V dB <1.5 >1.9 V V +4 +0.1 0.01 0.9 1.0 1.25 µA µA µs 1.5 4 µs <1.5 >1.9 −1.0 Unit V V +0.1 0.01 150 1.0 185 µA µA ns 450 600 ns ADA4806-1 Parameter OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing Short-Circuit Current Linear Output Current Off Isolation Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio Positive Negative 1 2 Data Sheet Test Conditions/Comments Min VIN = −1 V to +6 V, G = +2 RL = 2 kΩ Sourcing/sinking; full power mode Sourcing/sinking; low power mode, SLEEP = −VS <1% THD at 100 kHz, VOUT = 2 V p-p VIN = 0.5 V p-p, f = 1 MHz, SHUTDOWN = −VS 30% overshoot Typ 130/145 0.02 2.7 500 74 2.9 100 100 Unit ns 4.98 V mA mA mA dB pF 10 520 V µA µA µA 73/63 1.0/1.3 ±47 41 15 Full power mode Low power mode, SLEEP = −VS SHUTDOWN = −VS +VS = 1.5 V to 3.5 V, −VS = −2.5 V +VS = 2.5 V, −VS = −1.5 V to −3.5 V Max 4 120 126 dB dB fC is the fundamental frequency. Guaranteed, but not tested. 3 V SUPPLY VS = 3 V at TA = 25°C; RF = 0 Ω for G = +1; otherwise, RF = 1 kΩ; RL = 2 kΩ to midsupply; unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Harmonic Distortion, HD2/HD3 1 Input Voltage Noise Input Voltage Noise 1/f Corner 0.1 Hz to 10 Hz Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift 2 Input Bias Current Input Offset Current Open-Loop Gain Test Conditions/Comments Min Typ Max Unit G = +1, VOUT = 0.02 V p-p G = +1, VOUT = 1 V p-p, +VS = 2 V, −VS = −1 V G = +1, VOUT = 0.02 V p-p G = +1, VOUT = 1 V step, +VS = 2 V, −VS = −1 V G = +1, VOUT = 1 V step 95 30 35 85 41 MHz MHz MHz V/µs ns fC = 20 kHz, VOUT = 1 V p-p, +VS = 2 V, −VS = −1 V fC = 100 kHz, VOUT = 1 V p-p, +VS = 2 V, −VS = −1 V f = 100 kHz −123/−143 −107/−133 6.3 8 55 0.8 dBc dBc nV/√Hz Hz nV rms pA/√Hz f = 100 kHz Full power mode Low power mode, SLEEP = −VS TMIN to TMAX, 4 σ Full power mode Low power mode, SLEEP = −VS VOUT = 1.1 V to 1.9 V Rev. 0 | Page 6 of 24 100 7 300 0.2 440 3 0.5 107 125 1.5 690 µV µV µV/°C nA nA nA dB Data Sheet Parameter INPUT CHARACTERISTICS Input Resistance Common Mode Differential Mode Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio SHUTDOWN PIN SHUTDOWN Voltage Low High SHUTDOWN Current Low High Turn-Off Time Turn-On Time SLEEP PIN SLEEP Voltage Low High SLEEP Current Low High Turn-Off Time (Full Power Mode to Sleep Mode) Turn-On Time (Sleep Mode to Full Power Mode) OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing Short-Circuit Current Linear Output Current Off Isolation Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio Positive Negative 1 2 ADA4806-1 Test Conditions/Comments Min Typ Max 50 260 1 VIN, CM = 0.5 V to 2 V −0.1 89 Powered down Enabled Powered down Enabled 50% of SHUTDOWN to <10% of enabled quiescent current 50% of SHUTDOWN to >99% of final VOUT −1.0 Powered down Enabled Low Power Mode, SLEEP = −VS Enabled 50% of SLEEP to 30% of enabled quiescent current 50% of SLEEP to >99% of final VOUT VIN = −1 V to +4 V, G = +2 RL = 2 kΩ Sourcing/sinking; full power mode Sourcing/sinking; low power mode, SLEEP = −VS <1% THD at 100 kHz, VOUT = 1 V p-p VIN = 0.5 V p-p, f = 1 MHz, SHUTDOWN = −VS 30% overshoot 117 MΩ kΩ pF V dB <0.7 >1.1 V V +2 +0.1 0.01 0.9 1.0 1.25 µA µA µs 2.5 8 µs <0.7 >1.1 −1.0 +0.1 0.01 155 450 0.02 fC is the fundamental frequency. Guaranteed, but not tested. Rev. 0 | Page 7 of 24 1.0 210 600 470 70 1.3 96 96 119 125 µA µA ns ns ns 2.98 V mA mA mA dB pF 10 495 V µA µA µA 65/47 1.0/1.3 ±40 41 15 2.7 +VS = 1.5 V to 3.5 V, −VS = −1.5 V +VS = 1.5 V, −VS = −1.5 V to −3.5 V V V 135/175 Full power mode Low power mode, SLEEP = −VS SHUTDOWN = −VS Unit 3 dB dB ADA4806-1 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 11 V See Figure 3 −VS − 0.7 V to +VS + 0.7 V ±1 V −65°C to +125°C −40°C to +125°C 300°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst case conditions, that is, θJA is specified for a device soldered in a circuit board for surface-mount packages. Table 6 lists the θJA for the ADA4806-1. The quiescent power dissipation is the voltage between the supply pins (VS) multiplied by the quiescent current (IS). PD = Quiescent Power + (Total Drive Power − Load Power) V V PD = (VS × I S ) + S × OUT RL 2 RMS output voltages must be considered. If RL is referenced to −VS, as in single-supply operation, the total drive power is VS × IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. PD = (VS × I S ) + (VS / 4)2 RL In single-supply operation with RL referenced to −VS, the worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing θJA. Additionally, more metal directly in contact with the package leads and exposed pad from metal traces, through holes, ground, and power planes reduces θJA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature on a JEDEC standard, 4-layer board. θJA values are approximations. Table 6. Thermal Resistance 1.0 Unit °C/W TJ = 150°C 0.9 MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the ADA4806-1 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4806-1. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4806-1 output load drive. 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –50 –30 –10 10 30 50 70 90 AMBIENT TEMPERATURE (°C) 110 130 13391-600 θJA 209.1 MAXIMUM POWER DISSIPATION (W) Package Type 8-Lead SOT-23 VOUT 2 − RL Figure 3. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board ESD CAUTION Rev. 0 | Page 8 of 24 Data Sheet ADA4806-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOUT 1 8 +VS NC 2 7 SHUTDOWN –VS 3 6 SLEEP +IN 4 5 –IN 13391-002 ADA4806-1 NOTES 1. NC = NO CONNECTION. DO NOT CONNECT TO THIS PIN. Figure 4. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VOUT NC −VS +IN −IN SLEEP SHUTDOWN +VS Description Output. No Connection. Do not connect to this pin. Negative Supply. Noninverting Input. Inverting Input. Low Power Mode. Power-Down Mode. Positive Supply. Rev. 0 | Page 9 of 24 ADA4806-1 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS RL = 2 kΩ, unless otherwise noted. When G = +1, RF = 0 Ω. 3 G = +2 NORMALIZED CLOSED-LOOP GAIN (dB) 0 G = +1 G = +10 –3 G = +5 –6 G = +2 –9 VS = ±2.5V VOUT = 20mV p-p RL = 2kΩ RF = 1kΩ –12 0.1 1 10 1000 100 FREQUENCY (MHz) 0 G = +5 –3 –6 –9 G = +10 VS = ±2.5V VOUT = 2V p-p RF = 1kΩ RL = 2kΩ –12 0.1 13391-206 NORMALIZED CLOSED-LOOP GAIN (dB) G = +1 1 100 10 FREQUENCY (MHz) Figure 5. Small Signal Frequency Response for Various Gains Figure 8. Large Signal Frequency Response for Various Gains 3 3 13391-015 3 –40°C –40°C +25°C CLOSED-LOOP GAIN (dB) +25°C –3 +125°C –6 –12 0.1 +125°C –3 –6 VS = ±2.5V G = +1 VOUT = 2V p-p RL = 2kΩ VS = ±2.5V G = +1 VOUT = 20mV p-p RL = 2kΩ 1 0 10 100 1000 FREQUENCY (MHz) –9 0.1 Figure 6. Small Signal Frequency Response for Various Temperatures 1 10 100 FREQUENCY (MHz) 13391-016 –9 13391-208 CLOSED-LOOP GAIN (dB) 0 Figure 9. Large Signal Frequency Response for Various Temperatures 3 3 VS = ±5V VOUT = 0.5V p-p VS = ±2.5V VOUT = 20mV p-p CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 0 VS = ±1.5V –3 –6 0 VOUT = 2V p-p –3 –9 10 FREQUENCY (MHz) 100 1000 Figure 7. Small Signal Frequency Response for Various Supply Voltages Rev. 0 | Page 10 of 24 –6 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 10. Frequency Response for Various Output Voltages 13391-211 1 13391-207 –12 0.1 VOUT = 100mV p-p VS = ±2.5V G = +1 RL = 2kΩ G = +1 VOUT = 20mV p-p RL = 2kΩ Data Sheet ADA4806-1 0.6 12 VS = ±2.5V G = +1 RL = 2kΩ VOUT = 20mV p-p 0.4 CL = 10pF 6 CL = 5pF 3 CL = 0pF 0 CL = 15pF RS = 226Ω –3 VS = ±2.5V G = +1 RL = 2kΩ VOUT = 20mV p-p 0.5 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 9 CL = 15pF –6 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –9 10 –0.6 13391-309 1 100 FREQUENCY (MHz) 1 10 Figure 11. Small Signal Frequency Response for Various Capacitive Loads (See Figure 47) Figure 14. Small Signal 0.1 dB Bandwidth –50 –50 –60 –70 HD2, G = +1 HD2 VS = ±5V –80 DISTORTION (dBc) HD2, G = +2 –90 –100 –110 –120 HD3, G = +2 –130 –90 –100 –110 HD2 VS = +2V/–1V –120 HD2 VS = ±2.5V –130 –140 –140 –150 –150 HD3 VS = +2V/–1V HD3 VS = ±2.5V HD3 VS = ±5V HD3, G = +1 10 100 1000 –160 FREQUENCY (kHz) Figure 12. Distortion vs. Frequency for Various Gains TOTAL HARMONIC DISTORTION (dB) –50 –60 VS = ±2.5V VIN, CM = 0V G = +1 RL = 2kΩ –70 –50 INPUT COMMON-MODE VOLTAGE UPPER LIMIT (+VS – 1V) 1000 HD2 VS = ±5V –70 HD2 VS = ±2.5V –80 –80 –90 VIN = 100kHz –110 –90 –100 HD2 VS = +2V/–1V –110 –120 –130 –120 VIN = 10kHz HD3 VS = +2V/–1V –140 –130 HD3 VS = ±2.5V –150 0.50 0.75 1.00 1.25 1.50 OUTPUT VOLTAGE (V peak) 1.75 2.00 13391-316 –140 0.25 100 FREQUENCY (kHz) VS = ±5V, VOUT = 4V p-p VS = ±2.5V, VOUT = 4V p-p VS = +2V/–1V, VOUT = 1V p-p –60 VIN = 1MHz –100 10 Figure 15. Distortion vs. Frequency for Various Supplies, G = +1 DISTORTION (dBc) –40 1 Figure 13. Total Harmonic Distortion vs. Output Voltage For Various Frequencies Rev. 0 | Page 11 of 24 –160 HD3 VS = ±5V 1 10 100 FREQUENCY (kHz) Figure 16. Distortion vs. Frequency, G = +2 1000 13391-518 1 13391-514 –160 13391-517 –80 DISTORTION (dBc) VS = ±5V, VOUT = 2V p-p VS = ±2.5V, VOUT = 2V p-p VS = +2V/–1V, VOUT = 1V p-p VS = ±5V, VOUT = 4V p-p –60 –70 100 FREQUENCY (MHz) 13391-110 –0.5 –12 ADA4806-1 Data Sheet 90 12 VS = ±2.5V G = +1 80 VS = ±2.5V G = +1 CURRENT NOISE (pA/√Hz) VOLTAGE NOISE (nV/√Hz) 10 70 60 50 40 30 20 8 6 4 2 10 1 1k 100 10k 1M 100k 10M 100M FREQUENCY (Hz) 0 13391-219 0 0.1 1 10 10k 1k 100k 1M 10M FREQUENCY (Hz) Figure 17. Voltage Noise vs. Frequency Figure 20. Current Noise vs. Frequency (See Figure 48) 300 –10 VS = ±2.5V 250 AVERAGE NOISE = 54nV rms VS = ±2.5V G = +1 RL = 2kΩ VIN = 0.5 Vp-p SHUTDOWN = –VS SLEEP = –VS –20 200 150 –30 100 ISOLATION (dB) AMPLITUDE (nV) 100 13391-018 10 50 0 –50 –100 –40 –50 –60 –150 –70 –200 –80 0 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) –90 0.01 13391-318 –300 100 0.3 VS = +5V G = +1 VOUT = 2V STEP RL = 2kΩ VS = ±2.5V ΔVS, ΔVCM = 100mV p-p 0.2 –20 –PSRR –40 –60 CMRR –80 0.1 0 –0.1 +PSRR –100 –0.2 –140 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M –0.3 0 20 40 60 80 100 120 140 TIME (ns) Figure 22. Settling Time to 0.1% Figure 19. CMRR, PSRR vs. Frequency Rev. 0 | Page 12 of 24 160 180 13391-030 –120 13391-232 CMRR, PSRR (dB) 10 Figure 21. Forward Isolation vs. Frequency SETTLING (%) 0 1 FREQUENCY (MHz) Figure 18. 0.1 Hz to 10 Hz Voltage Noise 20 0.1 13391-601 –250 Data Sheet ADA4806-1 35 4500 VS = ±2.5V = 9.8µV σ = 19.5µV 4000 VS = ±2.5V T = –40°C TO +125°C = –0.19µV/°C σ = 0.28µV/°C 30 3500 NUMBER OF UNITS 25 UNITS (%) 3000 2500 2000 20 15 1500 10 1000 5 60 30 –30 0 –60 INPUT OFFSET VOLTAGE (µV) –90 90 120 0 13391-613 0 –120 –1.6 1.2 0.8 1.6 Figure 26. Input Offset Voltage Drift Distribution 100 150 VS = ±2.5V 10 UNITS VS = ±2.5V 30 UNITS 100 60 INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV) 0.4 0 –0.4 INPUT OFFSET VOLTAGE DRIFT (µV/°C) Figure 23. Input Offset Voltage Distribution 80 –0.8 –1.2 13391-323 500 40 20 0 –20 –40 –60 50 0 –50 –100 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 INPUT COMMON-MODE VOLTAGE (V) –150 –40 13391-327 –25 20 35 50 65 80 95 110 6 –400 630 VS = ±5V 610 125 Figure 27. Input Offset Voltage vs. Temperature 650 IB– –450 4 590 INPUT BIAS CURRENT (nA) 570 550 530 510 VS = ±2.5V 490 470 450 –500 IB+ 2 –550 INPUT OFFSET CURRENT 0 –600 –650 –2 –700 VS = ±1.5V 430 –4 –750 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 13391-257 410 –800 –0.4 –6 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 INPUT COMMON-MODE VOLTAGE (V) Figure 28. Input Bias Current and Input Offset Current vs. Input Common-Mode Voltage Figure 25. Input Bias Current vs. Temperature for Various Supplies (See Figure 49) Rev. 0 | Page 13 of 24 13391-135 INPUT BIAS CURRENT (nA) 5 TEMPERATURE (°C) Figure 24. Input Offset Voltage vs. Input Common-Mode Voltage 390 –40 –10 INPUT OFFSET CURRENT (nA) –100 –3.0 13391-013 –80 ADA4806-1 Data Sheet 15 1.5 G = +1 VOUT = 20mV p-p VS = ±5V, VIN, CM = 0V, VOUT = 2V p-p G = +1 VS = ±2.5V, VIN, CM = 0V, VOUT = 2V p-p 10 1.0 OUTPUT VOLTAGE (V) 5 0 –5 VS = ±1.5V –10 0.5 0 –0.5 –1.0 50 100 150 200 250 300 TIME (ns) 13391-024 0 –1.5 0 VOUT 0 –1 –2 –3 300 350 VS = ±2.5V G = +2 3 2 VOUT 1 0 –1 –2 –3 –4 0 100 200 300 400 500 600 TIME (ns) 700 800 900 1000 13391-128 –4 250 2×VIN 4 2 1 200 5 INPUT AND OUTPUT VOLTAGE (V) INPUT AND OUTPUT VOLTAGE (V) 3 150 Figure 32. Large Signal Transient Response for Various Supplies VS = ±2.5V G = +1 VIN 100 TIME (ns) Figure 29. Small Signal Transient Response for Various Supplies 4 50 13391-025 VS = ±1.5V, VIN, CM = –0.5V, VOUT = 1V p-p VS = ±5V –15 –5 0 100 200 300 400 500 600 TIME (ns) 700 800 900 1000 13391-129 OUTPUT VOLTAGE (mV) VS = ±2.5V Figure 33. Output Overdrive Recovery Time Figure 30. Input Overdrive Recovery Time 0.8 0.8 0.7 0.7 +125°C 0.6 OUTPUT VOLTAGE (V) 0.5 +25°C 0.4 –40°C 0.3 0.2 –0.1 –0.5 0 0.5 1.0 TIME (µs) 1.5 0.4 +25°C 0.3 –40°C 0.2 0.1 VS = ±2.5V G = +1 RL = 2kΩ 0 +125°C 0.5 VS = ±2.5V G = +1 RL = 2kΩ 0 2.0 –0.1 –0.25 Figure 31. Turn-On Response Time from Shutdown for Various Temperatures (See Figure 50) 0 0.25 TIME (µs) 0.50 0.75 13391-605 0.1 13391-602 OUTPUT VOLTAGE (V) 0.6 Figure 34. Turn-On Response Time from Sleep for Various Temperatures (See Figure 50) Rev. 0 | Page 14 of 24 Data Sheet ADA4806-1 800 800 700 +125°C +125°C 700 G = +1 RL = 2kΩ 600 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) VS = ±2.5V VS = ±2.5V G = +1 RL = 2kΩ 500 +25°C 400 300 –40°C 200 100 600 500 400 300 +25°C 200 100 1 0 2 3 4 5 6 TIME (µs) 0 –1 13391-258 –1 Figure 35. Turn-Off Response Time to Shutdown for Various Temperatures (See Figure 51) 4 5 6 0.7 VS = ±5V VS = ±5V 0.6 OUTPUT VOLTAGE (V) 0.6 0.5 0.4 VS = +2/–1V 0.3 0.2 VS = ±2.5V VS = ±2.5V 0.5 0.4 0.3 VS = +2V/–1V 0.2 0.1 0 0 1 TIME (µs) 2 3 –0.1 –0.25 13391-603 –0.1 –1 G = +1 RL = 2kΩ 0 G = +1 RL = 2kΩ 0 0.25 0.5 0.75 TIME (µs) Figure 36. Turn-On Response Time from Shutdown for Various Supplies 13391-608 0.1 Figure 39. Turn-On Response Time from Sleep for Various Supplies 800 800 G = +1 RL = 2kΩ 700 700 VS = ±5V SUPPLY CURRENT (µA) 600 VS = ±2.5V 500 400 VS = ±1.5V 300 200 100 G = +1 RL = 2kΩ VS = ±5V 600 VS = ±2.5V 500 400 VS = ±1.5V 300 200 –1 0 1 2 3 TIME (µs) 4 5 6 13391-242 100 0 –1 Figure 37. Turn-Off Response Time to Shutdown for Various Supplies Rev. 0 | Page 15 of 24 0 1 2 3 TIME (µs) 4 5 6 Figure 40. Turn-Off Response Time to Sleep for Various Supplies 13391-609 OUTPUT VOLTAGE (V) 2 3 TIME (µs) 0.8 0.7 SUPPLY CURRENT (µA) 1 Figure 38. Turn-Off Response Time to Sleep for Various Temperatures (See Figure 51) 0.8 0 0 13391-607 –40°C 0 Data Sheet 800 140 750 130 QUIESCENT SUPPLY CURRENT (µA) 700 650 600 VS = ±5V 550 500 VS = ±1.5V 450 VS = ±2.5V 400 120 110 100 80 70 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 40 –40 13391-256 –25 Figure 41. Quiescent Supply Current vs. Temperature 3.5 3.5 OUTPUT CURRENT (mA) 4.0 –40°C 2.5 +125°C +25°C 2.0 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 1.5 1.0 VS = ±5.0V VS = ±2.5V 3.0 2.5 VS = ±1.5V 2.0 1.5 1.0 Figure 42. SHUTDOWN and SLEEP Threshold vs. Supply Voltage from Ground for Various Temperatures 2 5 65 20 35 50 TEMPERATURE (°C) 80 95 120 25.0 –20 100 –1 23.5 –2 23.0 –3 22.5 –4 200 400 600 800 1000 1200 TIME (Hours) 1400 OPEN-LOOP GAIN (dB) 24.0 –40 80 –60 60 –80 –100 PHASE 40 –120 20 –140 22.0 0 21.5 –20 10 13391-542 0 TEMPERATURE (°C) 24.5 OIL BATH TEMPERATURE 125 0 GAIN 1 110 Figure 45. Sleep Mode Output Current vs. Temperature 25.5 VS = ±2.5V 6 UNITS, SOLDERED TO PCB –10 Figure 43. Long-Term VOS Drift –160 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 46. Open-Loop Gain and Phase Margin Rev. 0 | Page 16 of 24 OPEN-LOOP PHASE (Degrees) 3 –25 13391-604 0 –40 13391-236 SUPPLY VOLTAGE FROM GROUND (V) 0 125 0.5 0.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 –5 110 Figure 44. Sleep Mode Quiescent Supply Current vs. Temperature 4.0 3.0 –25 13391-606 50 300 –40 SHUTDOWN AND SLEEP THRESHOLD (V) VS = ±1.5V 60 350 CHANGE IN INPUT OFFSET VOLTAGE (µV) VS = ±2.5V VS = ±5.0V 90 –180 100M 13391-026 QUIESCENT SUPPLY CURRENT (µA) ADA4806-1 Data Sheet ADA4806-1 TEST CIRCUITS SHUTDOWN OR SLEEP +2.5V VOUT +2.5V –2.5V 50Ω VOUT CL 2kΩ 0.5V 2kΩ –2.5V + 5V – 13391-404 VIN 20mV p-p 13391-401 RS –2.5V Figure 47. Output Capacitive Load Behavior Test Circuit (See Figure 11) Figure 50. Turn-On Response Test Circuit (See Figure 31 and Figure 34) +2.5V IS SHUTDOWN OR SLEEP +2.5V VOUT VOUT 2kΩ –2.5V + 5V – –2.5V Figure 48. Current Noise Test Circuit (See Figure 20) Figure 51. Turn-Off Response Test Circuit (See Figure 35 and Figure 38) 13391-403 IB+ IB – 13391-405 –2.5V 13391-402 75kΩ Figure 49. Input Bias Current Temperature Test Circuit (See Figure 25) Rev. 0 | Page 17 of 24 ADA4806-1 Data Sheet THEORY OF OPERATION AMPLIFIER DESCRIPTION The ADA4806-1 has a bandwidth of 105 MHz and a slew rate of 160 V/µs. It has an input referred voltage noise of only 5.9 nV/√Hz. The ADA4806-1 operates over a supply voltage range of 2.7 V to 10 V and consumes only 500 µA of supply current at VS = 5 V. The low end of the supply range allows −10% variation of a 3 V supply. The amplifier is unity-gain stable, and the input structure results in an extremely low input 1/f noise. The ADA4806-1 uses a slew enhancement architecture, as shown in Figure 52. The slew enhancement circuit detects the absolute difference between the two inputs. It then modulates the tail current, ITAIL, of the input stage to boost the slew rate. The architecture allows a higher slew rate and fast settling time with low quiescent current while maintaining low noise. SLEW ENHANCEMENT CIRCUIT +VS ITAIL TO DETECT ABSOLUTE VALUE VIN+ VIN– +IN 13391-255 –IN INPUT STAGE Figure 52. Slew Enhancement Circuit INPUT PROTECTION The ADA4806-1 is fully protected from ESD events, withstanding human body model ESD events of ±3.5 kV and charged device model events of ±1.25 kV with no measured performance degradation. The precision input is protected with an ESD network between the power supplies and diode clamps across the input device pair, as shown in Figure 53. For differential voltages above approximately 1.2 V at room temperature, and 0.8 V at 125°C, the diode clamps begin to conduct. If large differential voltages must be sustained across the input terminals, the current through the input clamps must be limited to less than 10 mA. Series input resistors that are sized appropriately for the expected differential overvoltage provide the needed protection. The ESD clamps begin to conduct for input voltages that are more than 0.7 V above the positive supply and input voltages more than 0.7 V below the negative supply. If an overvoltage condition is expected, the input current must be limited to less than 10 mA. SHUTDOWN/SLEEP MODE OPERATION Figure 54 shows the ADA4806-1 shutdown circuitry. To maintain very low supply current in shutdown mode, no internal pull-up resistor is supplied; therefore, the SHUTDOWN pin must be driven high or low externally and must not be left floating. Pulling the SHUTDOWN pin to ≥1 V below midsupply turns the device off, reducing the supply current to 2.9 µA for a 5 V supply. When the amplifier is powered down, its output enters a high impedance state. The output impedance decreases as frequency increases. In shutdown mode, a forward isolation of −62 dB can be achieved at 100 kHz (see Figure 21). A second circuit similar to Figure 54 is used for sleep mode operation. Pulling the SLEEP pin low places the amplifier in a low power state, drawing only 74 µA from a 5 V supply. Leaving the amplifier biased on at a very low level greatly reduces the turnon time from sleep to full power mode, thus enabling dynamic power scaling of the ADA4806-1 at higher sample rates. The ADA4806-1 is not characterized for operation in sleep mode. +VS 2.2R 1.1V ESD +VS SHUTDOWN BIAS ESD –IN +IN ESD 1.8R ESD TO ENABLE AMPLIFIER –VS ESD 13391-006 ESD Figure 54. Shutdown/Sleep Equivalent Circuit TO THE REST OF THE AMPLIFIER 13391-005 –VS Figure 53. Input Stage and Protection Diodes The SHUTDOWN pin and the SLEEP pin are protected by ESD clamps, as shown in Figure 54. Voltages beyond the power supplies cause these diodes to conduct. To protect the SHUTDOWN and SLEEP pins, ensure that the voltage to these pins does not exceed 0.7 V above the positive supply or 0.7 V below the negative supply. If an overvoltage condition is expected, the input current must be limited to less than 10 mA with a series resistor. Rev. 0 | Page 18 of 24 Data Sheet ADA4806-1 The output noise spectral density is calculated by Table 8 summarizes the threshold voltages for the SHUTDOWN and SLEEP pins for various supplies. Table 9 shows the truth table for the SHUTDOWN and SLEEP pins. v n _ OUT = 2 R R 4kTR F + 1 + F 4kTRs + in+ 2 RS 2 + v n 2 + F R G RG Table 8. Threshold Voltages for Enabled Mode and Shutdown/Sleep Modes +3 V >+1.1 V <+0.7 V +5 V >+1.9 V <+1.5 V ±5 V >−0.9 V <−1.3 V +7 V/−2 V >+1.6 V <+1.2 V Table 9. Truth Table for the SHUTDOWN and SLEEP Pins SHUTDOWN SLEEP Low Low High High Low High Low High Operating State Powered down Powered down Low power mode Full power mode Figure 55 shows the primary noise contributors for the typical gain configurations. The total output noise (vn_OUT) is the root sum square of all the noise contributions. Vn_RF = 4kTRF Vn RG in– Vn_RS = 4kTRS RS in+ + Vn_OUT 13391-034 Vn_RG = 4kTRG 2 4kTRG + in− 2 R F 2 where: k is Boltzmann’s constant. T is the absolute temperature in degrees Kelvin. RF and RG are the feedback network resistances, as shown in Figure 55. RS is the source resistance, as shown in Figure 55. in+ and in− represent the amplifier input current noise spectral density in pA/√Hz. vn is the amplifier input voltage noise spectral density in nV/√Hz. Source resistance noise, amplifier input voltage noise (vn), and the voltage noise from the amplifier input current noise (in+ × RS) are all subject to the noise gain term (1 + RF/RG). NOISE CONSIDERATIONS RF ] Figure 56 shows the total referred to input (RTI) noise due to the amplifier vs. the source resistance. Note that with a 5.9 nV/√Hz input voltage noise and 0.6 pA/√Hz input current noise, the noise contributions of the amplifier are relatively small for source resistances from approximately 2.6 kΩ to 47 kΩ. The Analog Devices, Inc., silicon germanium (SiGe) bipolar process makes it possible to achieve a low noise of 5.9 nV/√Hz for the ADA4806-1. This noise is much improved compared to similar low power amplifiers with a supply current in the range of hundreds of microamperes. Figure 55. Noise Sources in Typical Connection 1000 RTI NOISE (nV/√Hz) TOTAL NOISE SOURCE RESISTANCE NOISE AMPLIFIER NOISE 100 10 SOURCE RESISTANCE = 47kΩ SOURCE RESISTANCE = 2.6kΩ 1 100 1k 10k 100k SOURCE RESISTANCE (Ω) Figure 56. RTI Noise vs. Source Resistance Rev. 0 | Page 19 of 24 1M 13391-051 Mode Enabled Shutdown/Sleep Mode [ ADA4806-1 Data Sheet APPLICATIONS INFORMATION SLEW ENHANCEMENT 5 The ADA4806-1 has an internal slew enhancement circuit that increases the slew rate as the feedback error voltage increases. This circuit allows the amplifier to settle a large step response faster, as shown in Figure 57. This is useful in ADC applications where multiple input signals are multiplexed. The impact of the slew enhancement can also be seen in the large signal frequency response, where larger input signals cause a slight increase in peaking, as shown in Figure 58. 4 NORMALIZED GAIN (dB) 3 1.5 0 –1 RF = 2.6kΩ, CF = 1pF –3 RF = 4.99kΩ, CF = 1pF 1M VOUT = 1V p-p 10M 100M FREQUENCY (Hz) 13391-106 –6 100k Figure 59. Peaking in Frequency Response at Selected RF Values COMPENSATING PEAKING IN LARGE SIGNAL FREQUENCY RESPONSE 0 –0.5 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) 13391-254 –1.0 At high frequency, the slew enhancement circuit can contribute to peaking in the large signal frequency response. Figure 59 shows the effect of a feedback capacitor on the small signal response, whereas Figure 60 shows that the same technique is effective for reducing peaking in the large signal response. 6 Figure 57. Step Response with Selected Output Steps 3 2 VS = ±2.5V G = +1 RL = 2kΩ NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) RF = 1kΩ –2 0 VIN = 2V p-p VIN = 200mV p-p VIN = 632mV p-p VIN = 400mV p-p –1 –2 VS = ±2.5V G = +2 RL = 2 kΩ VIN = 632mV p-p 0 –3 RF = 2.6kΩ, CF = 0pF RF = 1kΩ, CF = 0pF RF = 2.6kΩ, CF = 2.7pF RF = 1 kΩ, CF = 2 pF –6 –9 –3 –12 VIN = 100mV p-p –4 –15 100k –5 1M 10M 100M –6 100k 1M 10M FREQUENCY (Hz) 100M 13391-105 FREQUENCY (Hz) Figure 58. Peaking in Frequency Responses as Signal Level Changes, G = +1 EFFECT OF FEEDBACK RESISTOR ON FREQUENCY RESPONSE The amplifier input capacitance and feedback resistor form a pole that, for larger value feedback resistors, can reduce phase margin and contribute to peaking in the frequency response. Figure 59 shows the peaking for selected feedback resistors (RF) when the amplifier is configured in a gain of +2. Figure 59 also shows how peaking can be mitigated with the addition of a small value capacitor placed across the feedback resistor of the amplifier. 13391-107 OUTPUT VOLTAGE (V) 1 –5 VOUT = 500mV p-p 1 RF = 4.99kΩ 2 VOUT = 2V p-p 0.5 –1.5 RF = 2.6kΩ –4 VS = ±2.5V G = +1 RL = 2kΩ 1.0 VS = ±2.5V G = +2 RL = 2 kΩ VIN = 20mV p-p Figure 60. Peaking Mitigation in Large Signal Frequency Response DRIVING LOW POWER, HIGH RESOLUTION SUCCESSIVE APPROXIMATION REGISTER (SAR) ADCs The ADA4806-1 is ideal for driving low power, high resolution SAR ADCs. The 5.9 nV/√Hz input voltage noise and rail-to-rail output stage of the ADA4806-1 help minimize distortion at large output levels. With its low power of 500 µA, the amplifier consumes power that is compatible with low power SAR ADCs, which are usually in the microwatt (µW) to low milliwatt (mW) range. Furthermore, the ADA4806-1 supports a single-supply configuration; the input common-mode range extends to 0.1 V below the negative supply, and 1 V below the positive supply. Rev. 0 | Page 20 of 24 Data Sheet ADA4806-1 Figure 61 shows a typical 16-bit, single-supply application. The ADA4806-1 drives the AD7980, a 16-bit, 1 MSPS, SAR ADC in a low power configuration. The AD7980 operates on a 2.5 V supply and supports an input from 0 V to VREF. In this case, the ADR435 provides a 5 V reference. The ADA4806-1 is used both as a driver for the AD7980 and as a reference buffer for the ADR435. DYNAMIC POWER SCALING The low-pass filter formed by R3 and C1 reduces the noise to the input of the ADC (see Figure 61). In lower frequency applications, the designer can reduce the corner frequency of the filter to remove additional noise. Figure 62 illustrates a method by which the quiescent power of the ADC driver can be dynamically scaled with the sampling rate of the system. By providing properly timed signals to the convert input (CNV) pin of the ADC and the SHUTDOWN and SLEEP pins of the ADA4806-1, both devices can be run at optimum efficiency. +7.5V 5V REF ADA4806-1 VDD C2 10µF C4 100nF C3 0.1µF +5V +6V +2.5V 0.1µF VIN ADA4806-1 +7.5V ADA4806-1 R3 20Ω IN+ VDD AD7980 GND CNV AD7980 IN– C1 2.7nF REF VDD GND TIMING GENERATOR 13391-310 0V TO VREF REF 20Ω 2.7nF Figure 62. ADA4806-1/AD7980 Power Management Circuitry Figure 61. Driving the AD7980 with the ADA4806-1 In this configuration, the ADA4806-1 consume 7.2 mW of quiescent power. The measured signal-to-noise ratio (SNR), THD, and signal-to-noise-and-distortion ratio (SINAD) of the whole system for a 10 kHz signal are 89.4 dB, 104 dBc, and 89.3 dB, respectively. This translates to an effective number of bits (ENOB) of 14.5 at 10 kHz, which is compatible with the AD7980 performance. Table 10 shows the performance of this setup at selected input frequencies. Figure 63 illustrates the relative signal timing for power scaling the ADA4806-1 and the AD7980. To prevent any degradation in the performance of the ADC, the ADA4806-1 must have a fully settled output into the ADC before the activation of the CNV pin. The amplifier on-time (tAMP, ON) is the time the amplifier is enabled prior to the rising edge of the CNV signal; this time depends on whether the SHUTDOWN pin or SLEEP pin is being driven. In the example shown in Figure 64, tAMP, ON is 3 µs for the SHUTDOWN pin and 0.5 µs for the SLEEP pin. After a conversion, the SHUTDOWN pin and/or the SLEEP pin of the ADA4806-1 are pulled low when the ADC input is inactive in between samples. While in shutdown mode, the ADA4806-1 output impedance is high. Table 10. System Performance at Selected Input Frequencies for Driving the AD7980 Single-Ended Input Frequency (kHz) 1 10 20 50 100 ADC Driver Supply (V) Gain 7.5 1 7.5 1 7.5 1 7.5 1 7.5 1 13391-330 ADR435 One of the merits of a SAR ADC, like the AD7980, is that its power scales with the sampling rate. This power scaling makes SAR ADCs very power efficient, especially when running at a low sampling frequency. However, the ADC driver used with the SAR ADC traditionally consumes constant power regardless of the sampling frequency. Reference Buffer Supply (V) Gain 7.5 1 7.5 1 7.5 1 7.5 1 7.5 1 Rev. 0 | Page 21 of 24 SNR (dB) 89.8 89.4 89.9 88.5 86.3 Results THD (dBc) SINAD (dB) 103 89.6 104 89.3 103 89.7 99 88.1 93.7 85.6 ENOB 14.6 14.5 14.6 14.3 13.9 ADA4806-1 Data Sheet CNV SAMPLING PERIOD, tS ACQUISITION CONVERSION ACQUISITION CONVERSION ACQUISITION CONVERSION ADC POWERED ON ADA4806-1 SHUTDOWN/ SLEEP POWERED ON SHUTDOWN/SLEEP tAMP, ON SHUTDOWN/SLEEP tAMP, ON POWERED ON SHUTDOWN/SLEEP tAMP, ON IQ, ON tAMP, OFF tAMP, OFF 13391-329 ADA4806-1 QUIESCENT CURRENT tAMP, OFF Figure 63. Timing Waveforms (1) With power scaling, the quiescent power becomes proportional to the ratio between the amplifier on time, tAMP, ON, and the sampling time, tS: t PQ = I Q _ on × VS × AMP ,ON tS t −t + I Q _ off × VS × S AMP ,ON tS (2) Thus, by dynamically switching the ADA4806-1 between shutdown/sleep and full power modes between consecutive samples, the quiescent power of the driver scales with the sampling rate. CONTINUOUSLY ON 1.0 SLEEP MODE 0.1 AD7980 ADC SHUTDOWN MODE 0.01 0.01 0.1 1 10 ADC SAMPLE RATE (ksps) 100 1000 Figure 64. Quiescent Power Consumption of the ADA4806-1 vs. ADC Sample Rate, Using Dynamic Power Scaling Note that tAMP, ON in Figure 64 is 3 µs for the SHUTDOWN pin and 0.5 µs for the SLEEP pin. Rev. 0 | Page 22 of 24 13391-612 P Q = IQ × V S 10 QUIESCENT POWER CONSUMPTION (mW) Figure 64 shows the quiescent power of the ADA4806-1, operating from a single +6 V supply, without power scaling and while power scaling via the SHUTDOWN pin and the SLEEP pin. Without power scaling, the ADA4806-1 consumes constant power regardless of the sampling frequency, as shown in Equation 1. Data Sheet ADA4806-1 SINGLE-ENDED TO DIFFERENTIAL CONVERSION LAYOUT CONSIDERATIONS Most high resolution ADCs have differential inputs to reduce common-mode noise and harmonic distortion. Therefore, it is necessary to use an amplifier to convert a single-ended signal into a differential signal to drive the ADCs. To ensure optimal performance, careful and deliberate attention must be paid to the board layout, signal routing, power supply bypassing, and grounding. There are two common ways the user can convert a single-ended signal into a differential signal: either use a differential amplifier, or configure two amplifiers as shown in Figure 65. The use of a differential amplifier yields better performance, whereas the 2-op-amp solution results in lower system cost. The ADA4806-1 solves this dilemma of choosing between the two methods by combining the advantages of both. Its low harmonic distortion, low offset voltage, and low bias current mean that it can produce a differential output that is well matched with the performance of the high resolution ADCs. It is important to avoid ground in the areas under and around the input and output of the ADA4806-1. Stray capacitance between the ground plane and the input and output pads of a device is detrimental to high speed amplifier performance. Stray capacitance at the inverting input, together with the amplifier input capacitance, lowers the phase margin and can cause instability. Stray capacitance at the output creates a pole in the feedback loop, which can reduce phase margin and cause the circuit to become unstable. Ground Plane Power Supply Bypassing Figure 65 shows how the ADA4806-1 converts a single-ended signal into a differential output. The first amplifier is configured in a gain of +1 with its output then inverted to produce the complementary signal. The differential output then drives the AD7982, an 18-bit, 1 MSPS SAR ADC. To further reduce noise, the user can reduce the values of R1 and R2. However, note that this increases the power consumption. The low-pass filter of the ADC driver limits the noise to the ADC. Power supply bypassing is a critical aspect in the performance of the ADA4806-1. A parallel connection of capacitors from each power supply pin to ground works best. Smaller value ceramic capacitors offer better high frequency response, whereas larger value ceramic capacitors offer better low frequency performance. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins are provided with a low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier—especially when the amplifier PSRR begins to roll off—because the bypass capacitors can help lessen the degradation in PSRR performance. The measured SNR, THD, and SINAD of the whole system for a 10 kHz signal are 93 dB, 113 dBc, and 93 dB, respectively. This translates to an ENOB of 15.1 at 10 kHz, which is compatible with the performance of the AD7982. Table 11 shows the performance of this setup at selected input frequencies. Place the smallest value capacitor on the same side of the board as the amplifier and as close as possible to the amplifier power supply pins. Connect the ground end of the capacitor directly to the ground plane. Table 11. System Performance at Selected Input Frequencies for Driving the AD7982 Differentially THD (dBc) 104 113 110 102 96 Results SINAD (dB) 93 93 93 91 88 It is recommended that a 0.1 µF ceramic capacitor with a 0508 case size be used. The 0508 case size offers low series inductance and excellent high frequency performance. Place a 10 µF electrolytic capacitor in parallel with the 0.1 µF capacitor. Depending on the circuit parameters, some enhancement to performance can be realized by adding additional capacitors. Each circuit is different and must be analyzed individually for optimal performance. ENOB 15.1 15.1 15.1 14.8 14.3 VDD R3 22Ω R2 1kΩ +7.5V R1 1kΩ ADA4806-1 VIN +2.5V C1 0.1µF C2 2.7nF +7.5V IN+ REF IN– R4 22Ω ADA4806-1 C4 0.1µF +5V VDD AD7982 C3 2.7nF 13391-053 Input Frequency (kHz) 1 10 20 50 100 SNR (dB) 93 93 93 92 89 +2.5V Figure 65. Driving the AD7982 with the ADA4806-1 Rev. 0 | Page 23 of 24 ADA4806-1 Data Sheet OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 1.60 1.50 8 7 6 5 1 2 3 4 3.00 2.80 2.60 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.45 MAX 0.95 MIN 0.15 MAX 0.05 MIN 0.38 MAX 0.22 MIN 0.22 MAX 0.08 MIN SEATING PLANE 8° 4° 0° 0.60 BSC 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-BA 12-16-2008-A 1.30 1.15 0.90 Figure 66. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4806-1ARJZ-R2 ADA4806-1ARJZ-R7 ADA4806-1RJ-EBZ 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 8-Lead Small Outline Transistor Package [SOT-23] 8-Lead Small Outline Transistor Package [SOT-23] Evaluation Board for 8-Lead SOT-23 Z = RoHS Compliant Part. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13391-0-9/15(0) Rev. 0 | Page 24 of 24 Package Option RJ-8 RJ-8