Holt HI-8281PJI Arinc 429 line driver and dual receicer Datasheet

HI-8281
January 2001
GENERAL DESCRIPTION
FEATURES
The HI-8281 device from Holt Integrated Circuits is a silicon
gate CMOS device for interfacing a 16-bit parallel data bus
directly to the ARINC 429 serial bus. The device provides
two receivers, an independent transmitter and line driver
capability in a single package. The receiver input circuitry
and logic are designed to meet the ARINC 429
specifications for loading, level detection, timing, and
protocol. The transmitter section provides the ARINC 429
communication protocol and the line driver circuits provide
the ARINC 429 output levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit. The
HI-8281 examines the null and data timings and will reject
erroneous patterns. For example, with a 125 KHz clock
selection, the data frequency must be between 10.4 KHz
and 15.6 KHz.
! ARINC specification 429 compatible
! Direct receiver and transmitter interface to
ARINC bus in a single device.
! 16-Bit parallel data bus.
! Timing control 10 times the data rate
! Selectable data clocks
! Receiver error rejection per ARINC
specification 429
! Automatic transmitter data timing
! Self test mode
! Parity functions
! Low power
! Industrial & full military temperature ranges
PIN CONFIGURATION (Top View)
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.
APPLICATIONS
! Avionics data communication
! Serial to parallel conversion
! Parallel to serial conversion
(See page 4-27 for additional pin configuration)
(DS8281 Rev. A)
HOLT INTEGRATED CIRCUITS
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01/01
HI-8281
SIGNAL
FUNCTION
DESCRIPTION
VCC
POWER
+5V ±5%
V+
POWER
+12V ± 5% or +15V ± 10%
V-
POWER
429DI1 (A)
INPUT
ARINC receiver 1 positive input
-12V ± 5% or -15V ± 10%
429DI1 (B)
INPUT
ARINC receiver 1 negative input
429DI2 (A)
INPUT
ARINC receiver 2 positive input
429DI2 (B)
INPUT
ARINC receiver 2 negative input
D/R1
OUTPUT
D/R2
OUTPUT
SEL
INPUT
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
EN1
INPUT
Data Bus control, enables receiver 1 data to outputs
EN2
INPUT
Data Bus control, enables receiver 2 data to outputs if EN1 is high
BD15
I/O
Data Bus
BD14
I/O
Data Bus
BD13
I/O
Data Bus
BD12
I/O
Data Bus
Receiver 1 data ready flag
Receiver 2 data ready flag
BD11
I/O
Data Bus
BD10
I/O
Data Bus
BD09
I/O
Data Bus
BD08
I/O
Data Bus
BD07
I/O
Data Bus
BD06
I/O
GND
POWER
Data Bus
BD05
I/O
Data Bus
BD04
I/O
Data Bus
BD03
I/O
Data Bus
0 V - both pins must be connected
BD02
I/O
Data Bus
BD01
I/O
Data Bus
BD00
I/O
Data Bus
TX/R
OUTPUT
PL1
INPUT
Latch enable for byte 1 entered from data bus to transmitter FIFO.
PL2
INPUT
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
TXA(OUT)
OUTPUT
TXB(OUT)
OUTPUT
ENTX
INPUT
Enable Transmission
CWSTR
INPUT
Clock for control word register
Master Clock input
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
After transmission and FIFO empty.
Line driver output - A side
Line driver output - B side
CLK
INPUT
TX CLK
OUTPUT
MR
INPUT
Master Reset, active low
SLP1.5
INPUT
Logic input to control the slope of the differential output signal. HIGH = 1.5 µs
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
HOLT INTEGRATED CIRCUITS
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HI-8281
FUNCTIONAL DESCRIPTION
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
CONTROL WORD REGISTER
The HI-8282 contains 10 data flip flops whose D inputs are connected to the data bus and clocks connected to CWSTR. Each
flip flop provides options to the user as follows:
DATA
BUS
PIN
FUNCTION CONTROL
BDO5
SELF TEST
0 = ENABLE
DESCRIPTION
If enabled, an internal connection
is made passing 429DO and
429DO to the receiver logic inputs
BDO6
RECEIVER 1
DECODER
1 = ENABLE
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
BDO7
-
-
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
-
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
BDO8
-
BDO9
RECEIVER 2
DECODER
1 = ENABLE
If enabled, ARINC bits 9 and
10 must match the next two
control word bits
BD10
-
-
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
BD11
-
-
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
INVERT
XMTR
PARITY
1 = ENABLE
Logic 0 enables normal odd parity
and Logic 1 enables even parity
output in transmitter 32nd bit
BD13
XMTR DATA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain XMTR data clock
BD14
RCVR DTA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain RCVR data clock
BD12
BYTE 1
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC
BIT
13 12 11 10
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC
BIT
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
9
31 30 32
1
2
3
4
5
6
7
8
BYTE 2
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
The HI-8282 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±4V for the worst case
condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
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HI-8281
FUNCTIONAL DESCRIPTION (con't)
RECEIVER LOGIC OPERATION
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
HIGH SPEED
LOW SPEED
83K BPS
125K BPS
10.4K BPS
15.6K BPS
DATA BIT RATE MIN
DATA BIT RATE MAX
The ARINC 429 specification contains the following timing
specification for the received data:
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSEWIDTH
HIGH SPEED
LOW SPEED
100K BPS ± 1% 12K -14.5K BPS
1.5 ± 0.5 µsec
10 ± 5 µsec
1.5 ± 0.5 µsec
10 ± 5 µsec
5 µsec ± 5%
34.5 to 41.7 µsec
Again the HI-8282 accepts signals that meet these specifications
and rejects outside the tolerances. The way the logic operation
achieves this is described below:
1. Key to the performance of the timing checking logic is an accurate 1MHz clock source. Less than 0.1% error is recommended.
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally, for data bits, the One or Zero in the upper bits
of the sampling shift registers must be followed by a Null in the
lower bits within the data bit time. For a Null in the word gap,
three consecutive Nulls must be found in both the upper and
lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed.
4. TheWordGaptimersamplestheNullshiftregister every
10 input clocks (80 for low speed) after the last data bit of a
Valid reception. If the Null is present, theWordGapcounter
Is incremented. A count of 3 will enable the next reception.
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in
the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The
data flag for a receiver will remain low until after both ARINC bytes
from that receiver are retrieved. This is accomplished by
activating EN with SEL, the byte selector, low to retrieve the first
byte and activating EN with SEL high to retrieve the second byte.
ENI retrieves data from receiver 1 and EN2 retrieves data from
receiver 2.
If another ARINC word is received, and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
TO PINS
SEL
EN
MUX
CONTROL
32 TO 16 DRIVER
LATCH
ENABLE
CONTROL
32 BIT LATCH
CLOCK
OPTION
CONTROL
BIT BD14
D/R
DECODER
CONTROL
BITS
/
CLOCK
BITS 9 & 10
32 BIT SHIFT REGISTER
DATA
PARITY
CHECK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
BIT CLOCK
EOS
ONES
CLK
EOS
WORD GAP
WORD GAP
TIMER
SHIFT REGISTER
BIT CLOCK
END
START
NULL
SHIFT REGISTER
ZEROS
SHIFT REGISTER
FIGURE 2.
SEQUENCE
CONTROL
ERROR
ERROR
DETECTION
RECEIVER BLOCK DIAGRAM
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CLOCK
HI-8281
TRANSMITTER
TRANSMITTER PARITY
A block diagram of the transmitter section is shown in Figure 3.
The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will make
parity odd. If the control bit is high the parity is even.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or 429DO. The 31 bits in the
data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
SELF TEST
If the BD05 control word bit is set low, 429DO or 429DO become
inputs to the receiver bypassing the interface circuitry.
SYSTEMOPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges are strictly at the option of the user. The
only restrictions are:
1. The received data may be overwritten if not retrieved
within one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores
attempts to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first.
Both bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable ,goes high it cannot go
low until TX/R, transmitter readyflag, goes high. Otherwise,
one ARINC word is lost during transmission.
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HI-8281
LINE DRIVER OPERATION
REPEATER OPERATION
The line driver in the HI-8281 is designed to directly drive the ARINC
429 bus. The two ARINC outputs (TXA(OUT) and TXB(OUT))
provide a differential voltage to produce a +10 volt One, a -10 volt
Zero, and a 0 volt Null. The device incorporates on board zeners to
translate internal CMOS levels to ARINC specified amplitudes. A
logic input (SLP1.5) is provided to control the slope of the differential
output signal. No additional hardware is required to control the
slope. A HIGH on SLP1.5 causes a slope of 1.5 µs on the ARINC
outputs; a LOW on SLP1.5 causes a slope of 10 µs. Timing is set by
on-chip resistor and capacitor and tested to be within ARINC
requirements. The HI-8281 has 37.5 ohms in series with each line
driver output.
Repeater mode of operation allows a data word that has been
received by the HI-8281 to be placed directly into its FIFO for
transmission. Repeater operation is similar to normal receiver
operation. In normal operation, either byte of a received data
word may be read from the receiver latches first by use of SEL
input. During repeater operation however, the lower byte of the
data word must be read first. This is necessary because, as the
data is being read, it is also being loaded into the FIFO and the
transmitter FIFO is always loaded with the lower byte of the data
word first. Signal flow for repeater operation is shown in the
Timing Diagrams section.
TXA(OUT)
ARINC BIT
TXB(OUT)
DATA
NULL
DATA
DATA
NULL
BIT 1
NEXT WORD
WORD GAP
BIT 32
BIT 31
BIT 30
NULL
VALID
DATA BUS
tCWSET
t CWHLD
CWSTR
t CWSTR
t END/R
t D/R
t EN
t SELEN
tD/REN
tSELEN
tENSEL
tENEN
tDATAEN
t DATAEN
DATA BUS
tENDATA
HOLT INTEGRATED CIRCUITS
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tENSEL
t ENDATA
HI-8281
BYTE 2 VALID
BYTE 1 VALID
DATA BUS
tDWSET
tDWSET
tDWHLD
tDWHLD
PL1
tPL12
t PL
PL2
tPL12
t PL
tTX/R
TX/R
PL2
tDTX/R
tPL2EN
TX/R
t ENTX/R
ENTX
ARINC BIT
DATA
BIT 1
t ENDAT
ARINC BIT
DATA
BIT 2
ARINC BIT
DATA
BIT 32
+5V
+5V
TXA(OUT)
-5V
+5V
TXB(OUT)
-5V
-5V
tfx
+10V
+10V
90%
V
DIFF
(TXA(OUT) - TXB(OUT))
tfx
10%
trx
one level
trx
10%
zero level
90%
null level
-10V
HOLT INTEGRATED CIRCUITS
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HI-8281
429DI
BIT 32
t END/R
D/R
tD/R
tD/REN
t EN
t ENEN
t EN
EN
t SELEN
SEL
tENSEL
DON'T CARE
DON'T CARE
tENPL
tSELEN
tPLEN
t ENSEL
PL1
t PLEN
tENPL
PL2
tTX/R
TX/R
tTX/REN
tENTX/R
ENTX
t DTX/R
tENDAT
TXA(OUT)
TXB(OUT)
BIT 1
BIT 32
t NULL
HOLT INTEGRATED CIRCUITS
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HI-8281
Supply Voltages Vcc
V+
V-
-0.3V to +7V Power Dissipation at 25C
Plastic PLCC
20V
Ceramic J-LEAD CERQUAD
-20V
Voltage at pins 4, 5, 6 and 7
-29V to +29V DC Current Drain per pin
1.5 W, derate 10mW/°C
1.0 W, derate 7mW/°C
±10mA
-0.3 to V+ +0.3V Storage Temperature Range:
Voltage at pin 38
Voltage at any other pin
-0.3V to Vcc +0.3V Operating Temperature Range:
-65°C to +150°C
(Industrial)
(Military)
-40°C to +85°C
-55°C to +125°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Vcc = 5V ±5%, V+ = 12V to 15V, V- = -12V to -15V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
ARINC INPUTS
-
SYMBOL
CONDITIONS
VIH
VIL
VNUL
Pins 4 to 5, 6 to 7: Common
mode voltage less than ±4V
with respect to GND
LIMITS
MIN
TYP
MAX
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
27
27
UNIT
Pins 4, 5, 6 & 7
Differential Input Voltage:
ONE
ZERO
NULL
Input Resistance:
Input Current:
Differential
To GND
To Vcc
RI
RG
RH
12
12
12
Input Sink
Input Source
IIH
IIL
-450
Differential
To GND
To Vcc
CI
CG
CH
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
IIH
IIL
Input Capacitance:
(Guaranteed but not tested)
Pins 4 to 5, 6 to 7
V
V
V
K
K
K
200
µA
µA
20
20
20
pF
pF
pF
0.7
V
V
BI-DIRECTIONAL INPUTS - Pins 13 - 22, 24 - 29
Input Voltage:
Input Current:
2.1
1.5
-1.5
µA
µA
OTHER INPUTS - Pins 1, 8 - 12, 30, 31, 39, 40 & 43
Input Voltage:
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
IIH
IIL
-20
Input Voltage
Input Voltage HI
Input Voltage LO
VIH
VIL
2.1
-
Input Current
Input Sink
Input Source
IIH
IIL
Input Current:
3.5
0.7
V
V
10
µA
V+
0.5
V
V
0.1
0.1
µA
µA
INPUT - SLP1.5, PIN 38
VIN = 0V
VIN = 5V
HOLT INTEGRATED CIRCUITS
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-
HI-8281
Vcc = 5V ±5%, V+ = 12V to 15V, V- = -12V to -15V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
SYMBOL
CONDITIONS
ARINC output voltage
One or zero
Null
VDOUt
VNOUT
no load and magnitude at pin
ARINC output current
IOUT
MIN
TYP
MAX
4.50
-0.25
5.00
5.50
0.25
UNIT
ARINC OUTPUTS - Pins 35 & 36
"
"
"
"
"
"
80
V
V
mA
OTHER OUTPUTS - Pins 13-22, 24-29, 32 & 34
Output Voltage:
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -1.5mA
IOL = 1.8mA
2.7
Output Current:
(Bi-directional Pins)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VCC - 0.4V
3.0
1.5
mA
mA
Output Current:
(All Other Outputs)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VCC - 0.4V
3.6
1.5
mA
mA
Output Capacitance:
CO
0.4
15
V
V
pF
Operating Supply Current
VCC, Pin 3:
ICC1
20
mA
V+, Pin 37:
IDD1
16
mA
V-, Pin 34:
IEE1
16
mA
HOLT INTEGRATED CIRCUITS
10
HI-8281
Vcc = 5V, V+=12V to 15V, V- = -12V to -15V,GND = 0V, TA = Oper. Temp. Range and fclk = 1MHz +0.1% with 60/40 duty cycle
PARAMETER
LIMITS
SYMBOL
MIN
TYP
UNITS
MAX
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWSTR
tCWSET
tCWHLD
130
140
0
ns
ns
ns
RECEIVER TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
tD/R
tD/R
16
128
µs
µs
200
ns
ns
Delay - D/R LOW to EN L0W
Delay - EN LOW to D/R HIGH
tD/REN
tEND/R
0
Setup - SEL to EN L0W
Hold - SEL to EN HIGH
tSELEN
tENSEL
20
50
Delay - EN L0W to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN L0W
tEN
tENEN
240
50
ns
ns
tPL
200
ns
tDWSET
tDWHLD
110
20
ns
ns
Spacing - PL1 or PL2
tPL12
0
ns
Delay - PL2 HIGH to TX/R LOW
tTX/R
Spacing - PL2 HIGH to ENTX HIGH
tPL2EN
Delay - 32nd ARINC Bit to TX/R HIGH
tDTX/R
Spacing - TX/R HIGH to ENTX L0W
tENTX/R
ns
ns
200
30
ns
ns
FIFO TIMING
Pulse Width - PL1 or PL2
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
840
ns
TRANSMISSION TIMING
0
µs
400
0
ns
ns
LINE DRIVER OUTPUT TIMING
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed
Line driver transition differential times:
(High Speed, Pin 38 - Logic 1)
(Low Speed, Pin 38 = Logic 0)
tENDAT
tENDAT
27
216
µs
µs
high to low
low to high
tfx
trx
1.0
1.0
1.5
1.5
2.0
2.0
µs
µs
high to low
low to high
tfx
trx
5.0
5.0
10
10
15
15
µs
µs
HOLT INTEGRATED CIRCUITS
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HI-8281
Vcc = 5V, V+ = 12V to 15V, V- = -12V to -15V,GND = 0V, TA= Oper. Temp. Range and fclk = 1MHz +0.1% with 60/40 duty cycle
LIMITS
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
tENPL
0
ns
Hold - PL HIGH to EN HIGH
tPLEN
0
ns
tTX/REN
0
ns
tMR
400
ns
Delay - TX/R LOW to ENTX HIGH
Master Reset Pulse Width
ARINC Data Rate and Bit Timing
± 1%
HOLT INTEGRATED CIRCUITS
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HI-8281
ADDITIONAL HI-8281 PIN CONFIGURATION
(See page 4-23 for additional pin configuration)
ORDERING INFORMATION
PART
NUMBER
PACKAGE
DESCRIPTION
TEMPERATURE
RANGE
HI-8281PJI
44 PIN PLASTIC J LEAD
HI-8281PJT
FLOW
BURN
IN
LEAD
FINISH
-40°C TO +85°C
I
NO
SOLDER
44 PIN PLASTIC J LEAD
-55°C TO +125°C
T
NO
SOLDER
HI-8281CJI
44 PIN CERQUAD J LEAD
-40°C TO +85°C
I
NO
SOLDER
HI-8281CJT
44 PIN CERQUAD J LEAD
-55°C TO +125°C
T
NO
SOLDER
HOLT INTEGRATED CIRCUITS
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HI-8281 PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC J-LEAD PLCC
PIN NO. 1
PACKAGE TYPE:
PIN NO. 1 IDENT
.045 x 45°
.045 x 45°
.050 ± .005
(1.27 ± .127)
.690 ± .005
(17.526 ± .127)
SQ.
.653 ± .004
(16.586 ± .102)
SQ.
.031± .005
(.787 ± .127)
.017 ± .004
(.432 ± .102)
SEE DETAIL
A
.009
.011
.172 ± .008
(4.369 ± .203)
DETAIL A
.610 ± .020
(15.494± .508)
44-PIN CERQUAD J-LEAD
.015 ± .002
(.381 ± .051)
.020 MIN
(.508 ΜΙΝ)
R .025
.045
Package Type:
2 1 44 43
.688 ± .005
(17.475 ± .127)
MAX.
SQ.
.650 ± .010
(16.510 ± .254)
SQ.
.200
MAX.
(5.080)
.039 ± .005
(.990 ± .127)
.019 ± .002
(.483 ± .051)
.100 ± .007
.050
TYP. (2.540 ± .178)
(1.270)
HOLT INTEGRATED CIRCUITS
14
.620 ± .012
(15.748 ± .305)
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