19-4782; Rev 2; 9/04 KIT ATION EVALU E L B A IL AVA Multirange, +5V, 8-Channel, Serial 12-Bit ADCs Features The MAX1270/MAX1271 are multirange, 12-bit dataacquisition systems (DAS) that require only a single +5V supply for operation, yet accept signals at their analog inputs that can span above the power-supply rail and below ground. These systems provide eight analog input channels that are independently software programmable for a variety of ranges: ±10V, ±5V, 0 to +10V, 0 to +5V for the MAX1270; ±VREF, ±VREF/2, 0 to VREF, 0 to VREF/2 for the MAX1271. This range switching increases the effective dynamic range to 14 bits and provides the flexibility to interface 4–20mA, ±12V, and ±15V powered sensors directly to a single +5V system. In addition, these converters are fault protected to ±16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other features include a 5MHz bandwidth track/hold, softwareselectable internal/external clock, 110ksps throughput rate, and internal 4.096V or external reference operation. ♦ 12-Bit Resolution, 0.5 LSB Linearity The MAX1270/MAX1271 serial interface directly connects to SPI™/QSPI™ and MICROWIRE™ devices without external logic. A hardware shutdown input (SHDN) and two softwareprogrammable power-down modes, standby (STBYPD) or full power-down (FULLPD), are provided for low-current shutdown between conversions. In standby mode, the reference buffer remains active, eliminating startup delays. ♦ Internal or External Clock ♦ +5V Single-Supply Operation ♦ SPI/QSPI and MICROWIRE-Compatible 3-Wire Interface ♦ Four Software-Selectable Input Ranges MAX1270: 0 to +10V, 0 to +5V, ±10V, ±5V MAX1271: 0 to VREF, 0 to VREF/2, ±VREF, ±VREF/2 ♦ Eight Analog Input Channels ♦ 110ksps Sampling Rate ♦ ±16.5V Overvoltage-Tolerant Input Multiplexer ♦ Internal 4.096V or External Reference ♦ Two Power-Down Modes ♦ 24-Pin Narrow PDIP or 28-Pin SSOP Packages Typical Operating Circuit +5V 0.1µF The MAX1270/MAX1271 are available in 24-pin narrow PDIP or space-saving 28-pin SSOP packages. VDD Applications SHDN Industrial Control Systems Automatic Testing Data-Acquisition Systems Robotics Battery-Powered Medical Instruments Instruments CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 ANALOG INPUTS MAX1270 MAX1271 MC68HCXX Ordering Information PART TEMP RANGE PIN-PACKAGE INL (LSB) MAX1270ACNG 0°C to +70°C 24 Narrow PDIP ±0.5 MAX1270BCNG 0°C to +70°C 24 Narrow PDIP ±1 MAX1270ACAI 0°C to +70°C 28 SSOP MAX1270BCAI 0°C to +70°C 28 SSOP Ordering Information continued at end of data sheet. REF REFADJ 4.7µF 0.01µF DGND CS SCLK DIN DOUT SSTRB I/O SCK MOSI MISO AGND ±0.5 ±1 Pin Configurations appear at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1270/MAX1271 General Description MAX1270/MAX1271 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to AGND............................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V CH0–CH7 to AGND ......................................................... ±16.5V REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V) SSTRB, DOUT to DGND.............................-0.3V to (VDD + 0.3V) SHDN, CS, DIN, SCLK to DGND..............................-0.3V to +6V Max Current into Any Pin ....................................................50mA Continuous Power Dissipation (TA = +70°C) 24-Pin Narrow DIP (derate 13.33mW/°C above +70°C)..1067mW 28-Pin SSOP (derate 9.52mW/°C above +70°C) ..........762mW Operating Temperature Ranges MAX127_C_ _......................................................0°C to +70°C MAX127_E_ _......................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK = 2.0MHz, 50% duty cycle (MAX127_B); fCLK = 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ACCURACY (Note 1) Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL ±0.5 MAX127_B ±1.0 Unipolar Bipolar ±5 ±5 LSB ±10 MAX127_B Bipolar ±0.3 Bipolar Gain Error Temperature Coefficient (Note 2) MAX127_B MAX127_A ±0.1 Gain Error (Note 2) LSB ±3 MAX127_A Unipolar Unipolar LSB ±1 No missing codes over temperature Offset Error Channel-to-Channel Offset Error Matching Bits MAX127_A LSB MAX127_A ±7 MAX127_B ±10 MAX127_A ±7 LSB ±10 MAX127_B Unipolar, external reference ±3 Bipolar, external reference ±5 ppm/°C DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10VP-P (MAX1270), or ±4.096VP-P (MAX1271), fSAMPLE = 110ksps (MAX127_B), fSAMPLE = 100ksps (MAX127_A)) Signal-to-Noise + Distortion Ratio SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Channel-to-Channel Crosstalk Aperture Delay Aperture Jitter 2 70 Up to the 5th harmonic dB -87 80 -78 dB dB 50kHz (Note 3) -86 DC, VIN = ±16.5V -96 External clock mode 15 ns External clock mode <50 ps Internal clock mode 10 ns _______________________________________________________________________________________ dB Multirange, +5V, 8-Channel, Serial 12-Bit ADCs (VDD = +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK = 2.0MHz, 50% duty cycle (MAX127_B); fCLK = 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT Track/Hold Acquisition Time tACQ Small-Signal Bandwidth MAX127_A, fCLK = 1.8MHz 3.3 MAX127_B, fCLK = 2.0MHz 3.0 ±10V or ±VREF range 5 ±5V or ±VREF/2 range 2.5 0 to 10V or 0 to VREF range 2.5 0 to 5V or 0 to VREF/2 range 1.25 -3dB rolloff MHz MAX1270 Unipolar (BIP = 0), Table 3 MAX1271 Input Voltage Range (Table 3) VIN MAX1270 Bipolar (BIP = 1), Table 3 MAX1271 Unipolar RNG = 1 0 RNG = 0 0 5 RNG = 1 0 VREF RNG = 0 0 VREF/2 RNG = 1 -10 +10 RNG = 0 -5 +5 RNG = 1 -VREF +VREF RNG = 0 -VREF/2 +VREF/ 2 0 to 10V range -10 +720 IIN 10 0 to 5V range -10 +360 V MAX1270 MAX1271 Input Current µs MAX1270 Bipolar -10 0.1 +10 ±10V range -1200 +720 ±5V range -600 +360 ±VREF range -1200 +10 ±VREF/2 range -600 +10 µA MAX1271 Dynamic Resistance Input Capacitance ∆VIN/∆IIN Unipolar 21 Bipolar 16 (Note 4) kΩ 40 pF _______________________________________________________________________________________ 3 MAX1270/MAX1271 ELECTRICAL CHARACTERISTICS (continued) MAX1270/MAX1271 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK = 2.0MHz, 50% duty cycle (MAX127_B); fCLK = 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.076 4.096 4.116 V INTERNAL REFERENCE REF Output Voltage VREF REF Output Tempco TC VREF TA = +25°C MAX1270_C/MAX1271_C ±15 MAX1270_E/MAX1271_E ±30 Output Short-Circuit Current ppm/°C 30 Load Regulation 0 to 0.5mA output current (Note 5) Capacitive Bypass at REF 4.7 Capacitive Bypass at REFADJ 0.01 REFADJ Output Voltage 2.465 REFADJ Adjustment Range mA 10 Figure 1 Buffer Voltage Gain mV µF µF 2.500 2.535 V ±1.5 % 1.638 V/V REFERENCE INPUT (Reference buffer disabled, reference input applied to REF) Input Voltage Range 2.40 Input Current VREF = 4.18V Input Resistance VREF = 4.18V 4.18 Normal or STBYPD 400 FULLPD Normal or STBYPD FULLPD REFADJ Threshold for Buffer Disable 1 V µA 10 kΩ 4.18 MΩ VDD 0.5 V POWER REQUIREMENT Supply Voltage VDD 4.75 Normal Supply Current Power-Supply Rejection Ratio (Note 7) IDD PSRR 5.25 Bipolar range 18 Unipolar range 6 10 STBYPD power-down mode (Note 6) 700 850 FULLPD power-down mode 120 220 External reference = 4.096V ±0.1 ±0.5 Internal reference ±0.5 V mA µA LSB TIMING External Clock Frequency Range Acquisition Phase fSCLK MAX127_A 0.1 1.8 MAX127_B 0.1 2.0 External clock mode (Note 8) MAX127_A 3.3 MAX127_B 3.0 Internal clock mode, Figure 9 4 3 _______________________________________________________________________________________ MHz µs 5 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs (VDD = +5.0V ±5%; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK = 2.0MHz, 50% duty cycle (MAX127_B); fCLK = 1.8MHz, 50% duty cycle (MAX127_A); 18 clock/conversion cycle, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL Conversion Time tCONV CONDITIONS External clock mode (Note 8) MAX127_A 6.6 MAX127_B 6.0 Internal clock mode, Figure 9 External clock mode Throughput Rate MIN 6 TYP MAX 7.7 11 µs MAX127_A 100 MAX127_B 110 Internal clock mode Bandgap Reference Startup Time Power-up (Note 9) Reference Buffer Settling Time To 0.1mV, REF bypass capacitor fully discharged UNITS ksps 43 200 CREF = 4.7µF 8 CREF = 33µF 60 µs ms DIGITAL INPUTS (DIN, SCLK, CS, and SHDN) Input High Threshold Voltage Input Low Threshold Voltage Input Hysteresis VIH 2.4 VIL 0.8 VHYS V 0.2 Input Leakage Current IIN VIN = 0 to VDD Input Capacitance CIN V -10 V +10 µA (Note 4) 15 pF ISINK = 5mA 0.4 DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low VOL Output Voltage High VOH Tri-State Leakage Current Tri-State Output Capacitance IL COUT ISINK = 16mA ISOURCE = 0.5mA CS = VDD CS = VDD (Note 4) 0.4 VDD 0.5 -10 V V +10 µA 15 pF _______________________________________________________________________________________ 5 MAX1270/MAX1271 ELECTRICAL CHARACTERISTICS (continued) MAX1270/MAX1271 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs TIMING CHARACTERISTICS (VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V REF = +4.096V; 4.7µF at REF; external clock; fCLK = 2.0MHz (MAX127_B); fCLK = 1.8MHz (MAX127_A); TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) (Figures 2, 5, 7, 10) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0 ns 170 ns DIN to SCLK Setup tDS DIN to SCLK Hold tDH 100 SCLK Fall to Output Data Valid tDO CS Fall to Output Enable tDV CLOAD = 100pF 120 ns CS Rise to Output Disable tTR CLOAD = 100pF 100 ns 20 ns CS to SCLK Rise Setup tCSS 100 ns CS to SCLK Rise Hold tCSH 0 ns SCLK Pulse-Width High tCH 200 ns SCLK Pulse-Width Low tCL 200 SCLK Fall to SSTRB tSSTRB ns CLOAD = 100pF 200 ns CS to SSTRB Output Enable tSDV CLOAD = 100pF, external clock mode only 200 ns CS to SSTRB Output Disable tSTR CLOAD = 100pF, external clock mode only 200 ns SSTRB Rise to SCLK Rise tSCK Internal clock mode only (Note 4) 0 ns Note 1: Accuracy specifications tested at VDD = +5.0V. Performance at power-supply tolerance limit is guaranteed by power-supply rejection test. Note 2: External reference: VREF = 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2 LSB. Note 3: Ground “on” channel; sine wave applied to all “off” channels. VIN = ±5V (MAX1270), VIN = ±4V (MAX1271). Note 4: Guaranteed by design, not production tested. Note 5: Use static external loads during conversion for specified accuracy. Note 6: Tested using internal reference. Note 7: PSRR measured at full scale. Tested for the ±10V (MAX1270) and ±4.096V (MAX1271) input ranges. Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6). Note 9: Not production tested. Provided for design guidance only. 6 _______________________________________________________________________________________ Multirange, +5V, 8-Channel, Serial 12-Bit ADCs 5.5 0 1 2 3 4 5 6 450 350 250 EXTERNAL REFERENCE 50 -40 7 MAX1270/1 toc03 INTERNAL REFERENCE 550 150 0 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE NORMALIZED REFERENCE VOLTAGE vs. TEMPERATURE CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE EXTERNAL REFERENCE 110 90 INTERNAL REFERENCE 70 MAX1270/1 toc05 130 1.001 NORMALIZED REFERENCE VOLTAGE 150 1.000 0.999 0.998 0.997 0.996 50 -15 10 35 60 -40 85 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE INTEGRAL NONLINEARITY vs. DIGITAL CODE 0.7 0.6 UNIPOLAR MODE 0.5 0.4 0.3 BIPOLAR MODE 85 0.15 0.1 0.10 0.05 0 -0.05 -15 10 35 TEMPERATURE (°C) 60 85 0.20 0.15 0.10 UNIPOLAR MODE 0.05 0 -40 -15 10 35 60 85 0 fIN = 10kHz fSAMPLE = 110ksps -20 -40 -60 -80 -100 -120 -0.15 -40 0.25 FTT PLOT -0.10 0.2 BIPOLAR MODE 0.30 TEMPERATURE (°C) AMPLITUDE (dB) MAX1270/1 toc07 0.8 INTEGRAL NONLINEARITY (LSB) -40 0.35 MAX1270/1 toc06 TEMPERATURE (°C) CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB) SUPPLY VOLTAGE (V) MAX1270/1 toc04 FULL POWER-DOWN SUPPLY CURRENT (µA) MAX1270/1 toc02 5.7 5 CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB) 5.9 650 MAX1270/1 toc09 10 6.1 STANDBY SUPPLY CURRENT (µA) 15 6.3 750 MAX1270/1 toc08 SUPPLY CURRENT (mA) 20 6.5 SUPPLY CURRENT (mA) MAX1270/1 toc01 25 STANDBY SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. SUPPLY VOLTAGE 0 819 1638 2457 DIGITAL CODE 3276 4095 0 10k 20k 30k 40k 50k FREQUENCY (Hz) _______________________________________________________________________________________ 7 MAX1270/MAX1271 Typical Operating Characteristics (Typical Operating Circuit, VDD = +5V; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock, fCLK = 2MHz; 110ksps; TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Operating Circuit, VDD = +5V; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock, fCLK = 2MHz; 110ksps; TA = +25°C, unless otherwise noted.) VDD = 5V, INTERNAL REFERENCE, fCLK = 2MHz EXTERNAL CLOCK MODE. LOW-RANGE UNIPOLAR MODE. VCH_ = 0 7 6 5 4 3 2 8 AVERAGE SUPPLY CURRENT (mA) MAX1270-toc10 8 MAX1270-toc11 AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING FULLPD) AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING STANDBY) AVERAGE SUPPLY CURRENT (mA) MAX1270/MAX1271 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs VDD = 5V, INTERNAL REFERENCE, fCLK = 2MHz EXTERNAL CLOCK MODE. LOW-RANGE UNIPOLAR MODE. VCH_ = 0 7 6 5 4 3 2 1 1 0 0 0.1 1 10 100 0.1 1000 1 10 100 1000 CONVERSION RATE (ksps) CONVERSION RATE (ksps) Pin Description PIN SSOP 1 1 VDD 2, 4 2, 3 DGND 4, 7, 8, 3, 9, 11, 22, 22, 24 24, 25, 28 FUNCTION +5V Supply. Bypass with a 0.1µF capacitor to AGND. Digital Ground N.C. No Connection. No internal connection. 5 5 SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. 6 6 CS Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. 7 9 DIN Serial Data Input. Data is clocked in on the rising edge of SCLK. 8 10 SSTRB Serial Strobe Output. In internal clock mode, SSTRB goes low after the falling edge of the eighth SCLK and returns high when the conversion is done. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high in external clock mode. 10 12 DOUT Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is high. 11 13 SHDN Shutdown Input. When low, device is in FULLPD mode. Connect high for normal operation. 12 14 AGND Analog Ground 13–20 15–21, 23 8 NAME PDIP CH0–CH7 Analog Input Channels 21 26 REFADJ Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect to VDD when using an external reference at REF. 23 27 REF Reference-Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a 4.096V nominal output, externally adjustable to REFADJ. In external reference mode, disable the internal reference by pulling REFADJ to VDD and applying the external reference to REF. _______________________________________________________________________________________ Multirange, +5V, 8-Channel, Serial 12-Bit ADCs 5mA DOUT OR SSTRB +5V MAX1270 MAX1271 510kΩ 100kΩ REFADJ DOUT OR SSTRB CLOAD 0.5mA CLOAD 0.01µF 24kΩ a) HIGH IMPEDANCE TO VOH, VOL TO VOH AND VOH TO HIGH IMPEDANCE Figure 1. Reference-Adjust Circuit b) HIGH IMPEDANCE TO VOH, VOL TO VOH AND VOH TO HIGH IMPEDANCE Figure 2. Output Load Circuit for Timing Characteristics Detailed Description When operating in bipolar (MAX1270 and MAX1271) or unipolar mode (MAX1270) the signal applied at the input channel is rescaled through the resistor-divider network formed by R1, R2, and R3 (Figure 4); a low impedance (<4Ω) input source is recommended to minimize gain error. When the MAX1271 is configured for unipolar mode, the channel input resistance (RIN) becomes a fixed 5.12kΩ (typ). Source impedances below 15kΩ (0 to VREF) and 5kΩ (0 to VREF/2) do not significantly affect the AC performance of the ADC. Converter Operation The MAX1270/MAX1271 multirange, fault-tolerant ADCs use successive approximation and internal track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. Figure 3 shows the block diagram of the MAX1270/MAX1271. Analog-Input Track/Hold The T/H enters tracking/acquisition mode on the falling edge of the sixth clock in the 8-bit input control word, and enters hold/conversion mode when the timed acquisition interval (six clock cycles, 3µs minimum) ends. In internal clock mode, the acquisition is timed by two external clock cycles and four internal clock cycles. DIN The acquisition time (tACQ) is a function of the source output resistance, the channel input resistance, and the T/H capacitance. Higher source impedances can be used if an input capacitor is connected between the analog inputs and AGND. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC’s signal bandwidth. SSTRB DOUT CS SCLK INT CLOCK SERIAL INTERFACE LOGIC SHDN VDD CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 REF AGND DGND ANALOG INPUT MUX AND SIGNAL CONDITIONING OUT T/H 12-BIT SAR ADC +4.096V 2.5V REFERENCE REFADJ CLOCK IN 10kΩ Av = 1.638 REF MAX1270 MAX1271 Figure 3. Block Diagram _______________________________________________________________________________________ 9 MAX1270/MAX1271 +5V MAX1270/MAX1271 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs Input Bandwidth Digital Interface The ADC’s input small-signal bandwidth depends on the selected input range and varies from 1.5MHz to 5MHz (see Electrical Characteristics). The MAX1270B/ MAX1271B maximum sampling rate is 110ksps (100ksps for the MAX1270A/MAX1271A). By using undersampling techniques, it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate. To avoid high-frequency signals being aliased into the frequency band of interest, anti-aliasing filtering is recommended. The MAX1270/MAX1271 feature a serial interface that is fully compatible with SPI/QSPI and MICROWIRE devices. For SPI/QSPI, set CPOL = 0, CPHA = 0 in the SPI control registers of the microcontroller. Figure 5 shows detailed serial-interface timing information. See Table 1 for details on programming the input control byte. BIPOLAR Input Range and Protection The MAX1270/MAX1271 have software-selectable input ranges. Each analog input channel can be independently programmed to one of four ranges by setting the appropriate control bits (RNG, BIP) in the control byte (Table 1). The MAX1270 has selectable input ranges extending to ±10V (±VREF x 2.441), while the MAX1271 has selectable input ranges extending to ±VREF. Figure 4 shows the equivalent input circuit. A resistor network on each analog input provides ±16.5V fault protection for all channels. Whether or not the channel is on, this circuit limits the current going into or out of the pin to less than 2mA. This provides an added layer of protection when momentary overvoltages occur at the selected input channel, when a negative signal is applied to the input, and when the device is configured for unipolar mode. The overvoltage protection is active even if the device is in power-down mode or if VDD = 0. VOLTAGE REFERENCE S1 UNIPOLAR R3 5.12kΩ OFF R1 CH_ CHOLD T/H OUT S2 ON R2 S3 HOLD S1 = BIPOLAR/UNIPOLAR SWITCH S2 = INPUT MUX SWITCH S3, S4 = T/H SWITCH TRACK TRACK S4 R1 = 12.5kΩ or 5.12kΩ R2 = 8.67kΩ or ∞ (MAX1270) (MAX1271) (MAX1270) (MAX1271) Figure 4. Equivalent Input Circuit CS tCSH tCSS tCL tCH tCSH SCLK tDS tDH DIN tDV tDO tTR DOUT Figure 5. Detailed Serial-Interface Timing 10 HOLD ______________________________________________________________________________________ Multirange, +5V, 8-Channel, Serial 12-Bit ADCs BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) START SEL2 SEL1 SEL0 RNG BIP PD1 PD0 BIT NAME 7 (MSB) START DESCRIPTION 6, 5, 4 SEL2, SEL1, SEL0 3 RNG 2 BIP 1, 0 (LSB) PD1, PD0 First logic 1 after CS goes low defines the beginning of the control byte. These 3 bits select the desired “on” channel (Table 2). Selects the full-scale input voltage range (Table 3). Selects the unipolar or bipolar conversion mode (Table 3). Select clock and power-down modes (Table 4). Table 2. Channel Selection Table 4. Power-Down and Clock Selection SEL2 SEL1 SEL0 CHANNEL 0 0 0 CH0 0 0 1 CH1 0 1 0 CH2 0 1 1 CH3 1 0 0 CH4 1 0 1 CH5 1 1 0 CH6 1 1 1 CH7 PD1 PD0 MODE 0 0 Normal operation (always on), internal clock mode. 0 1 Normal operation (always on), external clock mode. 1 0 Standby power-down mode (STBYPD), clock mode unaffected. 1 1 Full power-down mode (FULLPD), clock mode unaffected. Table 3. Range and Polarity Selection for MAX1270/MAX1271 RANGE AND POLARITY SELECTION FOR THE MAX1270 INPUT RANGE RNG BIP Negative FULL SCALE ZERO SCALE (V) FULL SCALE 0 to +5V 0 0 — 0 VREF x 1.2207 0 to +10V 1 0 — 0 VREF x 2.4414 ±5V 0 1 -VREF x 1.2207 0 VREF x 1.2207 ±10V 1 1 -VREF x 2.4414 0 VREF x 2.4414 ZERO SCALE (V) FULL SCALE VREF/2 RANGE AND POLARITY SELECTION FOR THE MAX1271 INPUT RANGE RNG BIP Negative FULL SCALE 0 to VREF/2 0 0 — 0 0 to VREF 1 0 — 0 VREF ±VREF/2 0 1 -VREF/2 0 VREF/2 ±VREF 1 1 -VREF 0 VREF ______________________________________________________________________________________ 11 MAX1270/MAX1271 Table 1. Control-Byte Format MAX1270/MAX1271 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs Input Data Format Input data (control byte) is clocked in at DIN at the rising edge of SCLK. CS enables communication with the MAX1270/MAX1271. After CS falls, the first arriving logic 1 bit represents the start bit (MSB) of the input control byte. The start bit is defined as: The first high bit clocked into DIN with CS low anytime the converter is idle; e.g., after VDD is applied. OR The first high bit clocked into DIN after bit 6 (D6) of a conversion in progress is clocked onto DOUT. Output Data Format Output data is clocked out on the falling edge of SCLK at DOUT, MSB first (D11). In unipolar mode, the output is straight binary. For bipolar mode, the output is two’s complement binary. For output binary codes, refer to the Transfer Function section. How to Start a Conversion The MAX1270/MAX1271 use either an external serial clock or the internal clock to complete an acquisition and perform a conversion. In both clock modes, the external clock shifts data in and out. See Table 4 for details on programming clock modes. The falling edge of CS does not start a conversion on the MAX1270/MAX1271; a control byte is required for each conversion. Acquisition starts after the sixth bit is programmed in the input control byte. Conversion starts when the acquisition time, six clock cycles, expires. Keep CS low during successive conversions. If a startbit is received after CS transitions from high to low, but before the output bit 6 (D6) becomes available, the current conversion will terminate and a new conversion will begin. External Clock Mode (PD1 = 0, PD0 = 1) In external clock mode, the clock shifts data in and out of the MAX1270/MAX1271 and controls the acquisition and conversion timings. When acquisition is done, SSTRB pulses high for one clock cycle and conversion begins. Successive-approximation bit decisions appear at DOUT on each of the next 12 SCLK falling edges (Figure 6). Additional SCLK falling edges will result in zeros appearing at DOUT. Figure 7 shows the SSTRB timing in external clock mode. SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB and DOUT will output a logic low. The conversion must be completed in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the clock period exceeds 10µs, or if serial-clock interruptions could cause the conversion interval to exceed 120µs. The fastest the MAX1270/MAX1271 can run is 18 clocks per conversion in external clock mode, and with a clock rate of 2MHz, the maximum sampling rate is 111 ksps (Figure 8). In order to achieve maximum throughput, keep CS low, use external clock mode with a continuous SCLK, and start the following control byte after bit 6 (D6) of the conversion in progress is clocked onto DOUT. If CS is low and SCLK is continuous, guarantee a start bit by first clocking in 18 zeros. CS SCLK 1 DIN START SEL2 SEL1 SEL0 RNG MSB SSTRB DOUT 8 BIP PD1 12 13 14 24 25 PD0 LSB HIGH-Z HIGH-Z HIGH-Z D11 D10 D9 MSB A/D STATE ACQUISITION 6 SCLK D1 D0 FILLED WITH ZEROS LSB CONVERSION 12 SCLK Figure 6. External Clock Mode—25 Clocks/Conversion Timing 12 ______________________________________________________________________________________ HIGH-Z Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271 CS tSTR tSDV SSTRB HIGH-Z HIGH-Z tSSTRB tSSTRB SCLK SCLK 12 Figure 7. External Clock Mode—SSTRB Detailed Timing CS SCLK 1 MSB DIN HIGH-Z 8 CONTROL BYTE 0 13 14 19 16 24 26 31 37 32 CONTROL BYTE 1 LSB CONTROL BYTE 2 START SEL2 SEL1 SEL0 RNG BIP PD1 PD0 START SEL2 SEL1 SEL0 RNG BIP PD1 PD0 START SEL2 18 SCLK SSTRB RESULT MSB HIGH-Z DOUT D11 D10 D9 D8 D7 D6 RESULT 1 LSB D5 D4 D3 D2 D1 D11 D10 D0 D9 D8 D7 D6 D5 18 SCLK A/D STATE ACQUISITION 6 SCLK CONVERSION 12 SCLK ACQUISITION 6 SCLK CONVERSION 12 SCLK Figure 8. External Clock Mode—18 Clocks/Conversion Timing Internal Clock Mode (PD1 = 0, PD0 = 0) In internal clock mode, the MAX1270/MAX1271 generate their conversion clock internally. This frees the microprocessor from the burden of running the acquisition and the SAR conversion clock, and allows the conversion results to be read back at the processor’s convenience, at any clock rate from 0 to typically 10MHz. SSTRB goes low after the falling edge of the last bit (PD0) of the control byte has been shifted in, and returns high when the conversion is complete. Acquisition is completed and conversion begins on the falling edge of the 4th internal clock pulse after the control byte; conversion ends on the falling edge of the 16th internal clock pulse (12 internal clock cycle pulses are used for conversion). SSTRB will remain low for a maximum of 15µs, during which time SCLK should remain low for best noise performance. An internal register stores data while the conversion is in progress. The MSB of the result byte (D11) is present at DOUT starting at the falling edge of the last internal clock of conversion. Successive falling edges of SCLK will shift the remaining data out of this register (Figure 9). Additional SCLK edges will result in zeros on DOUT. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Pulling CS high prevents data from being clocked in and tri-states DOUT, but does not adversely affect a ______________________________________________________________________________________ 13 MAX1270/MAX1271 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs CS SCLK 1 START SEL2 SEL1 SEL0 RNG DIN 9 8 MSB BIP PD1 10 19 D11 D10 D1 20 PD0 LSB SSTRB 16 INT CLK DOUT HIGH-Z HIGH-Z MSB D0 HIGH-Z FILLED WITH ZEROS LSB ACQUISITION CONVERSION A/D STATE 2 EXT SCLK +4 INT CLK 12 INT CLK Figure 9. Internal Clock Mode—20 SCLK/Conversion Timing CS tCSS tSCK tCSH SSTRB tSSTRB SCLK SCLK #8 NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION. Figure 10. Internal Clock Mode—SSTRB Detailed Timing conversion in progress. Figure 10 shows the SSTRB timing in internal clock mode. Internal clock mode conversions can be completed with 13 external clocks per conversion but require a waiting period of 15µs for the conversion to be completed (Figure 11). Most microcontrollers require that conversions occur in multiples of 8 SCLK clock cycles. Sixteen clock cycles per conversion (as shown in Figure 12) is typically the most convenient way for a microcontroller to drive the MAX1270/MAX1271. 14 Applications Information Power-On Reset The MAX1270/MAX1271 power up in normal operation (all internal circuitry active) and internal clock mode, waiting for a start bit. The contents of the output data register are cleared at power-up. Internal or External Reference The MAX1270/MAX1271 operate with either an internal or external reference. An external reference is connected to either REF or REFADJ (Figure 13). The REFADJ internal buffer gain is trimmed to 1.638V to provide 4.096V at REF from a 2.5V reference. ______________________________________________________________________________________ Multirange, +5V, 8-Channel, Serial 12-Bit ADCs MAX1270/MAX1271 CS DIN 8 1 SCLK 9 14 22 16 24 CONTROL BYTE Ø CONTROL BYTE 1 CONTROL BYTE 2 START SEL2 SEL1 SEL0 RNG BIP PD1 PD0 START SEL2 SEL1 SEL0 RNG BIP PD1 PD0 START SEL2 SEL1 SEL0 13 SCLK SSTRB RESULT 1 RESULT Ø HIGH-Z DOUT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D11 D10 D9 D1 D0 D8 D7 D6 D5 D4 D3 13 SCLK ACQUISITION CONVERSION ACQUISITION CONVERSION A/D STATE Figure 11. Internal Clock Mode—13 Clocks/Conversion Timing CS 8 1 SCLK 9 16 CONTROL BYTE Ø DIN 24 17 25 32 CONTROL BYTE 1 CB 2 START SEL2 SEL1 SEL0 RNG BIP PD1 PD0 START SEL2 SEL1 SEL0 RNG BIP PD1 PD0 START 16 SCLK SSTRB RESULT Ø DOUT HIGH-Z HIGH-Z D11 D10 D9 D8 D7 D6 D5 RESULT 1 D4 D3 D2 D1 D0 HIGH-Z D11 D10 D9 D8 D7 D6 D5 D4 D3 16 SCLK ACQUISITION CONVERSION A/D STATE ACQUISITION CONVERSION IDLE Figure 12. Internal Clock Mode—16 Clocks/Conversion Timing Internal Reference The internally trimmed 2.50V reference is amplified through the REFADJ buffer to provide 4.096V at REF. Bypass REF with a 4.7µF capacitor to AGND and REFADJ with a 0.01µF capacitor to AGND (Figure 13a). The internal reference voltage is adjustable to ±1.5% (±65 LSBs) with the reference-adjust circuit of Figure 1. External Reference To use the REF input directly, disable the internal buffer by tying REFADJ to V DD (Figure 13b). Using the REFADJ input eliminates the need to buffer the reference externally. When a reference is applied at REFADJ, bypass REFADJ with a 0.01µF capacitor to AGND. Note that when an external reference is applied at REFADJ, the voltage at REF is given by: VREF = 1.6384 x VREFADJ (2.4 < VREF < 4.18) (Figure 13c). At REF and REFADJ, the input impedance is a minimum of 10kΩ for DC currents. During conversions, an external reference at REF must be able to deliver 400µA DC load currents and must have an output impedance of 10Ω or less. If the reference has higher output impedance or is noisy, bypass REF with a 4.7µF capacitor to AGND as close to the chip as possible. With an external reference voltage of less than 4.096V at REF or less than 2.5V at REFADJ, the increase in the ratio of RMS noise to the LSB value (full-scale / 4096) results in performance degradation (loss of effective bits). ______________________________________________________________________________________ 15 MAX1270/MAX1271 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs Power-Down Mode REF 4.7µF CREF MAX1270 MAX1271 AV = 1.638 REFADJ 0.01µF 10kΩ 2.5V Figure 13a. Internal Reference REF MAX1270 MAX1271 AV = 1.638 4.096V 4.7µF CREF For hardware-controlled power-down (FULLPD), pull SHDN low. When hardware shutdown is asserted, it becomes effective immediately, and any conversion in progress is aborted. Choosing Power-Down Modes The bandgap reference and reference buffer remain active in STBYPD mode, maintaining the voltage on the 4.7µF capacitor at REF. This is a DC state that does not degrade after power-down of any duration. VDD REFADJ 10kΩ 2.5V Figure 13b. External Reference—Reference at REF REF 4.7µF CREF MAX1270 MAX1271 To save power, configure the converter into low-current shutdown mode between conversions. Two programmable power-down modes are available in addition to a hardware shutdown. Select STBYPD or FULLPD by programming PD0 and PD1 in the input control byte (Table 4). When software power-down is asserted, it becomes effective only after the end of conversion. For example, if the control byte contains PD1 = 0, then the chip remains powered up. If PD1 = 1, then the chip powers down at the end of conversion. In all powerdown modes, the interface remains active and conversion results can be read. Input overvoltage protection is active in all power-down modes. The first logical 1 on DIN after CS falls is interpreted as a start condition, and powers up the MAX1270/ MAX1271 from a software selected STBYPD or FULLPD condition. In FULLPD mode, only the bandgap reference is active. Connect a 33µF capacitor between REF and AGND to maintain the reference voltage between conversions and to reduce transients when the buffer is enabled and disabled. Throughput rates down to 1ksps can be achieved without allotting extra acquisition time for reference recovery prior to conversion. This allows conversion to begin immediately after power-up. If the discharge of the REF capacitor during FULLPD exceeds the desired limits for accuracy (less than a fraction of an LSB), run a STBYPD power-down cycle prior to starting conversions. Take into account that the reference buffer recharges the bypass capacitor at an 80mV/ms slew rate, and add 50µs for settling time. AV = 1.638 REFADJ 10kΩ 2.5V 0.01µF Auto-Shutdown Selecting STBYPD on every conversion automatically shuts down the MAX1270/MAX1271 after each conversion without requiring any start-up time on the next conversion. 2.5V Figure 13c. External Reference—Reference at REFADJ 16 ______________________________________________________________________________________ Multirange, +5V, 8-Channel, Serial 12-Bit ADCs FULL-SCALE TRANSITION 11... 111 1 LSB = FS 4096 11... 110 OUTPUT CODE 1 LSB = 011... 111 2|FS| 4096 011... 110 11... 101 000... 001 000... 000 111... 111 00... 011 100... 010 00... 010 100... 001 00... 001 100... 000 00... 000 0 1 2 FS 3 INPUT VOLTAGE (LSB) -FS 0 FS - 3/2 LSB Figure 14a. Unipolar Transfer Function +FS - 1 LSB INPUT VOLTAGE (LSB) Figure 14b. Bipolar Transfer Function Transfer Function Output data coding for the MAX1270/MAX1271 is binary in unipolar mode with 1 LSB = (FS / 4096) and two’s complement binary in bipolar mode with 1 LSB = [(2 x | FS | ) / 4096]. Code transitions occur halfway between successive-integer LSB values. Figures 14a and 14b show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. For full-scale values, refer to Table 3. Layout, Grounding, and Bypassing Careful PC board layout is essential for best system performance. Use a ground plane for best performance. To reduce crosstalk and noise injection, keep analog and digital signals separate. Connect analog grounds and DGND in a star configuration to AGND. For noise-free operation, ensure the ground return from AGND to the supply ground is low impedance and as short as possible. Connect the logic grounds directly to the supply ground. Bypass VDD with 0.1µF and 4.7µF capacitors to AGND to minimize highand low-frequency fluctuations. If the supply is excessively noisy, connect a 5Ω resistor between the supply and VDD, as shown in Figure 15. SUPPLY GND +5V 4.7µF R* = 5Ω 0.1µF VDD ** AGND DGND +5V MAX1270 MAX1271 DGND DIGITAL CIRCUITRY *OPTIONAL **CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE. Figure 15. Power-Supply Grounding Connections ______________________________________________________________________________________ 17 MAX1270/MAX1271 OUTPUT CODE MAX1270/MAX1271 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs Pin Configurations TOP VIEW VDD 1 28 N.C. VDD 1 24 N.C. DGND 2 27 REF DGND 2 23 REF DGND 3 26 REFADJ N.C. 3 22 N.C. N.C. 4 21 REFADJ DGND 4 MAX1270 MAX1271 SCLK 5 25 N.C. SCLK 5 24 N.C. MAX1270 MAX1271 20 CH7 CS 6 CS 6 19 CH6 N.C. 7 22 N.C. DIN 7 18 CH5 N.C. 8 21 CH6 SSTRB 8 17 CH4 DIN 9 20 CH5 N.C. 9 16 CH3 SSTRB 10 19 CH4 23 CH7 DOUT 10 15 CH2 N.C. 11 18 CH3 SHDN 11 14 CH1 DOUT 12 17 CH2 AGND 12 13 CH0 SHDN 13 16 CH1 AGND 14 15 CH0 PDIP SSOP Ordering Information (continued) PART TEMP RANGE PIN-PACKAGE MAX1270AENG -40°C to +85°C 24 Narrow PDIP MAX1270BENG -40°C to +85°C 24 Narrow PDIP MAX1270AEAI -40°C to +85°C 28 SSOP MAX1270BEAI -40°C to +85°C 28 SSOP MAX1271ACNG 0°C to +70°C 24 Narrow PDIP MAX1271BCNG 0°C to +70°C 24 Narrow PDIP MAX1271ACAI 0°C to +70°C 28 SSOP 0°C to +70°C 28 SSOP MAX1271BCAI INL (LSB) TRANSISTOR COUNT: 4219 SUBSTRATE CONNECTED TO AGND ±0.5 ±1 ±0.5 ±1 ±0.5 ±1 ±0.5 ±1 MAX1271AENG -40°C to +85°C 24 Narrow PDIP ±0.5 MAX1271BENG -40°C to +85°C 24 Narrow PDIP ±1 MAX1271AEAI -40°C to +85°C 28 SSOP ±0.5 MAX1271BEAI -40°C to +85°C 28 SSOP ±1 18 Chip Information ______________________________________________________________________________________ Multirange, +5V, 8-Channel, Serial 12-Bit ADCs PDIPN.EPS ______________________________________________________________________________________ 19 MAX1270/MAX1271 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 2 SSOP.EPS MAX1270/MAX1271 Multirange, +5V, 8-Channel, Serial 12-Bit ADCs 1 INCHES E H MILLIMETERS DIM MIN MAX MIN MAX A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 B 0.010 0.015 0.25 0.38 C D 0.20 0.09 0.004 0.008 SEE VARIATIONS E 0.205 e 0.212 0.0256 BSC 5.20 INCHES D D D D D 5.38 MILLIMETERS MIN MAX MIN MAX 0.239 0.239 0.278 0.249 0.249 0.289 6.07 6.07 7.07 6.33 6.33 7.33 0.317 0.397 0.328 0.407 8.07 10.07 8.33 10.33 N 14L 16L 20L 24L 28L 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.025 0∞ 0.037 8∞ 0.63 0∞ 0.95 8∞ N A C B e L A1 D NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL DOCUMENT CONTROL NO. 21-0056 REV. C 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.