AMIC AP160F 8-bit microcontroller with 8kb otp Datasheet

AP160
8-BIT MICROCONTROLLER
WITH 8KB OTP
DATA SHEET
October 2001
GENERAL DESCRIPTION
The AP160 is a wide operating voltage, Low power consumption and high performance with AMIC high-density CMOS
technology. All instruction set of AP160 are fully compatible with the standard 8051. The AP160 contains 8K bytes OTP
EPROM, 256 bytes RAM, four 8-bit bi-directional and bit addressable I/O ports, three 16-bit timer/counter and eight interrupt
sources. To reduce power consumption, idle mode and power down mode are provided to implementation. For data
protection, program lock bits can be performed through programming LB1, LB2 and LB3. The AMIC AP160 is a useful and
powerful microcontroller in many control system application.
FEATURES
l
Compatible with MCS-51 Products
l
256 X 8 bit internal Data RAM.
l
8KB On-Chip OTP EPROM.
l
2.7V~5.5V Operating Range.
l
Fully Static Operation : 0Hz to 16 MHz
l
0~33MHZ speed range at VCC=5V.
l
32 Programmable I/O pins
l
Three 16-Bit Timers/Counters.
l
Programmable clock out.
l
Full-duplex UART
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Eight interrupt sources.
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2 level priority-interrupt.
l
Power reduction control modes
n
Idle mode
n
Power-down mode
l
3 security bits.
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Low EMI (Inhibit ALE)
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Wake-up from Power Down by an external interrupt.
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Available in PLCC and QFP44 packages.
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AMIC Technology, Inc.
AP160
PIN CONFIGURATIONS
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
40
NC
VCC
1
41
P1.0 (T2)
2
P0.0 (AD0)
P1.1 (T2EX)
3
42
P1.2
4
43
P1.3
5
44
P1.4
6
n PLCC
P1.5
7
39
P0.4 (AD4)
P1.6
8
38
P1.7
9
37
P0.5 (AD5)
P0.6 (AD6)
RST
10
36
P0.7 (AD7)
(RXD) P3.0
11
35
EA/VPP
NC
12
34
NC
(TXD) P3.1
33
ALE/PROG
(INT0) P3.2
13
14
32
PSEN
(INT1) P3.3
15
31
P2.7 (A15)
(T0) P3.4
16
30
P2.6 (A14)
(T1) P3.5
17
29
P2.5 (A13)
28
P0.3 (AD3)
34
27
(A11) P2.3
(A12) P2.4
P0.2 (AD2)
35
26
P0.1 (AD1)
25
(A9) P2.1
(A10) P2.2
P0.0 (AD0)
36
24
(A8) P2.0
37
23
NC
VCC
39
22
GND
NC
P1.0 (T2)
40
21
XTAL1
P1.1 (T2EX)
41
20
P1.2
19
42
18
P1.3
43
(RD) P3.7
XTAL2
P1.4
44
(WR) P3.6
AP160L
P1.5
1
33
P0.4 (AD4)
P1.6
2
32
P0.5 (AD5)
P1.7
3
31
P0.6 (AD6)
RST
4
30
P0.7 (AD7)
(RXD) P3.0
5
29
EA/VPP
NC
6
28
NC
(TXD) P3.1
27
ALE/PROG
(INT0) P3.2
7
8
(INT1) P3.3
AP160F
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n QFP
19
20
21
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
2
22
18
(A8) P2.0
17
16
P2.5 (A13)
GND
GND
P2.6 (A14)
23
15
24
11
XTAL1
10
(T1) P3.5
14
(T0) P3.4
13
P2.7 (A15)
12
25
(RD) P3.7
XTAL2
PSEN
9
(WR) P3.6
26
AMIC Technology, Inc.
AP160
BLOCK DIAGRAM
P0.0-P0.7
P2.0-P2.7
VCC
PORT 0 DRIVERS
PORT 2 DRIVERS
GND
RAM ADDR.
REGISTER
B
REGISTER
PORT0
LATACH
RAM
PORT2
LATACH
QUICK
FLASH
STACK
POINTER
ACC
TMP2
TMP1
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCREMENTER
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PROGRAM
COUNER
PSW
PSEN
ALE/ PROG
EA /VPP
RST
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
DPTR
PORT1
LATACH
OSC
PORT3
LATACH
PORT 1 DRIVERS
P1.0-P1.7
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PORT 3 DRIVERS
P3.0-P3.7
AMIC Technology, Inc.
AP160
PIN DESCRIPTIONS
SYMBOL
TYPE
VSS
I
DESCRIPTIONS
Ground.
VCC
I
P0.0-P0.7
I/O
Port 0 is an 8-bit open drain, bidirectional I/O port. When 1s are written to port 0 pins, the pins
can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed
low-order address/data bus during accesses to external program and data memory. In this
mode, P0 has internal pullups. Port 0 also receives the code bytes during programming on-chip
OTP EPROM and outputs the code bytes during program verification. External pullups are
required during program verification.
Supply voltage.
P1.0-P1.7
I/O
Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the
internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current ( IIL ) because of the internal pullups. In addition, P1.0 and P1.1
can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter
2 trigger input (P1.1/T2EX), respectively, as shown in the following:
T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out)
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control.
Port 1 also receives the low-order address bytes during programming on-chip OTP EPROM
and verification.
P2.0-P2.7
I/O
Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the
internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being
pulled low will source current ( IIL ) because of the internal pullups. Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong
internal pullups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2
also receives the high-order address bits and some control signals during programming on-chip
OTP EPROM and verification.
P3.0-P3.7
I/O
Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can
sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by the
internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being
pulled low will source current ( IIL ) because of the pullups. Port 3 also serves the functions of
various special features of the AP160, as shown below:
RXD (P3.0): Serial input port
TXD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Port 3 also receives some control signals for programming and verification.
RST
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Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device.
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AMIC Technology, Inc.
AP160
SYMBOL
TYPE
ALE/PROG
O/I
PSEN
O
Program Store Enable is the read strobe to external program memory. When the AP160 is
executing code from external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory.
EA/Vpp
I
External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to
VCC for internal program executions. This pin also receives the 12-volt programming enable
voltage (VPP) during programming OTP EPROM.
XTAL1
I
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
O
Output from the inverting oscillator amplifier.
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DESCRIPTIONS
Address Latch Enable is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during
Programming on-chip OPT EPROM. In normal operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external data memory. If
desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled
high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution
mode.
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AMIC Technology, Inc.
AP160
SPECIAL FUNCTION REGISTERS
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.
Table 1. AP160 SFR Map and Reset Values
0F8H
0F0H
0FFH
B
00000000
0F7H
0E8H
0E0H
0EFH
ACC
00000000
0E7H
0D8H
0DFH
0D0H
PSW
00000000
0C8H
T2CON
00000000
0D7H
T2MOD
XXXXXX00
RCAP2L
00000000
TL2
00000000
TH2
00000000
0CFH
0C0H
0C7H
0B8H
IP
XX000000
0BFH
0B0H
P3
11111111
0B7H
0A8H
IE
0X000000
0AFH
0A0H
P2
11111111
0A7H
098H
SCON
00000000
090H
P1
11111111
088H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
080H
P0
11111111
SP
00000111
DPL
00000000
DPH
00000000
SBUF
XXXXXXXX
09FH
097H
TH0
00000000
TH1
00000000
08FH
PCON
0XXX0000
087H
Note that not all of the addresses are occupied. Unoccupied addresses may not be implemented on the chip. Read
accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User
software should not write 1s to these unlisted locations, since they may be used in future AMIC products to invoke new
features. In that case the reset or inactive values of the new bits will always be 0.
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AMIC Technology, Inc.
AP160
TIMER2
Timer2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by
bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down
counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.
Table 2. T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8H
Bit
7
6
5
TF2
EXF2
RCLK
Reset Value = 00000000
Bit Addressable
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
4
TCLK
3
EXEN2
2
TR2
1
C/T2
0
CP/RL2
Function
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when
either RCLK = 1 or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt
routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode
(DCEN=1).
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in
serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in
serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on
T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered0.
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1.
CP/Rl2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX
when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on
Timer 2 overflow.
Table 3. Timer 2 Operating Modes
RCLK+TCLK
0
0
1
X
CP/RL2
0
1
X
X
TR2
1
1
1
0
MODE
16-Bit Auto-Reload
16-Bit Capture
Baud Rate Generator
(Off)
Timer2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine
cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the
Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2.
In this function, the external input is samples show a high in one cycle and a low in the next cycle, the count is incremented.
The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected.
Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is
1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be
held for at least one full machine cycle.
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AMIC Technology, Inc.
AP160
Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2=0, Timer 2 is a 16-bit timer or counter
which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2=1, Timer 2
performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to
be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be
set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 1.
OSC
÷ 12
C/T2=0
TH2
TL2
OVERFLOW
CONTROL
TR2
C/T2=1
TF2
T2 PIN
CAPTURE
TRANSITION
DETECTOR
RCAP2H
RCAP2L
TIMER 2
INTERRUPT
EXF2
T2EX PIN
CONTROL
EXEN2
Figure 1. Timer in Capture Mode
Auto-Reload (UP or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by
the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 3). Upon reset, the DCEN bit is set to 0 so that
Timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.
Figure 2 shows Timer 2 automatically counting up when DCEN=0.
OSC
÷ 12
C/T2=0
TH2
TL2
CONTROL
TR2
OVERFLOW
C/T2=1
RELOAD
T2 PIN
RCAP2H
TIMER 2
INTERRUPT
RCAP2L
TRANSITION
DETECTOR
TF2
EXF2
T2EX PIN
CONTROL
EXEN2
Figure 2. Timer 2 Auto Reload Mode (DCEN=0)
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AMIC Technology, Inc.
AP160
In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2=0, Timer2 counts up to 0FFFFH and then sets
the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and
RCAP2L. The values in Timer in Capture Mode RCAP2H and RCAP2L are preset by software.
If EXEN2=1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This
transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit
enables Timer2 to count up or down, as shown in Figure 3. In the mode, the T2EX pin controls the direction of the count. A
logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. The overflow also causes
the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at
T2EX makes Timer 2 count down. The timer underflows when TH2 and Tl2 equal the values stored in RCAP2H and
RACP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles
th
whenever Timer 2 overflows or underflows and can be used as a 17 bit of resolution. In this operating mode, EXF2 does
not flag an interrupt.
Table 3. T2MOD (Timer 2 Mode Control Register)
T2Mod Address = 0C9H
Not bit addressable
Bit
7
Symbol
Symbol
T2OE
DCEN
6
-
Reset Value = XXXX XX00B
5
-
4
-
3
-
2
-
1
T2OE
0
DCEN
Function
Not implemented, reserved for future
Timer 2 Output Enable bit.
When set, this bit allows Timer 2 to be configured as an up/down counter.
(DOWN COUNTING RELOAD VALUE)
0FFH
TOGGLE
0FFH
EXF2
OVERFLOW
OSC
÷ 12
C/T2=0
TH2
TL2
TF2
CONTROL
TR2
C/T2=1
TIMER 2
INTERRUPT
T2 PIN
RCAP2H
COUNT
DIRECTION
1=UP
0=DOWN
RCAP2L
(UP COUNTING RELOAD VALUE)
T2EX PIN
Figure 3. Timer 2 Auto Reload Mode (DCEN=1)
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AMIC Technology, Inc.
AP160
Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates
for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other
function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 4. The baud rate
generator mode is similar to the auto-reload mode, in that a rollover in Th2 causes the Timer 2 registers to be reloaded with
the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in modes 1 and 3 are
determined by Timer 2’s overflow rate according to the following equation.
Mode 1 and 3 Baud Rates =
Timer 2 Overflow Rate
16
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation
(CP/T2=0). The Timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it
increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every
state time (at 1/2 the oscillator frequency). The baud rate formula is given below.
Modes 1 and 3
Oscillator Frequency
=
Baud Rate
32 × [65536 − ( RCAP 2 H , RCAP 2 L)]
where (RCAP2H,RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK or TCLK=1 in T2CON. Note that a
rollover in TH2 does not ser TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX
will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Thus when timer 2 is in use as a baud rate
generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2=1) as a timer in the
baud rate generator mode. TH2 or TL2 should not be read from or written to. Under there conditions, the Timer is
incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but
should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be
turned off (clear TR2) before accessing the timer 2 or RCAP2 register.
TIMER 1 OVERFLOW
NOTE:OSC FREQ. IS DIVIDED BY 2, NOT 12
OSC
÷
2
÷
2
"0"
"1"
C/T2=0
SMOD1
"1"
TH2
RCLK
÷ 16
CONTROL
TR2
"1"
C/T2=1
T2 PIN
"0"
TL2
"0"
TCLK
RCAP2H
÷ 16
RCAP2L
RX
CLOCK
TX
CLOCK
TRANSITION
DETECTOR
T2EX PIN
EXF2
TIMER 2
INTERRUPT
CONTROL
EXEN2
Figure 4. Timer 2 in Baud Rate Generator Mode
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AMIC Technology, Inc.
AP160
Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regular
I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50%
duty cycle clock ranging from 61 HZ to 4MHZ at a 16MHZ operating frequency. To configure the Timer/Counter 2 as a clock
generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit Tr2 (T2CON.2) starts and stops
the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers
(RCAP2H, RCAP2L), as shown in the following equation.
Clock − Out Frequency =
Oscillator Frequency
4 × [65535 − ( RCAP 2 H , RCAP 2 L)]
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a
baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note,
however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they
both use RCAP2H and RCAP2L.
OSC
÷2
TL2
(8 BITS)
TH2
(8 BITS)
RCAP2L
RCAP2H
TR2
C/T2 BIT
P1.0
(T2)
÷2
T2OE (T2MOD.1)
TRANSITION
DETECTOR
P1.1
(T2EX)
EXF2
TIMER 2
INTERRUPT
EXEN2
Figure 5. Timer 2 in Clock-Out Mode
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AMIC Technology, Inc.
AP160
INTERRUPTS
The AP160 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1,
and 2), and the serial port interrupt. These interrupts are all shown in Figure 6. Each of these interrupt sources can be
individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable
bit, EA, which disables all interrupts at once. Note that Table 4 shows that bit position IE.6 is unimplemented. User software
should not write 1s to the bit position, since they may be used in future AMIC products. Timer 2 interrupt is generated by the
logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine
is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in
which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set
at S2P2 and is polled in the same cycle in which the timer overflows.
Table 4: Interrupt Enable (IE) Register
(MSB)
EA
-ET2
ES
ET1
EX1
ET0
(LSB)
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol
EA
Position
IE.7
Function
Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA=1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
-IE.6
Reserved.
ET2
IE.5
Timer 2 interrupt enable bit.
ES
IE.4
Serial Port interrupt enable bit.
ET1
IE.3
Timer 1 interrupt enable bit.
EX1
IE.2
External interrupt 1 enable bit.
ET0
IE.1
Timer 0 interrupt enable bit.
EX0
IE.0
External interrupt 0 enable bit.
User software should never write 1s to unimplemented bits, because they may be used in future AMIC products
0
INT0
IE0
1
TF0
0
INT1
IE1
1
TF1
T1
R1
TF2
EXF2
Figure 6. Interrupt Sources
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AMIC Technology, Inc.
AP160
DATA MEMORY
The AP160 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special
Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically
separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used
in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use
direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location
0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing
instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are avail-able as stack
space.
POWER MANAGEMENT
IDLE MODE
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software.
The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode
can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware
reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal
reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is
not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the
instruction following the one that invokes idle mode should not write to a port pin or to external memory.
POWER DOWN MODE
In the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated.
The way to exit from power down mode is either hardware reset or external interrupt. Reset redefines the SFRs but does not
change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must
be held active long enough to allow the oscillator to restart and stabilize.
Status of External Pins During Idle and Power Down Modes
Mode
Idle
Idle
Power Down
Power Down
Program Memory
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT0
Data
Float
Data
Float
PORT1
Data
Data
Data
Data
PORT2
Data
Address
Data
Data
PORT3
Data
Data
Data
Data
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the
oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to
start up (normally a few milliseconds) plus two machine cycles.
REDUCED EMI
All port pins of the AP160 have slew rate controlled outputs. This is to limit noise generated by quickly switching output
signals. The slew rate is factory set to approximately 10 ns rise and fall times.
AUXR Address = 8EH
Bit
7
6
5
4
3
NOTE: The AO bit (AUXR.0) in the AUXR register when set disables the ALE output.
Version 0.0
13
2
-
1
-
0
AO
AMIC Technology, Inc.
AP160
EPROM PROGRAMMING MODE
The setup for programming and verification on-chip OPT EPROM of AP160 is shown in Figure 7 and Figure 8,
independently. The address of the EPROM location to be programmed is applied to ports 1 and 2. The code byte to be
programmed into that location and read verified data are applied to port 0. The programming, verifying, Write Lock bits and
read signature byte mode are selectable by the pins of RST, PSEN, ALE/PROG, P2.6, P2.7, P3.6 and P3.7, as shown in
table 8. The programming and verification waveform is shown in Figure 9. VCC must be rising to VCC1 during
programming.
VCC1
A0~A7
ADDR
0000H/1FFFH
A8~A12
P1
VCC1
A0~A7
ADDR
0000H/1FFFH
A8~A12
VCC
P2.0~P2.4
P0
PGM
DATA
P2.6
ALE
PROG
P3.6
P0
P2.7
SEE
TABLE 8.
PGM DATA
(10K PULLUPS)
ALE
P3.6
P3.7
VIH
P3.7
XTAL2
XTAL1
GND
VCC
P2.0~P2.4
P2.6
P2.7
SEE
TABLE 8.
P1
EA
RST
VIH/VPP
XTAL2
VIH
EA
RST
XTAL1
PSEN
GND
Figure 7. Programming the EPROM MEMORY
VIH
PSEN
Figure 8. Verifying the EPROM MEMORY.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Symbol
VPP
VCC1
IPP
Parameter
Programming Voltage
Programming Supply Voltage
VPP Current During Program
Min.
11.5
6.0
Max.
12.5
6.5
1.0
t AS
Address Valid to Program Low
2
us
t DS
Input Valid to Program Low
2
us
t VPS
VPP Setup Time
2
us
t VCS
VCC Setup Time
2
us
t PW
Program Pulse Width
95
t DH
Data Hold Time
2
us
t VR
EA/VPP Recovery Time
2
us
105
Unit
V
V
mA
Data Valid from P2.7
100
ns
t DFP
Chip Enable to Output Float Delay
130
ns
t AH
Address Hold Time
Version 0.0
14
ALE/PROG = VIL
us
t DV
0
Test Conditions
ns
AMIC Technology, Inc.
AP160
PRGRAMMING AND VERIFY MODE AC WAVEFORMS
PROGRAM
ADDRESS
(P1.0~P1.7
P2.0~P2.4)
VERIFY
VIH
VALID
VIL
tAS
DATA
(PORT 0)
Hi-Z
DATA IN
DATA OUT
tDV
tDS
tDFP
tDH
VPP
VCC
LOGIC 1
EA/VPP
LOGIC 0
tVPS
tVPS
VCC1
VCC
VCC
tVCS
tPW
ALE/PROG
tVR
tAH
P2.7
Table 8. EPROM PROGRAMMING MODE
Mode
RST
PSEN
ALE/PROG EA/VPP
P2.6
P2.7
P3.6
P3.7
12V
L
H
H
H
H
L
L
H
H
Write Code Data
H
L
Read Code Data
H
L
Bit -1
H
L
12V
H
H
H
H
Bit -2
H
L
12V
H
H
L
L
Bit -3
H
L
12V
H
L
H
L
H
L
H
L
L
L
L
Write Lock
Read Signature Byte
H
H
Note: The signature bytes are read by the same procedure as a normal verification of locations 30H, 31H and 32H. The
values returns are as follows:
(30H) = 37H indicates manufactured by AMIC.
(31H) = 6EH indicates embedded OTP device.
(32H) = 7FH indicates JEDEC continuation code.
Version 0.0
15
AMIC Technology, Inc.
AP160
PROGRAM MEMORY LOCK BITS
The AP160 has three lock bits that can be left unprogrammed(U) or can be programmed (P) to obtain the additional
features listed in the following table.
Program Lock Bits
1
2
LB1
U
P
3
4
P
P
LB2
U
U
P
P
Protection Type
LB3
U
No program lock features
U
MOVC instructions executed from external program memory are disabled from fetching
code bytes from internal memory, EA is sampled and latched on reset, and further
programming of the OPT EPROM is disabled.
U
Same as mode 2, but verify is also disabled.
P
Same as mode 3, bur external execution is also disabled.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an
on-chip oscillator, as shown in the logic symbol. To drive the device from an external clock source, XTAL1 should be driven
while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the
input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times
specified in the data sheet must be observed.
Version 0.0
16
AMIC Technology, Inc.
AP160
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature range
Voltage on EA/V PP pin to V SS
Voltage on any other pin to V SS
Maximum Operating Voltage
Maximum I OL per I/O pin
Rating
-55 to +125
-65 to +150
0 to +12.5
-0.1 to +7.0
6.0
15.0
Unit
°C
°C
V
V
V
mA
NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
This is a stress rating only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DC CHARACTERICSTICS
The values shown in this table are valid for T A = -40°C to 85°C and V CC = 2.7V to 5.5V, unless otherwise noted.
Parameter
Condition
Min
Max
Units
Symbol
Input Low Voltage
(Except EA)
-0.5
0.2 VCC-0.1
V
VIL
VIL1
Input Low Voltage (EA)
VIH
Input High Voltage
VIH1
Input High Voltage
VOL
Output Low Voltage
(Ports 1,2,3)
Output Low Voltage
(Port 0, ALE, PSEN)
Output High Voltage
(Port 1,2,3, ALE, PSEN)
VOL1
VOH
Output High Voltage
(Port 0 in External Bus Mode)
VOH1
IIL
ITL
ILI
RRST
C IO
Logical 0 Input Current
(Ports 1,2,3)
Logical 1 to 0 Transition Current
(Ports 1,2,3)
Input Leakage Current
(Port 0, EA)
Reset Pulldown Resistor
Pin Capacitance
-0.5
0.2 VCC-0.3
V
(Except XTAL1, RST)
0.2 VCC+0.9
VCC+0.5
V
(XTAL1, RST)
0.7 VCC
VCC+0.5
V
I OL = 1.6mA
0.45
V
I OL = 3.2mA
0.45
V
IOH =-60uA, VCC=5V±10%
2.4
V
IOH =-25uA
0.75 VCC
V
IOH =-10uA
0.9 VCC
V
IOH =-800uA, VCC=5V±10%
2.4
V
IOH =-300uA
0.75 VCC
V
IOH =-80uA
0.9 VCC
V
VIN =0.45V
-50
uA
VIN =2V, VCC=5V±10%
-650
uA
0.45< VIN < VCC
±10
uA
300
10
KΩ
PF
25
6.5
100
40
mA
mA
uA
uA
50
Test Freq. =1 MHZ,
TA =25° C
Power Supply Current
Active Mode, 12 MHZ
Idle Mode, 12MHZ
Power Down Mode
VCC = 5.5V
VCC = 3V
Notes: 1. Under steady state (non-transient) conditions, I OL must be externally limited as follows:
ICC
Maximum I OL per port pin: 10mA
Maximum I OL per 8-biit port: Port 0: 26mA, Ports 1,2,3: 15mA
Maximum total I OL for all output pins: 71mA
If I OL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink currenr
greater than the listed test condition.
2. Minimum VCC for Power Down is 2V.
Version 0.0
17
AMIC Technology, Inc.
AP160
AC CHARACTERISTICS
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for
all other outputs = 80 pF.
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
Parameter
1/t CLCL
Oscillator Frequency
12MHZ Oscillator
Min
Max
Variable Oscillator
Min
Max
0
16
Units
MHZ
t LHLL
ALE Pulse Width
127
2 t CLCL -40
ns
t AVLL
Address Valid to ALE Low
43
t CLCL -40
ns
t LLAX
Address Hold After ALE Low
48
t CLCL -35
ns
t LLIV
ALE Low to Valid Instruction In
t LLPL
ALE Low to PSEN Low
43
t PLPH
PSEN Pulse Width
205
t PLIV
PSEN Low to Valid Instruction In
t PXIX
Input Instruction Hold After PSEN
233
4 t CLCL -100
ns
3 t CLCL -45
ns
145
0
ns
t CLCL -40
3 t CLCL -105
0
59
ns
ns
ns
t PXIZ
Input Instruction Float After PSEN
t PXAV
PSEN to Address Valid
t AVIV
Address to Valid Instruction In
312
5 t CLCL -105
ns
t PLAZ
PSEN Low to Address Float
10
10
ns
t RLRH
RD Pulse Width
400
t WLWH
WR Pulse Width
400
t RLDV
RD Low to Valid Data In
75
t CLCL -25
ns
t CLCL -8
ns
6 t CLCL -100
ns
6 t CLCL -100
252
0
5 t CLCL -165
ns
t RHDX
Data Hold After RD
t RHDZ
Data Float After RD
97
0
2 t CLCL -70
ns
t LLDV
ALE Low to Valid Data In
517
8 t CLCL -150
ns
9 t CLCL -165
ns
3 t CLCL +50
ns
t AVDV
Address to Valid Data In
t LLWL
ALE Low to RD or WR Low
200
t AVWL
Address to RD or WR Low
203
4 t CLCL -130
ns
t QVWX
Data Valid to WR Transition
33
t CLCL -50
ns
t QVWH
Data Valid to WR High
433
7 t CLCL -150
ns
t WHQX
Data Hold After WR
33
t CLCL -50
ns
t RLAZ
RD low to Address Float
t WHLH
RD or WR High to ALE High
Version 0.0
585
ns
300
3 t CLCL -50
0
43
123
18
t CLCL -40
0
ns
t CLCL +40
ns
AMIC Technology, Inc.
AP160
External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL
tLLIV
tLLPL
tPLIV
tPXAV
PSEN
tPLAZ
tPXIZ
tLLAX
PORT 0
tPXIX
INSTR IN
A0-A7
A0-A7
tAVIV
PORT 2
A8-A15
A8-A15
External Data Memory Read Cycle
tLHLL
ALE
tWHLH
tLLDV
PSEN
tRLRH
tLLWL
RD
tLLAX
tRHDZ
tRLDV
tAVLL
tRLAZ
PORT 0
tRHDX
A0-A7 FROM RI OR DPL
DATA IN
A0-A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
Version 0.0
P2.0-P2.7 OR A8-A15 FORM DPH
19
A8-A15 FROM PCH
AMIC Technology, Inc.
AP160
EXTERNAL CLOCK DRIVE WAVEFORMS
tCHCX
tCLCH
tCHCX
tCHCL
VCC-0.5V
0.7 VCC
0.2 VCC-0.1V
0.45V
tCLCX
tCLCL
EXTERNAL CLOCK DRIVE
Symbol
1/ t CLCL
Parameter
Oscillator Frequency
Min
0
t CLCL
Clock Period
62.5
ns
t CHCX
High Time
20
ns
t CLCX
Low Time
20
t CLCH
Rise Time
20
ns
t CHCL
Fall time
20
ns
Version 0.0
20
Max
16
Units
MHZ
ns
AMIC Technology, Inc.
AP160
SERIAL PORT TIMING: SHIFT REGISTER MODE TEST CONDITIONS
The values in this table are valid for VCC = 2.7V to 5.5V and Load Capacitance = 80pF
Symbol
Parameter
12MHZ Osc
Variable Oscillator
Min
Max
Min
Max
Serial Port Clock Cycle Time
1.0
12 t CLCL
t XLXL
Units
ns
t QVXH
Output Data Setup to Clock Rising Edge
700
10 t CLCL -133
ns
t XHQX
Output Data Hold After Clock Rising Edge
50
2 t CLCL -117
ns
t XHDX
Input Data Hold After Clock Rising Edge
0
t XHDV
Clock Rising Edge to Input Data Valid
0
ns
700
ns
10 t CLCL -133
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
0
1
2
4
3
5
6
7
8
ALE
tXLXL
CLOCK
tQVXH
WRITE TO SBUF
tXHQX
0
1
OUTPUT DATA
2
tXHDV
3
4
5
6
7
tXHDX
SET TI
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
INPUT DATA
VALID
VALID
SET RI
AC TESTING INPUT/OUTPUT WAVEFORMS
VCC-0.5V
0.2 VCC + 0.9V
TEST POINTS
0.2 VCC - 0.1V
0.45V
Note: 1. AC Inputs during testing are driven at V CC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are
made at V IH min. for a logic 1 and V IL max. for a logic 0.
FLOAT WAVEFORMS
VLOAD + 0.1V
VOL - 0.1V
TIMING REFERENCE
POINTS
VLOAD
VLOAD - 0.1V
VOL + 0.1V
Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin
begins to float when a 100 mV change from the loaded VOH /VOL level occurs.
Version 0.0
21
AMIC Technology, Inc.
AP160
ORDERING INFORMATION
Part
Number
Package
Type
Operation
Temperature Range
AP160L
PLCC
-40° C ~ +85° C
AP160F
QFP
-40° C ~ +85° C
NOTE : AMIC Technology, Inc. reserves the right to make changes without prior notice.
Version 0.0
22
AMIC Technology, Inc.
AP160
Package Information
PLCC 44L Outline Dimension
unit: inches/mm
HD
D
1 44
40
39
17
29
E
HE
GE
7
18
0.630/0.590
6
28
b
0.022/0.016
b1
0.032/0.026
Seating Plane
A
A2
A1
D 0.020 MIN
e
0.050 REF
0.150 REF
L
0.014/0.0008
C
0.004
y
GD
0.630/0.590
Dimensions in inches
Symbol
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.185
-
-
4.70
D
0.648
0.653
0.658
16.46
16.59
16.71
E
0.648
0.653
0.658
16.46
16.59
16.71
HD
0.680
0.690
0.700
17.27
17.53
17.78
HE
0.680
0.690
0.700
17.27
17.53
17.78
L
0.090
0.100
0.110
2.29
2.54
2.79
θ
0°
-
10°
0°
-
10°
Notes:
1. Dimensions D and E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
Version 0.0
23
AMIC Technology, Inc.
AP160
Package Information
QFP 44L Outline Dimensions
unit: inches/mm
See Detail A
D
D1
44
33
11
23
E1
1
E
34
22
12
0.20 min
e
D
0.25
Gauge Plane
Seating Plane
θ
A1
b
A
A2
C
0° min
0.10
L
1.6
DETAIL A
Symbol
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
A
-
-
0.106
-
-
2.7
A1
0.010
0.012
0.014
0.25
0.30
0.35
A2
0.0748
0.0787
0.0866
1.9
2.0
2.2
b
0.012 TYP
Max
0.3 TYP
D
0.5118
0.5196
0.5274
13.00
13.20
13.40
D1
0.3897
0.3937
0.3977
9.9
10.00
10.10
E
0.5118
0.5196
0.5275
13.00
13.20
13.40
E1
0.3897
0.3937
0.3977
9.9
10.00
10.10
L
0.0287
0.0346
0.0366
0.73
0.88
0.93
e
0.0315 TYP
0.80 TYP
C
0.0021
0.0060
0.0099
0.1
0.15
0.2
θ
0°
-
7°
0°
-
7°
Notes:
1. Dimensions D1 and E1 do not include mold protrusion.
2. Dimension b does not include dambar protrusion.
Version 0.0
24
AMIC Technology, Inc.
AP160
Corporation Headquarters
6F, No. 5, Li-Shin Road VI,
Hsin Chu, HSIP,
Taiwan, R.O.C.
Tel : 886-3-567-9966
Fax : 886-3-567-9977
Web : www.amic.com.tw
ASIA Pacific
AMIC Technology, Inc.
17F-8, No. 77, Shin Tai Wu Road,
Shi Chi, Taipei,
Taiwan, R.O.C.
Tel : 886-2-2698-1131
Fax : 886-2-2698-1030
Europe
AMIC Technology (EUROPE) B.V.
Crown Point Building, De Paal 1-6,13351 JA,
P.O Box 50053,1305 AB,
Almere, The Netherlands
Tel. +31-36-5359666
Fax. +31-36-5401888
US and Canada
AMIC Technology Inc.
2518 Mission College Blvd., Suite 102
Santa Clara, CA 95054, U.S.A.
Tel. +408-988-8818
Fax. +408-988-8817
Copyright © 2001 AMIC Technology, Inc.
Specification subject to change without notice. All rights reserved.
Version 0.0
25
AMIC Technology, Inc.