Micron MT48LC16M4A2 Synchronous dram Datasheet

64Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
MT48LC16M4A2 - 4 Meg x 4 x 4 banks
MT48LC8M8A2 - 2 Meg x 8 x 4 banks
MT48LC4M16A2 - 1 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/mti/msp/html/datasheet.html
FEATURES
PIN ASSIGNMENT (Top View)
• PC66-, PC100- and PC133-compliant
• 143 MHz, graphical 4 Meg x 16 option
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Modes: standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS
54-Pin TSOP
x4 x8 x16
NC
DQ0
NC
NC
NC
DQ1
NC
NC
-
MARKING
• Configurations
16 Meg x 4 (4 Meg x 4 x 4 banks)
8 Meg x 8 (2 Meg x 8 x 4 banks)
4 Meg x 16 (1 Meg x 16 x 4 banks)
16M4
8M8
4M16
• WRITE Recovery (tWR)
t
WR = “2 CLK”1
A2
• Plastic Package - OCPL2
54-pin TSOP II (400 mil)
TG
• Timing (Cycle Time)
10ns @ CL2 (PC100)
7.5ns @ CL3 (PC133)
7.5ns @ CL2 (PC133)
7ns @ CL3 (143 MHz)
None
L
• Operating Temperature Range
Commercial (0°C to +70°C)
Extended (-40°C to +85°C)
None
IT4
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
Part Number Example:
Refer to Micron Technical Note TN-48-05.
Off-center parting line.
Available on 4 Meg x 16.
Available on x8, x16, -8E.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Vss
DQ15 DQ7
VssQ DQ14 NC
DQ13 DQ6
VDDQ DQ12 NC
DQ11 DQ5
VssQ DQ10 NC
DQ9 DQ4
VDDQ DQ8 NC
Vss
NC
DQMH DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
-
NC
NC
DQ3
NC
NC
NC
DQ2
NC
DQM
-
16 Meg x 4
4 Meg x 4 x 4 banks
4K
4K (A0-A11)
4 (BA0, BA1)
8 Meg x 8
2 Meg x 8 x 4 banks
4K
4K (A0-A11)
4 (BA0, BA1)
4 Meg x 16
1 Meg x 16 x 4 banks
4K
4K (A0-A11)
4 (BA0, BA1)
1K (A0-A9)
512 (A0-A8)
256 (A0-A7)
KEY TIMING PARAMETERS
MT48LC8M8A2TG-8E
NOTE: 1.
2.
3.
4.
VDD
DQ0
- VDDQ
NC DQ1
DQ1 DQ2
- VssQ
NC DQ3
DQ2 DQ4
- VDDQ
NC DQ5
DQ3 DQ6
- VssQ
NC DQ7
VDD
NC DQML
- WE#
- CAS#
- RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD
-
Note: The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
-8E
-75
-7E
-7G3
• Self Refresh
Standard
Low Power
-
NC DQ0
x16 x8 x4
SPEED
GRADE
CLOCK
FREQUENCY
-7G
-7E
-75
-8E
-7E
-75
-8E
143 MHz
143 MHz
133 MHz
125 MHz
133 MHz
100 MHz
100 MHz
ACCESS TIME SETUP
CL = 2* CL = 3* TIME
–
–
–
–
5.4ns
6ns
6ns
6ns
5.4ns
5.4ns
6ns
–
–
–
2ns
1.5ns
1.5ns
2ns
1.5ns
1.5ns
2ns
HOLD
TIME
1ns
0.8ns
0.8ns
1ns
0.8ns
0.8ns
1ns
* CL = CAS (READ) latency
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
64Mb SDRAM PART NUMBERS
PART NUMBER
MT48LC16M4A2TG
MT48LC8M8A2TG
MT48LC4M16A2TG
command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4 or 8 locations, or the
full page, with a burst terminate option. An auto
precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the
burst sequence.
The 64Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while
accessing one of the other three banks will hide the
precharge cycles and provide seamless, high-speed,
random-access operation.
The 64Mb SDRAM is designed to operate in 3.3V
memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks in order to hide precharge time
and the capability to randomly change column
addresses on each clock cycle during a burst access.
ARCHITECTURE
16 Meg x 4
8 Meg x 8
4 Meg x 16
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 67,108,864 bits. It
is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the x4’s
16,777,216-bit banks is organized as 4,096 rows by
1,024 columns by 4 bits. Each of the x8’s 16,777,216-bit
banks is organized as 4,096 rows by 512 columns by 8
bits. Each of the x16’s 16,777,216-bit banks is organized
as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The address
bits registered coincident with the READ or WRITE
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 16 Meg x 4 .................
Functional Block Diagram - 8 Meg x 8 .................
Functional Block Diagram - 4 Meg x 16 ...............
Pin Descriptions .....................................................
4
5
6
7
Functional Description .........................................
Initialization ......................................................
Register Definition ............................................
Mode Register ...............................................
Burst Length ............................................
Burst Type ...............................................
CAS Latency ............................................
Operating Mode ......................................
Write Burst Mode ....................................
Commands ........................................................
8
8
8
8
8
9
10
10
10
11
11
12
12
12
12
12
12
12
12
12
13
13
14
14
15
21
23
23
24
24
Truth Table 1 (Commands and DQM Operation) .......
Command Inhibit ........................................
No Operation (NOP) ....................................
Load Mode Register ......................................
Active ............................................................
Read ..............................................................
Write .............................................................
Precharge ......................................................
Auto Precharge .............................................
Burst Terminate ............................................
Auto Refresh .................................................
Self Refresh ...................................................
Operation ..........................................................
Bank/Row Activation ...................................
Reads ............................................................
Writes ...........................................................
Precharge ......................................................
Power-Down .................................................
Clock Suspend ..............................................
Burst Read/Single Write ...............................
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
Concurrent Auto Precharge ......................... 25
Truth Table 2 (CKE) ................................................. 27
Truth Table 3 (Current State, Same Bank) .................. 28
Truth Table 4 (Current State, Different Bank) ............. 30
Absolute Maximum Ratings ................................... 32
DC Electrical Characteristics
and Operating Conditions ................................... 32
IDD Specifications and Conditions ......................... 32
Capacitance ............................................................ 33
Electrical Characteristics and Recommended
Operating Conditions (Timing Table) ............. 33
Timing Waveforms
Initialize and Load Mode Register .....................
Power-Down Mode ............................................
Clock Suspend Mode .........................................
Auto Refresh Mode ............................................
Self Refresh Mode ..............................................
Reads
Read - Without Auto Precharge ...................
Read - With Auto Precharge .........................
Single Read - Without Auto Precharge ........
Single Read - With Auto Precharge ..............
Alternating Bank Read Accesses ...................
Read - Full-Page Burst ...................................
Read - DQM Operation ................................
Writes
Write - Without Auto Precharge ..................
Write - With Auto Precharge .......................
Single Write - Without Auto Precharge .......
Single Write - With Auto Precharge .............
Alternating Bank Write Accesses .................
Write - Full-Page Burst .................................
Write - DQM Operation ...............................
3
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
16 Meg x 4 SDRAM
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 1,024 x 4)
1
DQM
SENSE AMPLIFIERS
4
4096
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
4
4
1024
(x4)
1
DQ0-DQ3
DATA
INPUT
REGISTER
COLUMN
DECODER
10
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
COLUMNADDRESS
COUNTER/
LATCH
10
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
8 Meg x 8 SDRAM
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 512 x 8)
1
DQM
SENSE AMPLIFIERS
8
4096
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
8
8
512
(x8)
1
DQ0-DQ7
DATA
INPUT
REGISTER
COLUMN
DECODER
9
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
COLUMNADDRESS
COUNTER/
LATCH
9
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
FUNCTIONAL BLOCK DIAGRAM
4 Meg x 16 SDRAM
CKE
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 256 x 16)
2
DQML,
DQMH
SENSE AMPLIFIERS
16
4096
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
16
16
256
(x16)
2
DQ0-DQ15
DATA
INPUT
REGISTER
COLUMN
DECODER
8
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
COLUMNADDRESS
COUNTER/
LATCH
8
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
38
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
37
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN and
SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row
active in any bank) or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters powerdown and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
19
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
16, 17, 18
WE#, CAS#,
RAS#
Input
Command Inputs: WE#, CAS# and RAS# (along with CS#) define the
command being entered.
39
x4, x8: DQM
Input
15, 39
x16: DQML,
DQMH
Input/Output Mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC and
DQMH is DQM. On the x16, DQML corresponds to DQ0-DQ7 and
DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered
same state when referenced as DQM.
20, 21
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
23-26, 29-34, 22, 35
A0-A11
Input
Address Inputs: A0-A11 are sampled during the ACTIVE command (rowaddress A0-A11) and READ/WRITE command (column-address A0-A9
[x4]; A0-A8 [x8]; A0-A7 [x16]; with A10 defining auto precharge) to
select one location out of the memory array in the respective bank. A10
is sampled during a PRECHARGE command to determine if all banks are
to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The
address inputs also provide the op-code during a LOAD MODE
REGISTER command.
2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0-DQ15
44, 45, 47, 48, 50, 51, 53
2, 5, 8, 11, 44, 47, 50, 53
DQ0-DQ7
5, 11, 44, 50
DQ0-DQ3
36, 40
NC
DESCRIPTION
x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, 51 are
NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, 53 are NCs for x4).
x8: I/O Data Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for x4).
x4: I/O Data Input/Output: Data bus for x4.
–
No Connect: These pins should be left unconnected.
3, 9, 43, 49
6, 12, 46, 52
VDDQ
VSSQ
1, 14, 27
VDD
Supply Power Supply: +3.3V ±0.3V.
28, 41, 54
VSS
Supply Ground.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
Supply DQ Power: Isolated DQ power on the die for improved noise immunity.
Supply DQ Ground: Isolated DQ ground on the die for improved noise
immunity.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
FUNCTIONAL DESCRIPTION
Register Definition
In general, the 64Mb SDRAMs (4 Meg x 4 x 4 banks,
2 Meg x 8 x 4 banks and 1 Meg x 16 x 4 banks) are quadbank DRAMs which operate at 3.3V and include a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the x4’s
16,777,216-bit banks is organized as 4,096 rows by
1,024 columns by 4 bits. Each of the x8’s 16,777,216-bit
banks is organized as 4,096 rows by 512 columns by 8
bits. Each of the x16’s 16,777,216-bit banks is organized
as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed
by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0 and BA1
select the bank, A0-A11 select the row). The address bits
(x4: A0-A9; x8: A0-A8; x16: A0-A7) registered coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register definition, command descriptions and device operation.
MODE REGISTER
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode and a write burst mode, as
shown in Figure 1. The mode register is programmed
via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed
again or the device loses power.
Mode register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the WRITE
burst mode, and M10 and M11 are reserved for future
use.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating
either of these requirements will result in unspecified
operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable, as
shown in Figure 1. The burst length determines the
maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a fullpage burst is available for the sequential type. The fullpage burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A9 (x4), A1-A8 (x8) or A1-A7 (x16) when
the burst length is set to two; by A2-A9 (x4), A2-A8 (x8)
or A2-A7 (x16) when the burst length is set to four; and
by A3-A9 (x4), A3-A8 (x8) or A3-A7 (x16) when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page
if the boundary is reached.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation.
Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COMMAND INHIBIT or a NOP. Starting at some point during
this 100µs period and continuing at least through the
end of this period, COMMAND INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be applied. All banks must be precharged, thereby placing
the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for mode register programming. Because the mode register will power up in
an unknown state, it should be loaded prior to applying
any operational command.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the
starting column address, as shown in Table 1.
Table 1
Burst Definition
Burst
Length
2
A11 A10
A9
A8
A6
A7
A5
A4
A3
A1
A2
Address Bus
A0
4
11
10
9
Reserved* WB
8
6
7
Op Mode
5
4
CAS Latency
3
1
2
BT
0
Mode Register (Mx)
Burst Length
*Should program
M11, M10 = “0, 0”
to ensure compatibility
with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
8
Full
Page
(y)
Burst Type
M3
0
Sequential
1
Interleaved
M6 M5 M4
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
n = A0-A9/8/7
(location 0-y)
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
NOTE: 1. For full-page accesses: y = 1,024 (x4); y = 512 (x8);
y = 256 (x16).
2. For a burst length of two, A1-A9 (x4), A1-A8 (x8),
or A1-A7 (x16) select the block-of-two burst; A0
selects the starting column within the block.
3. For a burst length of four, A2-A9 (x4), A2-A8 (x8),
or A2-A7 (x16) select the block-of-four burst; A0A1 select the starting column within the block.
4. For a burst length of eight, A3-A9 (x4), A3-A8
(x8), or A3-A7 (x16) select the block-of-eight
burst; A0-A2 select the starting column within the
block.
5. For a full-page burst, the full row is selected and
A0-A9 (x4), A0-A8 (x8), or A0-A7 (x16) select the
starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A9 (x4), A0-A8 (x8),
or A0-A7 (x16) select the unique column to be
accessed, and mode register bit M3 is ignored.
CAS Latency
0
Starting Column
Order of Accesses Within a Burst
Address
Type = Sequential Type = Interleaved
All other states reserved
Figure 1
Mode Register Definition
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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64Mb: x4, x8, x16
SDRAM
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result
of the clock edge one cycle earlier (n + m - 1), and
provided that the relevant access times are met, the
data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all
relevant access times are met, if a READ command is
registered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 2. Table 2
indicates the operating frequencies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions
may result.
T0
T1
T2
Operating Mode
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to
READ bursts, but write accesses are single-location
(nonburst) accesses.
Table 2
CAS Latency
ALLOWABLE OPERATING
FREQUENCY (MHz)
T3
CLK
COMMAND
READ
NOP
SPEED
-7G
-7E
-75
-8E
NOP
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 2
T0
T1
T2
T3
NOP
NOP
NOP
CAS
LATENCY = 2
–
≤ 133
≤ 100
≤ 100
CAS
LATENCY = 3
≤ 143
≤ 143
≤ 133
≤ 125
T4
CLK
COMMAND
READ
tLZ
tOH
DOUT
DQ
tAC
CAS Latency = 3
DON’T CARE
UNDEFINED
Figure 2
CAS Latency
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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64Mb: x4, x8, x16
SDRAM
Commands
Truth Table 1 provides a quick reference of
available commands. This is followed by a written
description of each command. Three additional Truth
Tables appear following the Operation section; these
tables provide current state/next state information.
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Notes: 1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
CS# RAS# CAS# WE# DQM
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)
L
L
H
H
X
Bank/Row
X
3
H
L/H8
Bank/Col
X
4
L
L/H8
Bank/Col
Valid
4
WRITE (Select bank and column, and start WRITE burst)
H
L
L
H
BURST TERMINATE
L
H
H
L
X
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
X
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
L
L
L
H
X
X
X
6, 7
LOAD MODE REGISTER
L
L
L
L
X
Op-Code
X
2
Write Enable/Output Enable
–
–
–
–
L
–
Active
8
Write Inhibit/Output High-Z
–
–
–
–
H
–
High-Z
8
NOTE: 1.
2.
3.
4.
5.
6.
7.
8.
L
X
NOTES
X
L
X
DQs
H
READ (Select bank and column, and start READ burst)
X
ADDR
CKE is HIGH for all commands shown except SELF REFRESH.
A0-A11 define the op-code written to the mode register.
A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
A0-A9 (x4), A0-A8 (x8), or A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read
from or written to.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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64Mb: x4, x8, x16
SDRAM
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM
is effectively deselected. Operations already in progress
are not affected.
determines whether or not auto precharge is used. If
auto precharge is selected, the row being accessed will
be precharged at the end of the WRITE burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses. Input data appearing on the DQs
is written to the memory array subject to the DQM
input logic level appearing coincident with the data. If
a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal
is registered HIGH, the corresponding data inputs will
be ignored, and a WRITE will not be executed to that
byte/column location.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations already
in progress are not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0-A11. See
mode register heading in the Register Definition section.
The LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether one
or all banks are to be precharged, and in the case where
only one bank is to be precharged, inputs BA0, BA1
select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A11 selects the row. This
row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank.
A PRECHARGE command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A9 (x4), A0-A8 (x8), or A0-A7 (x16) selects the
starting column location. The value on input A10
determines whether or not auto precharge is used. If
auto precharge is selected, the row being accessed will
be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses. Read data appears on the DQs
subject to the logic level on the DQM inputs two clocks
earlier. If a given DQM signal was registered HIGH, the
corresponding DQs will be High-Z two clocks later; if
the DQM signal was registered LOW, the DQs will
provide valid data.
AUTO PRECHARGE
Auto precharge is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in
conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except
in the full-page burst mode, where auto precharge does
not apply. Auto precharge is nonpersistent in that it is
either enabled or disabled for each individual READ or
WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (tRP) is completed. This is
determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each
burst type in the Operation section of this data sheet.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A9 (x4), A0-A8 (x8), or A0-A7 (x16) selects the
starting column location. The value on input A10
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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64Mb: x4, x8, x16
SDRAM
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a
refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 64Mb SDRAM
requires 4,096 AUTO REFRESH cycles every 64ms (tREF),
regardless of width option. Providing a distributed
AUTO REFRESH command every 15.625µs will meet
the refresh requirement and ensure that each row is
refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle
rate (tRC), once every 64ms.
Once the SELF REFRESH command is registered, all the
inputs to the SDRAM become “Don’t Care,” with the
exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM
provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must
remain in self refresh mode for a minimum period
equal to tRAS and may remain in self refresh mode for
an indefinite period beyond that.
The procedure for exiting self refresh requires a
sequence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks)
for tXSR, because time is required for the completion of
any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued every 15.625µs or less as
both SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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64Mb: x4, x8, x16
SDRAM
Operation
CLK
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must
be “opened.” This is accomplished via the ACTIVE
command, which selects both the bank and the row to
be activated (see Figure 3).
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks, rounded to 3. This is reflected in Figure 4,
which covers any case where 2 < tRCD (MIN)/tCK ≤ 3.
(The same procedure is used to convert other specification limits from time units to clock cycles).
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access overhead. The minimum time interval between successive
ACTIVE commands to different banks is defined by
tRRD.
T0
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0-A11
BANK
ADDRESS
BA0, BA1
Figure 3
Activating a Specific Row in a
Specific Bank
T1
T2
NOP
NOP
T3
T4
CLK
COMMAND
ACTIVE
READ or
WRITE
tRCD
DON’T CARE
Example: Meeting
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
tRCD
Figure 4
(MIN) When 2 < tRCD (MIN)/tCK < 3
14
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64Mb: x4, x8, x16
SDRAM
READs
READ bursts are initiated with a READ command, as
shown in Figure 5.
The starting column and bank addresses are provided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available
following the CAS latency after the READ command.
Each subsequent data-out element will be valid by the
next positive clock edge. Figure 6 shows general timing
for each possible CAS latency setting.
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go HighZ. A full-page burst will continue until terminated. (At
the end of the page, it will wrap to column 0 and
continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixedlength READ burst may be immediately followed by
data from a READ command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last
element of a completed burst or the last desired data
element of a longer burst which is being truncated.
T0
CLK
T1
T2
T3
NOP
NOP
CLK
CKE
HIGH
COMMAND
READ
tLZ
CS#
tOH
DOUT
DQ
tAC
CAS Latency = 2
RAS#
CAS#
T0
T1
T2
T3
T4
NOP
NOP
NOP
CLK
WE#
A0-A9: x4
A0-A8: x8
A0-A7: x16
COMMAND
READ
tLZ
COLUMN
ADDRESS
tOH
DOUT
DQ
tAC
A11: x4
A9, A11: x8
A8, A9, A11: x16
CAS Latency = 3
DON’T CARE
ENABLE AUTO PRECHARGE
UNDEFINED
A10
DISABLE AUTO PRECHARGE
BA0,1
Figure 6
CAS Latency
BANK
ADDRESS
Figure 5
READ Command
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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64Mb: x4, x8, x16
SDRAM
The new READ command should be issued x cycles
before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 7 for CAS latencies of two
and three; data element n + 3 is either the last of a burst
of four or the last desired of a longer burst. The 64Mb
SDRAM uses a pipelined architecture and therefore
T0
T1
T2
does not require the 2n rule associated with a prefetch
architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Fullspeed random read accesses can be performed to the
same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
T3
T4
T5
T6
CLK
COMMAND
READ
NOP
NOP
NOP
NOP
READ
NOP
X = 1 cycle
ADDRESS
BANK,
COL n
BANK,
COL b
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
DOUT
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
READ
NOP
NOP
X = 2 cycles
BANK,
COL b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CAS Latency = 3
NOTE:
Each READ command may be to any bank. DQM is LOW.
DON’T CARE
Figure 7
Consecutive READ Bursts
64Mb: x4, x8, x16 SDRAM
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64Mb: x4, x8, x16
SDRAM
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
a
NOP
DOUT
x
NOP
DOUT
m
CAS Latency = 3
NOTE:
Each READ command may be to any bank. DQM is LOW.
DON’T CARE
Figure 8
Random READ Accesses
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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64Mb: x4, x8, x16
SDRAM
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by
data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or
last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given
system design, there may be a possibility that the
device driving the input data will go Low-Z before the
SDRAM DQs go High-Z. In this case, at least a singlecycle delay should occur between the last read data and
the WRITE command.
The DQM input is used to avoid I/O contention, as
shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output
buffers) to suppress data-out from the READ. Once the
WRITE command is registered, the DQs will go High-Z
(or remain High-Z), regardless of the state of the DQM
signal, provided the DQM was active on the clock just
prior to the WRITE command that truncated the READ
command. If not, the second WRITE will be an invalid
WRITE. For example, if DQM was LOW during T4 in
Figure 10, then the WRITEs at T5 and T7 would be valid,
while the WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for input
buffers) to ensure that the written data is not masked.
Figure 9 shows the case where the clock frequency
allows for bus contention to be avoided without adding
a NOP cycle, and Figure 10 shows the case where the
additional NOP is needed.
T0
T0
T1
T2
T3
T4
T1
T2
T3
T4
T5
CLK
CLK
DQM
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
WRITE
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
WRITE
BANK,
COL b
tHZ
BANK,
COL b
DQ
tCK
DOUT n
tDS
tHZ
DOUT n
DQ
DIN b
NOTE:
DIN b
tDS
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
DON’T CARE
NOTE:
A CAS latency of three is used for illustration.
The READ command may be to any bank, and the WRITE
command may be to any bank. If a burst of one is used,
then DQM is not required.
DON’T CARE
Figure 10
READ to WRITE With
Extra Clock Cycle
Figure 9
READ to WRITE
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This
is shown in Figure 11 for each possible CAS latency;
data element n + 3 is either the last of a burst of four or
T0
T1
T2
the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that
part of the row precharge time is hidden during the
access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
BANK a,
ROW
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n
DQ
DOUT
n+1
BANK a,
ROW
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE:
DON’T CARE
DQM is LOW.
Figure 11
READ to PRECHARGE
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
19
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©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
PRECHARGE command is that it requires that the
command and address buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE
T0
T1
T2
command, provided that auto precharge was not activated. The BURST TERMINATE command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 12 for each
possible CAS latency; data element n + 3 is the last
desired data element of a longer burst.
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 1 cycle
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE:
DQM is LOW.
DON’T CARE
Figure 12
Terminating a READ Burst
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
20
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64Mb: x4, x8, x16
SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
The starting column and bank addresses are
provided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the
generic WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE command. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to column 0 and
continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixedlength WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE command
can be issued on any clock following the previous
WRITE command, and the data provided coincident
with the new command applies to the new command.
An example is shown in Figure 15. Data n + 1 is either
the last of a burst of two or the last desired of a longer
burst. The 64Mb SDRAM uses a pipelined architecture
and therefore does not require the 2n rule associated
with a prefetch architecture. A WRITE command can be
initiated on any clock cycle following a previous WRITE
command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in
Figure 16, or each subsequent WRITE may be performed
to a different bank.
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
NOTE:
Burst length = 2. DQM is LOW.
Figure 14
WRITE Burst
CLK
CKE
DIN
n+1
DIN
n
DQ
HIGH
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CS#
CLK
RAS#
CAS#
WE#
A0-A9: x4
A0-A8: x8
A0-A7: x16
BANK,
COL b
COLUMN
ADDRESS
A11: x4
A9, A11: x8
A8, A9, A11: x16
DQ
DIN
n
DIN
n+1
DIN
b
ENABLE AUTO PRECHARGE
A10
NOTE:
DISABLE AUTO PRECHARGE
BA0,1
BANK
ADDRESS
DON’T CARE
Figure 13
WRITE Command
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
DQM is LOW. Each WRITE
command may be to any bank.
Figure 15
WRITE to WRITE
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©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a
subsequent READ command. Once the READ command is registered, the data inputs will be ignored, and
WRITEs will not be executed. An example is shown in
Figure 17. Data n + 1 is either the last of a burst of two
or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was not
activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank.
The PRECHARGE command should be issued tWR after
T0
T1
T2
T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
the clock edge at which the last desired input data
element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless
of frequency. In addition, when truncating a WRITE
burst, the DQM signal must be used to mask input data
for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is
shown in Figure 18. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
CLK
T0
T1
T2
T3
WRITE
NOP
PRECHARGE
NOP
T4
T5
T6
NOP
ACTIVE
NOP
CLK
tWR@ tCK 15ns
DIN
n
DQ
DQM
DIN
m
DIN
x
DIN
a
t RP
NOTE:
COMMAND
Each WRITE command may be to any bank.
DQM is LOW.
ADDRESS
Figure 16
Random WRITE Cycles
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
DIN
n+1
DIN
n
tWR@ tCK < 15ns
T0
T1
T2
T3
T4
T5
DQM
CLK
t RP
COMMAND
COMMAND
WRITE
ADDRESS
BANK,
COL n
NOP
READ
NOP
NOP
NOP
ADDRESS
WRITE
NOP
NOP
PRECHARGE
NOP
BANK
(a or all)
BANK a,
COL n
NOP
ACTIVE
BANK a,
ROW
t WR
DQ
DIN
n
BANK,
COL b
DIN
n+1
DQ
DOUT
b
NOTE:
DOUT
b+1
DIN
n
DIN
n+1
DQM could remain LOW in this example if the WRITE burst is a fixed
length of two.
DON’T CARE
NOTE:
The WRITE command may be to any bank, and the READ command may
be to any bank. DQM is LOW. CAS latency = 2 for illustration.
Figure 18
WRITE to PRECHARGE
Figure 17
WRITE to READ
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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64Mb: x4, x8, x16
SDRAM
PRECHARGE
The PRECHARGE command (Figure 20) is used to
deactivate the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a
subsequent row access some specified time (tRP) after
the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to
be precharged, inputs BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle
state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 19, where data n is the last
desired data element of a longer burst.
T0
T1
T2
COMMAND
WRITE
BURST
TERMINATE
ADDRESS
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
CLK
DQ
NOTE:
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no
accesses are in progress. If power-down occurs when all
banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a row
active in either bank, this mode is referred to as active
power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not
remain in the power-down state longer than the refresh
period (64ms) since no refresh operations are performed in this mode.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting tCKS). See Figure 21.
NEXT
COMMAND
DQMs are LOW.
Figure 19
Terminating a WRITE Burst
CLK
CKE
HIGH
((
))
((
))
CLK
tCKS
CS#
CKE
> tCKS
((
))
RAS#
COMMAND
((
))
((
))
NOP
NOP
All banks idle
CAS#
Input buffers gated off
Enter power-down mode.
WE#
Exit power-down mode.
ACTIVE
tRCD
tRAS
tRC
DON’T CARE
A0-A9, A11
Figure 21
Power-Down
All Banks
A10
Bank Selected
BA0,1
BANK
ADDRESS
Figure 20
PRECHARGE Command
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
CLOCK SUSPEND
The clock suspend mode occurs when a column
access/burst is in progress and CKE is registered LOW.
In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended. Any command or data present on the input
pins at the time of a suspended internal clock edge is
ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long
as the clock is suspended. (See examples in Figures 22
and 23.)
T0
T1
T2
T3
T4
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by
programming the write burst mode bit (M9) in the
mode register to a logic 1. In this mode, all WRITE
commands result in the access of a single column
location (burst of one), regardless of the programmed
burst length. READ commands access columns according to the programmed burst length and sequence, just
as in the normal mode of operation (M9 = 0).
T5
T0
CLK
CLK
CKE
CKE
T2
T3
T4
T5
T6
INTERNAL
CLOCK
INTERNAL
CLOCK
COMMAND
T1
NOP
ADDRESS
WRITE
NOP
COMMAND
READ
ADDRESS
BANK,
COL n
DIN
n
DIN
n+1
DIN
n+2
NOP
NOP
NOP
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
NOTE: For this example, burst length = 4 or greater, and DQM
is LOW.
DON’T CARE
Figure 22
Clock Suspend During WRITE Burst
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
NOP
BANK,
COL n
DQ
DQ
NOP
NOP
Figure 23
Clock Suspend During READ Burst
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©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO
PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is
registered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a
READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank n
will begin when the WRITE to bank m is registered
(Figure 25).
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
NOP
Page Active
READ - AP
BANK m
NOP
READ with Burst of 4
NOP
NOP
NOP
Interrupt Burst, Precharge
Idle
t RP - BANK n
Page Active
BANK m
tRP - BANK m
Precharge
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
BANK m,
COL d
DOUT
a+1
DOUT
a
DQ
DOUT
d
DOUT
d+1
CAS Latency = 3 (BANK n)
NOTE:
CAS Latency = 3 (BANK m)
DQM is LOW.
Figure 24
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
READ with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
Write-Back
WRITE with Burst of 4
BANK n,
COL a
t WR - BANK m
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
CAS Latency = 3 (BANK n)
NOTE:
1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
DON’T CARE
Figure 25
READ With Auto Precharge Interrupted by a WRITE
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
25
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©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will
begin after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the
READ to bank m (Figure 26).
T0
T1
4. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a WRITE
on bank n when registered. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
the WRITE to bank m is registered. The last valid data
WRITE to bank n will be data registered one clock prior
to a WRITE to bank m (Figure 27).
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
READ - AP
BANK m
NOP
WRITE with Burst of 4
DIN
a
DQ
NOP
Precharge
tWR - BANK n
tRP - BANK n
NOP
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
Interrupt Burst, Write-Back
Page Active
BANK m
NOP
BANK m,
COL d
DOUT
d+1
DOUT
d
DIN
a+1
CAS Latency = 3 (BANK m)
NOTE:
1. DQM is LOW.
Figure 26
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
Page Active
NOP
NOP
WRITE with Burst of 4
WRITE - AP
BANK m
NOP
Interrupt Burst, Write-Back
tWR - BANK n
BANK m
ADDRESS
DQ
NOTE:
WRITE - AP
BANK n
Page Active
NOP
Precharge
tRP - BANK n
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK n,
COL a
DIN
a
NOP
BANK m,
COL d
DIN
a+1
DIN
a+2
1. DQM is LOW.
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
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©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKEn-1 CKEn
L
L
L
H
H
L
H
H
CURRENT STATE
COMMANDn
ACTIONn
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
Clock Suspend
X
Maintain Clock Suspend
Power-Down
COMMAND INHIBIT or NOP
Exit Power-Down
5
Self Refresh
COMMAND INHIBIT or NOP
Exit Self Refresh
6
7
Clock Suspend
X
Exit Clock Suspend
All Banks Idle
COMMAND INHIBIT or NOP
Power-Down Entry
All Banks Idle
AUTO REFRESH
Self Refresh Entry
Reading or Writing
VALID
NOTES
Clock Suspend Entry
See Truth Table 3
NOTE: 1.
2.
3.
4.
5.
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
Current state is the state of the SDRAM immediately prior to clock edge n.
COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
All states and sequences not shown are illegal or reserved.
Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1
(provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT
or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP
commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at
clock edge n + 1.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
27
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©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS#CAS# WE#
Any
COMMAND (ACTION)
NOTES
H
X
X
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
H
H
NO OPERATION (NOP/Continue previous operation)
L
L
H
H
ACTIVE (Select and activate row)
L
L
L
H
AUTO REFRESH
7
L
L
L
L
LOAD MODE REGISTER
7
L
L
H
L
PRECHARGE
11
L
H
L
H
READ (Select column and start READ burst)
10
Row Active
L
H
L
L
WRITE (Select column and start WRITE burst)
10
L
L
H
L
PRECHARGE (Deactivate row in bank or banks)
8
Read
L
H
L
H
READ (Select column and start new READ burst)
10
(Auto
L
H
L
L
WRITE (Select column and start WRITE burst)
10
Precharge
L
L
H
L
PRECHARGE (Truncate READ burst, start PRECHARGE)
Idle
8
Disabled)
L
H
H
L
BURST TERMINATE
9
Write
L
H
L
H
READ (Select column and start READ burst)
10
(Auto
L
H
L
L
WRITE (Select column and start new WRITE burst)
10
Precharge
L
L
H
L
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
8
Disabled)
L
H
H
L
BURST TERMINATE
9
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses
and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to
Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is
met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is
met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends
when tRP has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends
when tRP has been met. Once tRP is met, the bank will be in the idle state.
(Continued on next page)
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
28
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©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands
must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once
t
RC is met, the SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has
been met. Once tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once
t
RP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
Any
Idle
COMMAND (ACTION)
H
X
X
X
COMMAND INHIBIT (NOP/Continue previous operation)
L
H
H
H
NO OPERATION (NOP/Continue previous operation)
X
X
X
X
Any Command Otherwise Allowed to Bank m
NOTES
Row
L
L
H
H
ACTIVE (Select and activate row)
Activating,
L
H
L
H
READ (Select column and start READ burst)
7
Active, or
L
H
L
L
WRITE (Select column and start WRITE burst)
7
Precharging
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (Select and activate row)
(Auto
L
H
L
H
READ (Select column and start new READ burst)
7, 10
Precharge
L
H
L
L
WRITE (Select column and start WRITE burst)
7, 11
Disabled)
L
L
H
L
PRECHARGE
Write
L
L
H
H
ACTIVE (Select and activate row)
9
(Auto
L
H
L
H
READ (Select column and start READ burst)
7, 12
Precharge
L
H
L
L
WRITE (Select column and start new WRITE burst)
7, 13
Disabled)
L
L
H
L
PRECHARGE
Read
L
L
H
H
ACTIVE (Select and activate row)
(With Auto
L
H
L
H
READ (Select column and start new READ burst)
7, 8, 14
7, 8, 15
Precharge)
9
L
H
L
L
WRITE (Select column and start WRITE burst)
L
L
H
L
PRECHARGE
Write
L
L
H
H
ACTIVE (Select and activate row)
(With Auto
L
H
L
H
READ (Select column and start READ burst)
7, 8, 16
L
H
L
L
WRITE (Select column and start new WRITE burst)
7, 8, 17
L
L
H
L
PRECHARGE
Precharge)
9
9
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses
and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends
when tRP has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends
when tRP has been met. Once tRP is met, the bank will be in the idle state.
(Continued on next page)
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
NOTE (continued):
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been
interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m
will interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the
WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m
will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
Voltage on VDD, VDDQ Supply
Relative to VSS ....................................... -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS ....................................... -1V to +4.6V
Operating Temperature,
TA (commercial) ................................. 0°C to +70°C
Operating Temperature,
TA (industrial) .................................. -40°C to +85°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ................................................... 1W
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 6; notes appear on page 35) (0°C ≤ TA ≤ +70°C; VDD, VDDQ = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
SUPPLY VOLTAGE
VDD, VDDQ
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
VIH
2
VDD + 0.3
V
22
INPUT LOW VOLTAGE: Logic 0; All inputs
VIL
-0.3
0.8
V
22
II
-5
5
µA
OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-5
5
µA
OUTPUT LEVELS:
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
VOH
2.4
–
V
VOL
–
0.4
V
INPUT LEAKAGE CURRENT:
Any input 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
UNITS NOTES
IDD SPECIFICATIONS AND CONDITIONS
(Notes: 1, 6, 11, 13, 33; notes appear on page 35)
(0°C ≤ TA ≤ +70°C; VDD, VDDQ = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION
SYMBOL -7E
-7G -75 -8E
OPERATING CURRENT: Active Mode;
Burst = 2; READ or WRITE; tRC = tRC (MIN); CAS latency = 3
IDD1
STANDBY CURRENT: Power-Down Mode; All banks idle;
CKE = LOW
IDD2
2
2
2
STANDBY CURRENT: Active Mode;
CKE = HIGH; CS# = HIGH; All banks active after tRCD met;
No accesses in progress
IDD3
45
45
45
OPERATING CURRENT: Burst Mode; Continuous burst;
READ or WRITE; All banks active; CAS latency = 3
AUTO REFRESH CURRENT:
CKE = HIGH; CS# = HIGH
3, 18,
19, 32
2
mA
32
35
mA
3, 12,
19, 32
IDD4
150 150 140 120
mA
3, 18,
19, 32
230 230 210 190
mA
mA
3, 12,
18, 19,
32, 34
mA
4
= tRFC (MIN); CL = 3
IDD5
tRFC
= 15.625µs; CL = 3
IDD6
3
SELF REFRESH CURRENT:
Standard
IDD7
1
CKE ≤ 0.2V
Low power (L)
IDD7
0.5
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
32
UNITS NOTES
mA
tRFC
125 125 115 95
3
3
3
1
1
1
0.5 0.5 0.5
mA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
CAPACITANCE
PARAMETER
SYMBOL
MIN
CI 1
2.5
3.5
pF
29
Input Capacitance: All other input-only pins
C I2
2.5
3.8
pF
30
Input/Output Capacitance: DQs
CIO
4.0
6.0
pF
31
Input Capacitance: CLK
MAX UNITS NOTES
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11, 33; notes appear on page 35) (0°C ≤ TA ≤ +70°C)
AC CHARACTERISTICS
PARAMETER
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
Data-out low-impedance time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
WRITE recovery time
Exit SELF REFRESH to ACTIVE command
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
-7E
-75
-7G
-8E
SYMBOL MIN MAX MIN MAX MIN MAX
MIN MAX UNITS NOTES
tAC
5.4
5.4
6
6
ns
27
tAC
5.4
6
–
6
ns
tAH
0.8
0.8
1
1
ns
tAS
1.5
1.5
2
2
ns
tCH
2.5
2.5
2.75
3
ns
tCL
2.5
2.5
2.75
3
ns
tCK
7
7.5
7
8
ns
23
tCK
7.5
10
–
10
ns
23
tCKH
0.8
0.8
1
1
ns
tCKS
1.5
1.5
2
2
ns
tCMH
0.8
0.8
1
1
ns
tCMS
1.5
1.5
2
2
ns
tDH
0.8
0.8
1
1
ns
tDS
1.5
1.5
2
2
ns
tHZ
5.4
5.4
6
6
ns
10
tHZ
5.4
6
–
7
ns
10
tLZ
1
1
1
1
ns
tOH
2.7
2.7
2.5
3
ns
tOH
1.8
1.8
1.8
1.8
ns
28
N
tRAS
37 120,000 44 120,000 42 120,000
50 120,000 ns
tRC
60
66
70
70
ns
tRCD
15
20
21
20
ns
tREF
64
64
64
64
ms
tRFC
66
66
70
70
ns
tRP
15
20
21
20
ns
tRRD
14
15
14
20
ns
tT
0.3
1.2
0.3
1.2
0.3
1.2
0.3
1.2
ns
7
tWR
1 CLK +
1 CLK +
1 CLK +
1 CLK +
–
24
7ns
7.5ns
7ns
7ns
14
15
14
15
ns
25
tXSR
67
75
77
80
ns
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 35) (0°C ≤ TA ≤ +70°C)
PARAMETER
SYMBOL
tCCD
READ/WRITE command to READ/WRITE command
t
CKE to clock disable or power-down entry mode
CKED
tPED
CKE to clock enable or power-down exit setup mode
t
DQM to input data delay
DQD
tDQM
DQM to data mask during WRITEs
tDQZ
DQM to data high-impedance during READs
t
WRITE command to input data delay
DWD
tDAL
Data-in to ACTIVE command
tDPL
Data-in to PRECHARGE command
t
Last data-in to burst STOP command
BDL
tCDL
Last data-in to new READ/WRITE command
tRDL
Last data-in to PRECHARGE command
t
LOAD MODE REGISTER command to ACTIVE or REFRESH command
MRD
tROH
Data-out to high-impedance from PRECHARGE command
CL = 3
tROH
CL = 2
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
34
-7G
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
-7E
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
-7
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
-75
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
-8E
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
UNITS
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
NOTES
17
14
14
17
17
17
17
15, 21
16, 21
17
17
16, 21
26
17
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
NOTES
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
18. The IDD current will decrease as the CAS latency is
reduced. This is due to the fact that the maximum
cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on tCK = 143 MHz for -7E/-7G, 133 MHz for
-75 and 100 MHz for -8E.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width ≤ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during access or precharge states (READ, WRITE, including
tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (tRP) begins 7.5ns/7ns after the first clock
delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -7E/-75 at CL = 3 with no load is 4.6ns and
is guaranteed by design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. tCK = 7ns for -7E/-7G, 7.5ns for -75 and 10ns
for -8E.
33. For -7G, VDD (MIN) = 3.15V, TA (MAX) = 55°C.
34. CKE is HIGH during refresh command period (tRFC
[MIN]) else CKE is LOW. The IDD6 limit is actually
a nominal value and does not result in a fail value.
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V;
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.
3. IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C ≤ TA ≤ +70°C) is
ensured.
6. An initial pause of 100µs is required after power-up,
followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and
VDDQ must be powered up simultaneously. VSS and
VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated
any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH
and VIL (or between VIL and VIH) in a monotonic
manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
(-7G @ 30pF)
10. tHZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V,
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at VIL (MAX) and VIL (MIN)
and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no
more than once every two clocks and are otherwise
at valid VIH or VIL levels.
13. IDD specifications are tested after the device is
properly initialized.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
1
INITIALIZE AND LOAD MODE REGISTER
T0
CLK
((
))
CKE
((
))
((
))
COMMAND
((
))
((
))
tCK
T1
tCKH
tCKS
Tn + 1
((
))
((
))
((
))
((
))
tCH
tCMH tCMS
((
))
NOP
NOP
((
))
AUTO
REFRESH
AUTO
REFRESH
((
))
NOP
NOP
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0, BA1
((
))
((
))
DQ
((
))
ALL BANKS
SINGLE BANK
ALL
BANKS
High-Z
Tp + 3
((
))
((
))
((
))
DQM /
DQML, DQMH
Tp + 2
tCMH tCMS
((
))
PRECHARGE
((
))
NOP
Tp + 1
((
))
((
))
((
))
((
))
((
))
tCMH tCMS
To + 1
tCL
LOAD MODE
REGISTER
tAS
NOP
ACTIVE
tAH
ROW
CODE
tAS
tAH
ROW
CODE
BANK
((
))
T = 100µs
MIN
tRP
Power-up:
VDD and
CLK stable
tRFC
Precharge
all banks
tRFC
tMRD
Program Mode Register 2, 3, 4
AUTO REFRESH
AUTO REFRESH
DON’T CARE
TIMING PARAMETERS
SYMBOL* MIN
tAH
0.8
tAS
-7E
MAX
MIN
0.8
-75
MAX
MIN
1
-8E
MAX
UNITS
ns
SYMBOL* MIN
tCKS
MIN
-8E
MAX
UNITS
2
1
2
ns
ns
ns
2
66
2
66
2
70
tCK
tRFC
tRP
15
20
20
ns
2
3
ns
ns
tCMH
2.5
7
7.5
2.5
7.5
10
3
8
10
ns
ns
ns
tMRD3
(3)
tCK (2)
tCKH
0.8
0.8
1
ns
tCK
-75
MAX
1.5
0.8
1.5
1.5
2.5
tCL
MIN
1.5
0.8
1.5
1.5
2.5
tCH
-7E
MAX
tCMS
ns
*CAS latency indicated in parentheses.
NOTE: 1.
2.
3.
4.
If CS# is HIGH at clock HIGH time, all commands applied are NOP, with CKE a “Don’t Care.”
The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
JEDEC and PC100 specify three clocks.
Outputs are guaranteed High-Z after command is issued.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
POWER-DOWN MODE
T0
T1
T2
tCK
CLK
tCH
CKE
tCKS
Tn + 2
tCKS
((
))
tCKH
tCMS tCMH
COMMAND
Tn + 1
((
))
((
))
tCL
tCKS
1
PRECHARGE
NOP
((
))
((
))
NOP
NOP
ACTIVE
DQM /
DQML, DQMH
((
))
((
))
A0-A9, A11
((
))
((
))
ROW
((
))
((
))
ROW
((
))
((
))
BANK
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
tAH
BANK(S)
High-Z
((
))
DQ
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
TIMING PARAMETERS
SYMBOL* MIN
tAH
tAS
tCH
tCL
tCK
(3)
-7E
MAX
MIN
-75
MAX
MIN
-8E
MAX
UNITS
SYMBOL* MIN
-7E
MAX
MIN
-75
MAX
MIN
-8E
MAX
UNITS
0.8
1.5
0.8
1.5
1
2
ns
ns
tCK
(2)
tCKH
7.5
0.8
10
0.8
10
1
ns
ns
2.5
2.5
7
2.5
2.5
7.5
3
3
8
ns
ns
ns
tCKS
1.5
0.8
1.5
1.5
0.8
1.5
2
1
2
ns
ns
ns
tCMH
tCMS
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
CLOCK SUSPEND MODE
T0
T1
T2
tCK
CLK
T3
T4
1
T5
T6
T7
T8
NOP
WRITE
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
tCMS tCMH
DQM /
DQML, DQMH
A0-A9, A11
tAS
tAH
COLUMN m 2
tAS
COLUMN e 2
tAH
A10
tAS
BA0, BA1
tAH
BANK
BANK
tAC
tOH
tAC
DQ
tHZ
DOUT m
tLZ
tDS
DOUT m + 1
tDH
DOUT e
DOUT e + 1
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL* MIN
tAC (3)
tAC (2)
tAH
0.8
tAS
1.5
tCH
tCL
tCK
(3)
(2)
tCKH
tCK
-7E
MAX
5.4
5.4
MIN
-75
MAX
5.4
6
MIN
-8E
MAX
6
6
0.8
1.5
1
2
UNITS
ns
ns
ns
ns
SYMBOL* MIN
tCKS
1.5
tCMH
0.8
tCMS
1.5
tDH
0.8
2.5
2.5
2.5
2.5
3
3
ns
ns
tDS
tHZ
(3)
7
7.5
0.8
7.5
10
0.8
8
10
1
ns
ns
ns
tHZ
(2)
tLZ
tOH
-7E
MAX
1.5
MIN
1.5
0.8
1.5
0.8
-75
MAX
1.5
5.4
6
6
1
2.7
-8E
MAX
2
5.4
5.4
1
2.7
MIN
2
1
2
1
7
1
3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
AUTO REFRESH MODE
T0
CLK
T1
T2
t CK
Tn + 1
((
))
((
))
t CH
((
))
((
))
t CL
((
))
To + 1
((
))
CKE
t CKS
t CKH
t CMS
t CMH
COMMAND
PRECHARGE
((
))
( ( NOP
))
AUTO
REFRESH
NOP
NOP
NOP
((
))
((
))
DQM /
DQML, DQMH
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
t AS
BA0, BA1
DQ
AUTO
REFRESH
((
))
( ( NOP
))
ACTIVE
((
))
((
))
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
t AH
BANK(S)
((
))
((
))
((
))
((
))
((
))
((
))
High-Z
t RP
t RFC1
BANK
t RFC1
Precharge all
active banks
DON’T CARE
TIMING PARAMETERS
SYMBOL* MIN
tAH
0.8
tAS
tCH
tCL
tCK
(3)
tCK (2)
-7E
MAX
MIN
0.8
-75
MAX
MIN
1
-8E
MAX
UNITS
ns
SYMBOL* MIN
tCKH
-7E
MAX
MIN
-75
MAX
MIN
-8E
MAX
UNITS
0.8
1.5
0.8
0.8
1.5
0.8
1
2
1
ns
ns
ns
tRFC
1.5
66
1.5
66
2
70
ns
ns
tRP
15
20
20
ns
1.5
2.5
1.5
2.5
2
3
ns
ns
tCKS
2.5
7
7.5
2.5
7.5
10
3
8
10
ns
ns
ns
tCMS
tCMH
*CAS latency indicated in parentheses.
NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
SELF REFRESH MODE
T0
T1
CLK
tCK
tCL
tCH
T2
tCKS
> tRAS
CKE
COMMAND
Tn + 1
((
))
((
))
((
))
((
))
((
))
tCKS
tCKH
tCMS
tCMH
PRECHARGE
((
))
((
))
AUTO
REFRESH
NOP
A0-A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
SINGLE BANK
BA0, BA1
DQ
AUTO
REFRESH
))
((
))
((
))
tAS
tCKS
((
))
DQM /
DQML, DQMH
ALL BANKS
To + 2
NOP ( (
((
))
((
))
A10
To + 1
((
))
((
))
tAH
BANK(S)
High-Z
tRP
Precharge all
active banks
tXSR
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
TIMING PARAMETERS
SYMBOL* MIN
tAH
tAS
tCH
tCL
tCK
(3)
tCK
(2)
tCKH
-7E
MAX
MIN
-75
MAX
MIN
-8E
MAX
UNITS
SYMBOL* MIN
0.8
1.5
0.8
1.5
1
2
ns
ns
tCKS
2.5
2.5
7
2.5
2.5
7.5
3
3
8
ns
ns
ns
tCMS
tRP
1.5
37
15
7.5
0.8
10
0.8
10
1
ns
ns
tXSR
67
tCMH
tRAS
-7E
MAX
1.5
0.8
MIN
-75
MAX
1.5
0.8
120,000
1.5
44
20
75
MIN
-8E
MAX
2
1
120,000
2
50
20
80
UNITS
ns
ns
120,000
ns
ns
ns
ns
*CAS latency indicated in parentheses.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
READ – WITHOUT AUTO PRECHARGE
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
NOP
1
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
PRECHARGE
tCMS tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
COLUMN m2
ROW
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANKS
BANK
BANK(S)
BANK
tAC
tOH
tAC
DQ
tRCD
tAC
tAC
tOH
DOUT m
tLZ
DOUT m+1
BANK
tOH
tOH
DOUT m+2
DOUT m+3
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL* MIN
-7E
MAX
tAC
(3)
tAC (2)
tAH
tAS
MIN
MIN
SYMBOL* MIN
tCMH
0.8
0.8
1.5
1
2
2.5
2.5
2.5
2.5
3
3
ns
ns
tLZ
(3)
tCK (2)
tCKH
7
7.5
0.8
7.5
10
0.8
8
10
1
ns
ns
ns
tRAS
tCKS
1.5
1.5
2
ns
tRP
tCK
6
6
UNITS
0.8
1.5
tCL
5.4
6
-8E
MAX
ns
ns
ns
ns
tCH
5.4
5.4
-75
MAX
tCMS
tHZ
(3)
tHZ
(2)
tOH
tRC
tRCD
-7E
MAX
1.5
MIN
0.8
1.5
5.4
15
15
-8E
MAX
2
6
6
1
2.7
120,000
MIN
1
5.4
5.4
1
2.7
37
60
-75
MAX
44
66
20
20
50
70
ns
ns
7
ns
ns
ns
120,000
ns
ns
1
3
120,000
UNITS
ns
20
20
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
READ – WITH AUTO PRECHARGE
T0
T1
T2
tCK
CLK
tCKS
T3
T4
T5
NOP
NOP
1
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
COLUMN m 2
ROW
tAS
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
ROW
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
tLZ
tRCD
tAC
tOH
DOUT m
tAC
tOH
DOUT m + 1
tOH
DOUT m + 2
DOUT m + 3
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL* MIN
-7E
MAX
tAC
(3)
tAC (2)
tAH
tAS
tCH
tCL
tCK
(3)
tCK
(2)
tCKH
tCKS
MIN
5.4
5.4
-75
MAX
MIN
5.4
6
-8E
MAX
6
6
-7E
UNITS
SYMBOL* MIN
tCMH
0.8
tCMS
1.5
ns
ns
-75
MAX
MIN
0.8
1.5
0.8
1.5
2.5
0.8
1.5
2.5
1
2
3
ns
ns
ns
tHZ
tLZ
1
1
2.5
7
2.5
7.5
3
8
ns
ns
tOH
2.7
37
2.7
44
7.5
0.8
1.5
10
0.8
1.5
10
1
2
ns
ns
ns
tRC
tHZ
(3)
(2)
tRAS
tRCD
tRP
5.4
5.4
60
15
15
120,000
-8E
MAX
MIN
1
2
5.4
6
66
20
20
MAX
UNITS
ns
ns
6
7
ns
ns
ns
1
120,000
3
50
70
20
20
120,000
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
SINGLE READ – WITHOUT AUTO PRECHARGE
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
NOP3
1
T6
T7
T8
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
PRECHARGE
ACTIVE
NOP
tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
COLUMN m2
ROW
ROW
DISABLE AUTO PRECHARGE
tAH
SINGLE BANKS
BANK
BANK
tOH
tAC
DQ
DOUT m
tLZ
tRCD
BANK
BANK(S)
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL* MIN
tAC (3)
tAC
-7E
MAX
5.4
MIN
-75
MAX
5.4
MIN
-8E
MAX
6
UNITS
ns
SYMBOL* MIN
tCMH
0.8
0.8
0.8
1
ns
ns
tCMS
tAH
tHZ
(3)
tAS
1.5
2.5
2.5
1.5
2.5
2.5
2
3
3
ns
ns
ns
tHZ
(2)
7
7.5
7.5
10
8
10
ns
ns
tRAS
0.8
1.5
0.8
1.5
1
2
ns
ns
tRCD
(2)
tCH
tCL
tCK
tCK
(3)
(2)
tCKH
tCKS
5.4
6
6
tLZ
tOH
tRC
tRP
-7E
MAX
1.5
MIN
0.8
1.5
5.4
15
15
-8E
MAX
2
6
6
1
2.7
120,000
MIN
1
5.4
5.4
1
2.7
37
60
-75
MAX
44
66
20
20
50
70
ns
ns
7
ns
ns
ns
120,000
ns
ns
1
3
120,000
UNITS
ns
20
20
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
3. PRECHARGE command not allowed else tRAS would be violated.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
1
SINGLE READ – WITH AUTO PRECHARGE
T0
T1
T2
tCK
CLK
tCKS
T3
T4
T5
T6
T7
T8
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP3
NOP
NOP3
READ
tCMS
NOP
NOP
ACTIVE
NOP
tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
COLUMN m2
ROW
tAS
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
ROW
tAH
BANK
BANK
BANK
tAC
t OH
DOUT m
DQ
tRCD
CAS Latency
tHZ
tRP
tRAS
tRC
DON T CARE
UNDEFINED
TIMING PARAMETERS
-7E
SYMBOL* MIN
tAC (3)
tAC (2)
tAH
tAS
tCH
tCL
tCK
(3)
tCK
(2)
tCKH
tCKS
MAX
5.4
5.4
-75
MIN
MAX
5.4
6
-8E
MIN
MAX
6
6
-7E
UNITS
ns
ns
SYMBOL* MIN
tCMH
0.8
tCMS
1.5
-75
MAX
MIN
0.8
1.5
0.8
1.5
2.5
0.8
1.5
2.5
1
2
3
ns
ns
ns
tHZ
tLZ
1
1
2.5
7
2.5
7.5
3
8
ns
ns
tOH
2.7
37
2.7
44
7.5
0.8
1.5
10
0.8
1.5
10
1
2
ns
ns
ns
tRC
tHZ
(3)
(2)
tRAS
tRCD
tRP
5.4
5.4
60
15
15
120,000
-8E
MAX
MIN
1
2
5.4
6
66
20
20
MAX
UNITS
ns
ns
6
7
ns
ns
ns
1
120,000
3
50
70
20
20
120,000
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
3. READ command not allowed else tRAS would be violated.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
ALTERNATING BANK READ ACCESSES
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
ACTIVE
1
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
tAS
tAH
tAS
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
A10
BA0, BA1
COLUMN m 2
ROW
ROW
ROW
tAH
BANK 0
BANK 0
BANK 3
tAC
tOH
tAC
DQ
tLZ
tRCD - BANK 0
BANK 3
DOUT m
tAC
tOH
BANK 0
tAC
tOH
DOUT m + 1
tAC
tOH
DOUT m + 2
tAC
tOH
DOUT m + 3
DOUT b
tRCD - BANK 0
tRP - BANK 0
CAS Latency - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 3
tRRD
CAS Latency - BANK 3
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL* MIN
tAC (3)
tAC
-7E
MAX
5.4
(2)
MIN
MIN
SYMBOL* MIN
tCMH
tCMS
0.8
0.8
1
tAS
1.5
2.5
2.5
1.5
2.5
2.5
2
3
3
ns
ns
ns
tOH
tCK
(3)
tCK (2)
7
7.5
7.5
10
8
10
ns
ns
tRCD
tCKH
0.8
1.5
0.8
1.5
1
2
ns
ns
tCKS
6
-7E
UNITS
ns
tAH
tCL
6
-8E
MAX
6
ns
ns
tCH
5.4
-75
MAX
5.4
tLZ
tRAS
tRC
MAX
0.8
1.5
1
2.7
37
-75
MIN
MAX
0.8
1.5
1
120,000
2.7
44
-8E
MIN
MAX
1
2
1
120,000
3
50
UNITS
ns
ns
ns
120,000
ns
ns
tRP
60
15
15
66
20
20
70
20
20
ns
ns
ns
tRRD
14
15
20
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
1
READ – FULL-PAGE BURST
T0
T1
T2
tCL
CLK
T3
T4
T5
T6
((
))
((
))
tCK
tCH
tCKS
tCMH
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
tAS
tAH
tAH
NOP
BURST TERM
NOP
NOP
((
))
((
))
ROW
tAS
((
))
((
))
((
))
((
))
COLUMN m 2
ROW
tAS
BA0, BA1
Tn + 4
((
))
((
))
DQM /
DQML, DQMH
A10
Tn + 3
((
))
((
))
tCMS
A0-A9, A11
Tn + 2
tCKH
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tAC
tAC
tOH
DOUT m
DQ
tLZ
tRCD
tAC
tAC ( (
tOH ) )
tOH
DOUT m+1
tAC
tAC
tOH
((
))
DOUT m+2
((
))
tOH
DOUT m-1
tOH
DOUT m
DOUT m+1
tHZ
256 (x16) locations within same row
512 (x8) locations within same row
1,024 (x4) locations within same row
CAS Latency
DON’T CARE
Full page completed
UNDEFINED
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
TIMING PARAMETERS
-7E
SYMBOL* MIN
tAC
(3)
tAC (2)
tAH
tAS
tCH
tCL
tCK
(3)
(2)
tCKH
tCK
-75
MAX
MIN
5.4
5.4
-8E
MAX
MIN
-7E
MAX
UNITS
6
6
tCKS
5.4
6
SYMBOL* MIN
-75
MAX
-8E
MAX
MAX
UNITS
ns
ns
ns
ns
0.8
1.5
0.8
1.5
1
2
tHZ
(3)
5.4
5.4
6
2.5
2.5
2.5
2.5
3
3
ns
ns
tHZ
(2)
5.4
6
7
tLZ
1
1
1
ns
ns
7
7.5
0.8
7.5
10
0.8
8
10
1
ns
ns
ns
tOH
2.7
15
2.7
20
3
20
ns
ns
tCMS
tRCD
1.5
0.8
1.5
MIN
ns
ns
ns
ns
tCMH
1.5
0.8
1.5
MIN
2
1
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
3. Page left open; no tRP.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
READ – DQM OPERATION
T0
T1
T2
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T3
T4
NOP
NOP
1
T5
T6
T7
T8
NOP
NOP
NOP
tCL
tCH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
COLUMN m 2
ROW
tAS
tAH
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
DQ
DOUT m
tLZ
tRCD
tAC
tOH
tAC
tOH
tOH
DOUT m + 2
DOUT m + 3
tLZ
tHZ
tHZ
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL* MIN
tAC (3)
tAC (2)
tAH
-7E
MAX
5.4
5.4
MIN
-75
MAX
5.4
6
MIN
-8E
MAX
6
6
UNITS
ns
ns
SYMBOL* MIN
-7E
MAX
MIN
-75
MAX
MIN
-8E
MAX
1.5
1.5
2
ns
tCMH
0.8
1.5
0.8
1.5
1
2
ns
ns
ns
0.8
1.5
0.8
1.5
1
2
ns
ns
tCMS
tHZ
(3)
5.4
5.4
6
2.5
2.5
7.5
3
3
8
ns
ns
ns
tHZ
(2)
5.4
6
7
(3)
2.5
2.5
7
(2)
tCKH
7.5
0.8
10
0.8
10
1
ns
ns
tRCD
tAS
tCH
tCL
tCK
tCK
UNITS
tCKS
tLZ
1
1
1
ns
ns
tOH
2.7
15
2.7
20
3
20
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
WRITE – WITHOUT AUTO PRECHARGE
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
NOP
NOP
NOP
1
T6
T7
T8
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
tCMS tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
COLUMN m 3
ROW
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
BANK
tDH
DIN m + 3
t WR 2
tRCD
tRAS
tRP
tRC
DON’T CARE
TIMING PARAMETERS
SYMBOL* MIN
tAH
0.8
tAS
1.5
tCH
-7E
MAX
MIN
0.8
1.5
-75
MAX
MIN
1
2
-8E
MAX
UNITS
ns
ns
SYMBOL* MIN
tCMS
1.5
tDH
0.8
2.5
2.5
2.5
2.5
3
3
ns
ns
tDS
(3)
(2)
tCKH
7
7.5
0.8
7.5
10
0.8
8
10
1
ns
ns
ns
tRC
tCKS
1.5
0.8
1.5
0.8
2
1
ns
ns
tCL
tCK
tCK
tCMH
tRAS
1.5
37
-7E
MAX
120,000
MIN
1.5
0.8
1.5
44
-75
MAX
MIN
2
1
120,000
2
50
-8E
MAX
120,000
UNITS
ns
ns
ns
ns
tRP
60
15
15
66
20
20
70
20
20
ns
ns
ns
tWR
14
15
15
ns
tRCD
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
WRITE – WITH AUTO PRECHARGE
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
1
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
tDS
BANK
tDS
tDH
DIN m
DQ
tDH
tDS
DIN m + 1
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
tRAS
tRP
tWR
tRC
DON’T CARE
TIMING PARAMETERS
SYMBOL* MIN
tAH
0.8
tAS
1.5
tCH
2.5
tCL
-7E
MAX
MIN
0.8
1.5
2.5
-75
MAX
MIN
1
2
3
-8E
MAX
7E
UNITS
ns
ns
ns
SYMBOL* MIN
UNITS
ns
tDH
0.8
0.8
1
ns
tDS
1.5
37
60
1.5
44
66
2
50
70
tRAS
10
0.8
1.5
10
1
2
ns
ns
ns
tRCD
tCKS
7.5
0.8
1.5
tCMH
0.8
0.8
1
ns
(2)
-8E
MAX
2
ns
ns
tCKH
MIN
1.5
3
8
(3)
-75
MAX
1.5
2.5
7.5
tCK
MIN
tCMS
2.5
7
tCK
MAX
tRC
tRP
tWR
120,000
120,000
120,000
ns
ns
ns
15
15
20
20
20
20
ns
ns
1 CLK +
7ns
1 CLK +
7.5ns
1 CLK +
7ns
–
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
SINGLE WRITE – WITHOUT AUTO PRECHARGE
T0
tCK
CLK
T1
T2
tCL
T3
T4
NOP 4
NOP 4
T5
1
T6
T7
T8
ACTIVE
NOP
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
tCMS tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
COLUMN m 3
ROW
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tRP
t WR 2
tRC
DON’T CARE
TIMING PARAMETERS
SYMBOL* MIN
tAH
-7E
MAX
MIN
-75
MAX
MIN
-8E
MAX
UNITS
SYMBOL* MIN
-7E
MAX
MIN
-75
MAX
MIN
-8E
MAX
UNITS
0.8
1.5
0.8
1.5
1
2
ns
ns
tCMS
2.5
2.5
7.5
3
3
8
ns
ns
ns
tDS
(3)
2.5
2.5
7
(2)
tCKH
7.5
0.8
10
0.8
10
1
ns
ns
tRCD
tRP
15
15
20
20
20
20
ns
ns
tCKS
1.5
0.8
1.5
0.8
2
1
ns
ns
tWR
14
15
15
ns
tAS
tCH
tCL
tCK
tCK
tCMH
tDH
tRAS
tRC
1.5
0.8
1.5
37
60
1.5
0.8
120,000
1.5
44
66
2
1
120,000
2
50
70
ns
ns
120,000
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
4. PRECHARGE command not allowed else tRAS would be violated.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
SINGLE WRITE – WITH AUTO PRECHARGE
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
tCL
T2
1
T3
T4
T5
T6
T7
NOP3
WRITE
NOP
NOP
NOP
T8
T9
tCH
CKE
COMMAND
NOP3
ACTIVE
NOP3
tCMS
NOP
ACTIVE
tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tRP
tWR
tRC
DON’T CARE
TIMING PARAMETERS
SYMBOL* MIN
tAH
0.8
tAS
1.5
tCH
2.5
tCL
-7E
MAX
MIN
0.8
1.5
2.5
-75
MAX
MIN
1
2
3
-8E
MAX
7E
UNITS
ns
ns
ns
SYMBOL* MIN
UNITS
ns
tDH
0.8
0.8
1
ns
tDS
1.5
37
60
1.5
44
66
2
50
70
tRAS
10
0.8
1.5
10
1
2
ns
ns
ns
tRCD
tCKS
7.5
0.8
1.5
tCMH
0.8
0.8
1
ns
(2)
-8E
MAX
2
ns
ns
tCKH
MIN
1.5
3
8
(3)
-75
MAX
1.5
2.5
7.5
tCK
MIN
tCMS
2.5
7
tCK
MAX
tRC
tRP
tWR
120,000
120,000
120,000
ns
ns
ns
15
15
20
20
20
20
ns
ns
1 CLK +
7ns
1 CLK +
7.5ns
1 CLK +
7ns
–
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
3. WRITE command not allowed else tRAS would be violated.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
ALTERNATING BANK WRITE ACCESSES
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
1
T6
T7
T8
T9
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
ACTIVE
NOP
WRITE
tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAS
A10
COLUMN m 2
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
tDS
BANK 1
tDH
DIN m
DQ
tDS
tDH
tDS
DIN m + 1
BANK 1
tDH
tDS
DIN m + 2
tDH
tDS
DIN m + 3
tDH
BANK 0
tDS
DIN b
tWR - BANK 0
tRCD - BANK 0
tDH
tDS
DIN b + 1
tDH
tDS
DIN b + 2
tDH
DIN b + 3
tRCD - BANK 0
tRP - BANK 0
tRAS - BANK 0
tRC - BANK 0
tWR - BANK 1
tRCD - BANK 1
tRRD
DON’T CARE
TIMING PARAMETERS
7E
SYMBOL* MIN
tAH
MAX
MIN
-75
MAX
MIN
-8E
MAX
UNITS
SYMBOL* MIN
0.8
1.5
0.8
1.5
1
2
ns
ns
tDH
2.5
2.5
7.5
3
3
8
ns
ns
ns
tRAS
(3)
2.5
2.5
7
tCK
(2)
tCKH
7.5
0.8
10
0.8
10
1
ns
ns
tRP
tCKS
1.5
0.8
1.5
1.5
0.8
1.5
2
1
2
ns
ns
ns
tWR
tAS
tCH
tCL
tCK
tCMH
tCMS
tDS
tRC
tRCD
tRRD
-7E
MAX
0.8
1.5
37
60
MIN
-75
MAX
0.8
1.5
120,000
44
66
MIN
-8E
MAX
1
2
120,000
50
70
UNITS
ns
ns
120,000
ns
ns
15
15
14
20
20
15
20
20
20
ns
ns
ns
1 CLK +
7ns
1 CLK +
7.5ns
1 CLK +
7ns
–
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
WRITE – FULL-PAGE BURST
T0
T1
T2
tCL
CLK
T3
T4
T5
((
))
((
))
tCK
tCH
tCKS
tCKH
COMMAND
tCMH
ACTIVE
NOP
WRITE
NOP
NOP
NOP
tCMS tCMH
A0-A9, A11
tAH
tAH
tAS
BA0, BA1
NOP
BURST TERM
NOP
((
))
((
))
ROW
A10
((
))
((
))
((
))
((
))
COLUMN m 1
ROW
tAS
Tn + 3
((
))
((
))
DQM /
DQML, DQMH
tAS
Tn + 2
((
))
((
))
CKE
tCMS
Tn + 1
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
tDS
DIN m + 1
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
((
))
((
))
tDS
tDH
tDS
tDH
DIN m - 1
Full-page burst does
not self-terminate. Can
use BURST TERMINATE
command to stop.2, 3
256 (x16) locations within same row
512 (x8) locations within same row
1,024 (x4) locations within same row
DON’T CARE
Full page completed
TIMING PARAMETERS
SYMBOL* MIN
tAH
-7E
MAX
MIN
-75
MAX
MIN
-8E
MAX
-7E
UNITS
SYMBOL* MIN
tCKS
1.5
tCMH
0.8
0.8
1.5
0.8
1.5
1
2
ns
ns
2.5
2.5
7.5
3
3
8
ns
ns
ns
tCMS
(3)
2.5
2.5
7
(2)
tCKH
7.5
0.8
10
0.8
10
1
ns
ns
tRCD
tAS
tCH
tCL
tCK
tCK
tDH
tDS
MAX
-75
MIN
1.5
0.8
MAX
-8E
MIN
2
1
MAX
UNITS
ns
ns
1.5
0.8
1.5
0.8
2
1
ns
ns
1.5
15
1.5
20
2
20
ns
ns
*CAS latency indicated in parentheses.
NOTE: 1. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
2. tWR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
53
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
WRITE – DQM OPERATION
T0
T1
tCK
CLK
T2
1
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM /
DQML, DQMH
tAS
A0-A9, A11
tAH
COLUMN m 2
ROW
tAS
tAH
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
tAH
DISABLE AUTO PRECHARGE
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
tDS
DIN m + 2
tDH
DIN m + 3
tRCD
DON’T CARE
TIMING PARAMETERS
SYMBOL* MIN
tAH
0.8
tAS
1.5
tCH
tCL
tCK
(3)
tCK (2)
tCKH
-7E
MAX
MIN
0.8
1.5
-75
MAX
MIN
1
2
-8E
MAX
UNITS
ns
ns
SYMBOL* MIN
-7E
MAX
MIN
-75
MAX
MIN
-8E
MAX
UNITS
tCKS
1.5
1.5
2
ns
tCMH
0.8
1.5
0.8
0.8
1.5
0.8
1
2
1
ns
ns
ns
1.5
15
1.5
20
2
20
ns
ns
2.5
2.5
2.5
2.5
3
3
ns
ns
tCMS
7
7.5
0.8
7.5
10
0.8
8
10
1
ns
ns
ns
tDS
tDH
tRCD
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
54-PIN PLASTIC TSOP (400 mil)
22.30 3
SEE DETAIL A
22.14 4
.71
.80 TYP
.10 (2X)
.45
.30
9
9
2.80
11.86 5
11.66 6
PIN #1 ID
10.24
7
10.08 8
.75 (2X)
.18
.13
1.00 (2X)
.25
.20
.05
.10
1.2 MAX
.60
.40
.80
TYP
DETAIL A
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2.
3.
4.
5.
6.
7.
8.
Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
22.35 for some versions.
22.09 for some versions.
11.96 for some versions.
11.56 for some versions.
10.29 for some versions.
10.03 for some versions.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
64Mb: x4, x8, x16 SDRAM
64MSDRAM.p65 – Rev. 11/99
55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.