STMicroelectronics M41T11M6F Serial real-time clock with 56 bytes of nvram Datasheet

M41T11
Serial real-time clock with 56 bytes of NVRAM
Features
■
Counters for seconds, minutes, hours, day,
date, month, years and century
■
32 KHz crystal oscillator integrating load
capacitance (12.5 pF) providing exceptional
oscillator stability and high crystal series
resistance operation
■
Serial interface supports I2C bus (100 kHz
protocol)
■
Ultra-low battery supply current of 0.8 µA (typ.
at 3 V)
■
2.0 to 5.5 V clock operating voltage
■
Automatic switchover and deselect circuitry
■
56 bytes of general purpose RAM
■
Software clock calibration to compensate
crystal deviation due to temperature
■
Automatic leap year compensation
■
Operating temperature of –40 to 85°C
■
Packaging includes a 28-lead SOIC and
SNAPHAT® top (to be ordered separately;
3.3 V to 5.0 V supply voltage only)
■
RoHS compliant
– Lead-free second level interconnect
May 2008
8
1
SO8 (M)
SNAPHAT (SH) battery & crystal
28
1
SOH28 (MH)
Rev 8
1/29
www.st.com
1
Contents
M41T11
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
3
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
Preferred initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
M41T11
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SO8 – 8-lead plastic small outline (150 mils body width) pack. mech. data . . . . . . . . . . . . 23
SOH28 – 28-lead plastic small outline, battery snaphat pack. mech. data. . . . . . . . . . . . . 24
SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, package mechanical data . . 25
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data. . . . . . 26
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
List of figures
M41T11
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
4/29
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
28-pin SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Alternate read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC testing input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SO8 – 8-lead plastic small outline package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SOH28 – 28-lead plastic small outline, battery snaphat package outline . . . . . . . . . . . . . . 24
SH – 4-pin SNAPHAT housing for 48mAh battery & crystal package outline. . . . . . . . . . . 25
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 26
M41T11
1
Description
Description
The M41T11is a low-power serial real time clock with 56 bytes of NVRAM. A built-in
32.768 kHz oscillator (external crystal controlled) and the first 8 bytes of the RAM are used
for the clock/calendar function and are configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a two-line bi-directional bus. The built-in
address register is incremented automatically after each write or read data byte.
The M41T11 clock has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply during power failures. The energy needed to
sustain the RAM and clock operations can be supplied from a small lithium coin cell.
Typical data retention time is in excess of 5 years with a 50 mA/h 3 V lithium cell. The
M41T11 is supplied in 8-lead plastic small outline package or 28-lead SNAPHAT® package.
The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT housing containing the battery and crystal. The unique
design allows the SNAPHAT battery package to be mounted on top of the SOIC package
after the completion of the surface mount process. Insertion of the SNAPHAT housing after
reflow prevents potential battery and crystal damage due to the high temperatures required
for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in tape & reel form.
For the 28-lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number is “M4TxxBR12SH” (see Table 16 on page 27).
Caution:
Do not place the SNAPHAT battery/crystal package “M4Txx-BR12SH” in conductive foam
since this will drain the lithium button-cell battery.
Figure 1.
Logic diagram
VCC
VBAT
OSCO
OSCI
SCL
M41T11
SDA
FT/OUT
VSS
AI01000
5/29
Description
M41T11
Table 1.
Signal names
OSCI
Oscillator input
OCSO
Oscillator output
FT/OUT
Figure 2.
Frequency test/output driver (open drain)
SDA
Serial data address input/output
SCL
Serial clock
VBAT
Battery supply voltage
VCC
Supply voltage
VSS
Ground
8-pin SOIC connections
M41T11
OSCI
OSCO
VBAT
VSS
1
2
3
4
8
7
6
5
VCC
FT/OUT
SCL
SDA
AI01001
Figure 3.
28-pin SOIC connections
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
28
1
2
27
3
26
4
25
5
24
6
23
7
22
M41T11
8
21
9
20
10
19
11
18
12
17
13
16
14
15
AI03606
6/29
VCC
NC
FT/OUT
NC
NC
NC
NC
NC
SCL
NC
NC
NC
SDA
NC
M41T11
Description
Figure 4.
Block diagram
1 Hz
OSCI
OSCILLATOR
32.768 kHz
DIVIDER
SECONDS
MINUTES
CENTURY/HOURS
OSCO
DAY
FT/OUT
VCC
VSS
VBAT
SCL
SDA
DATE
VOLTAGE
SENSE
and
SWITCH
CIRCUITRY
SERIAL
BUS
INTERFACE
MONTH
CONTROL
LOGIC
YEAR
CONTROL
RAM
(56 x 8)
ADDRESS
REGISTER
AI02566
7/29
Operation
2
M41T11
Operation
The M41T11 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 64 bytes
contained in the device can then be accessed sequentially in the following order:
●
1st byte: seconds register
●
2nd byte: minutes register
●
3rd byte: century/hours register
●
4th byte: day register
●
5th byte: date register
●
6th byte: month register
●
7th byte: years register
●
8th byte: control register
●
9th - 64th bytes: RAM
The M41T11 clock continually monitors VCC for an out of tolerance condition. Should VCC
fall below VSO, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out of tolerance system. When VCC falls below VSO,
the device automatically switches over to the battery and powers down into an ultra low
current mode of operation to conserve battery life. Upon power-up, the device switches from
battery to VCC at VSO and recognizes inputs.
2.1
2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is high.
●
Changes in the data line while the clock line is high will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
8/29
M41T11
2.1.3
Operation
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is called “transmitter”, the receiving device
that gets the message is called “receiver”. The device that controls the message is called
“master”. The devices that are controlled by the master are called “slaves”.
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver, whereas the master generates an extra acknowledge
related clock pulse.
A slave receiver which is addressed is obliged to generate an acknowledge after the
reception of each byte. Also, a master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case, the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 5.
Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
9/29
Operation
Figure 6.
M41T11
Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
1
DATA OUTPUT
BY TRANSMITTER
2
8
MSB
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
Figure 7.
Bus timing requirements sequence
SDA
tBUF
tHD:STA
tHD:STA
tR
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
1. P = STOP and S = START
10/29
M41T11
Operation
Table 2.
AC characteristics
Parameter(1)
Symbol
Min
Max
Unit
0
100
kHz
fSCL
SCL clock frequency
tLOW
Clock low period
4.7
µs
tHIGH
Clock high period
4
µs
tR
SDA and SCL rise time
1
µs
tF
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
tSU:STA
4
µs
START condition setup time
(only relevant for a repeated start condition)
4.7
µs
tSU:DAT
Data setup time
250
ns
tHD:DAT(2)
Data hold time
0
µs
STOP condition setup time
4.7
µs
Time the bus must be free before a new transmission can start
4.7
µs
tSU:STO
tBUF
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max.) of the falling
edge of SCL.
2.2
Read mode
In this mode, the master reads the M41T11 slave after setting the slave address (see
Figure 8). Following the write mode control bit (R/W = 0) and the acknowledge bit, the word
address An is written to the on-chip address pointer. Next the START condition and slave
address are repeated, followed by the READ mode control bit (R/W = 1). At this point, the
master transmitter becomes the master receiver. The data byte which was addressed will be
transmitted and the master receiver will send an acknowledge bit to the slave transmitter
(see Figure 9). The address pointer is only incremented on reception of an acknowledge bit.
The M41T11 slave transmitter will now place the data byte at address An + 1 on the bus. The
master receiver reads and acknowledges the new byte and the address pointer is
incremented to An + 2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T11
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 10 on page 12).
11/29
Operation
Figure 8.
M41T11
Slave address location
R/W
SLAVE ADDRESS
1
A
LSB
MSB
START
1
0
1
0
0
0
AI00602
R/W
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
ACK
BUS ACTIVITY:
S
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Read mode sequence
START
Figure 9.
STOP
SLAVE
ADDRESS
DATA n+X
P
NO ACK
AI00899
ACK
DATA n+X
P
NO ACK
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
BUS ACTIVITY:
12/29
STOP
R/W
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 10. Alternate read mode sequence
AI00895
M41T11
2.3
Operation
Write mode
In this mode the master transmitter transmits to the M41T11 slave receiver. Bus protocol is
shown in Figure 11. Following the START condition and slave address, a logic '0' (R/W = 0)
is placed on the bus and indicates to the addressed device that word address An will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41T11
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address and again after it has received the word address and each data byte.
2.4
Data retention mode
With valid VCC applied, the M41T11 can be accessed as described above with read or write
cycles. Should the supply voltage decay, the M41T11 will automatically deselect, write
protecting itself when VCC falls (see Figure 15).
SLAVE
ADDRESS
STOP
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 11. Write mode sequence
AI00591
13/29
Clock operation
3
M41T11
Clock operation
The eight byte clock register (see Table 3) is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal format. Seconds, minutes, and hours are
contained within the first three registers. Bits D6 and D7 of clock register 2 (hours register)
contain the CENTURY ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1'
will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century
(depending upon its initial state). If CEB is set to a '0', CB will not toggle. Bits D0 through D2
of register 3 contain the day (day of week). Registers 4, 5 and 6 contain the date (day of
month), month and years. The final register is the control register (this is described in the
clock calibration section). Bit D7 of register 0 contains the STOP bit (ST). Setting this bit to a
'1' will cause the oscillator to stop. If the device is expected to spend a significant amount of
time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0'
the oscillator restarts within one second.
Note:
In order to guarantee oscillator startup after the initial power-up, set the ST bit to a '1,' then
reset this bit to a '0.' This sequence enables a “kick start” circuit which aids the oscillator
startup during worst case conditions of voltage and temperature.
The seven clock registers may be read one byte at a time, or in a sequential block. The
control register (address location 7) may be accessed independently. Provision has been
made to assure that a clock update does not occur while any of the seven clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
delayed by 250 ms to allow the read to be completed before the update occurs. This will
prevent a transition of data during the read.
Note:
14/29
This 250 ms delay affects only the clock register update and does not alter the actual clock
time.
M41T11
Clock operation
Table 3.
Register map(1)
Data
Function/range
Address
D7
D6
D5
D4
D3
D2
D1
D0
BCD format
0
ST
10 seconds
Seconds
Seconds
00-59
1
X
10 minutes
Minutes
Minutes
00-59
2
CEB(2)
CB
3
X
X
X
4
X
X
10 date
5
X
X
X
6
7
10 hours
10 years
OUT
FT
S
X
10 M.
Hours
X
Day
Century/hours 0-1/00-23
Day
01-07
Date
Date
01-31
Month
Month
01-12
Years
Year
00-99
Calibration
Control
1. Keys:
S = SIGN bit
FT = FREQUENCY TEST bit
ST = STOP bit
OUT = Output level
X = Don’t care
CEB = Century enable bit
CB = Century bit
2. When CEB is set to '1', CB will toggle from '0' to '1' or from '1' to '0' every 100 years (dependent upon the
initial value set). When CEB is set to '0', CB will not toggle.When CEB is set to '1', CB will toggle from '0' to
'1' or from '1' to '0' every 100 years (dependent upon the initial value set). When CEB is set to '0', CB will
not toggle.
3.1
Clock calibration
The M41T11 is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator
frequency error at 25°C, which equates to about ±1.53 minutes per month. With the
calibration bits properly set, the accuracy of each M41T11 improves to better than ±2 ppm
at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 12 on page 17).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome trim capacitors. The M41T11 design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 13 on page 17. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five-bit calibration byte found in the control register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The calibration byte occupies the five lower order bits (D4-D0) in the control register (addr
7). This byte can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
15/29
Clock operation
M41T11
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or
–2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M41T11 may
require. The first involves simply setting the clock, letting it run for a month and comparing it
to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows
the designer to give the end user the ability to calibrate his clock as his environment may
require, even after the final product is packaged in a non-user serviceable enclosure. All the
designer has to do is provide a simple utility that accessed the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of some test equipment. When the frequency test (FT) bit, the seventh-most significant bit in
the control register, is set to a '1', and the oscillator is running at 32,768 Hz, the FT/OUT pin
of the device will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and
direction of oscillator frequency shift at the test temperature.
For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency
error, requiring a –10(XX001010) to be loaded into the calibration byte for correction. Note
that setting or changing the calibration byte does not affect the frequency test output
frequency.
3.2
Output driver pin
When the FT Bit is not set, the FT/OUT pin becomes an output driver that reflects the
contents of D7 of the control register. In other words, when D6 of location 7 is a zero and D7
of location 7 is a zero and then the FT/OUT pin will be driven low.
Note: The FT/OUT pin is open drain which requires an external pull-up resistor.
3.3
Preferred initial power-on defaults
Upon initial application of power to the device, the FT bit will be set to a '0' and the OUT bit
will be set to a '1'. All other register bits will initially power-on in a random state.
16/29
M41T11
Clock operation
Figure 12. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
ΔF = K x (T –T )2
O
F
–100
K = –0.036 ppm/°C2 ± 0.006 ppm/°C2
–120
TO = 25°C ± 5°C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999b
Figure 13. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
17/29
Maximum ratings
4
M41T11
Maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Absolute maximum ratings
Symbol
TA
TSTG
TSLD(1)
Parameter
Ambient operating temperature
Storage temperature (VCC off, oscillator off)
Value
Unit
–40 to 85
°C
SNAPHAT®
–40 to 85
SOIC
–55 to 125
°C
Lead solder temperature for 10 seconds
260
°C
VIO
Input or output voltages
–0.3 to 7
V
VCC
Supply voltage
–0.3 to 7
V
IO
Output current
20
mA
PD
Power dissipation
0.25
W
1. Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed
245°C for greater than 30 seconds).
Caution:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up
mode.
Caution:
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
18/29
M41T11
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
Table 5: Operating and AC measurement conditions. Designers should check that the
operating conditions in their projects match the measurement conditions when using the
quoted parameters.
Table 5.
Operating and AC measurement conditions(1)
Parameter
M41T11
Unit
2.0 to 5.5(2)
V
–40 to 85
°C
Load capacitance (CL)
100
pF
Input rise and fall times
≤ 50
ns
Input pulse voltages
0.2VCC to 0.8VCC
V
Input and output timing ref. voltages
0.3VCC to 0.7VCC
V
Supply voltage (VCC)
Ambient operating temperature (TA)
1. Output Hi-Z is defined as the point where data is no longer driven.
2. Supply voltage for SOH28 is 3.3V to 5.5V.
Figure 14. AC testing input/output waveform
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI02568
19/29
DC and AC parameters
Table 6.
M41T11
Capacitance
Parameter(1)(2)
Symbol
CIN
COUT(3)
tLP
Min
Max
Unit
Input capacitance (SCL)
7
pF
Output capacitance (SDA, FT/OUT)
10
pF
1000
ns
Low-pass filter input time constant (SDA and SCL)
250
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1 MHz.
3. Outputs deselected.
Table 7.
Symbol
DC characteristics
Test Condition(1)
Parameter
Min
Typ
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
Switch frequency = 100 kHz
300
µA
SCL, SDA = VCC – 0.3 V
70
µA
ILI
Input leakage current
ILO
Output leakage current
ICC1
Supply current
ICC2
Supply current (standby)
VIL
Input low voltage
–0.3
0.3VCC
V
VIH
Input high voltage
0.7VCC
VCC + 0.5
V
VOL
Output low voltage
IOL = 3 mA
0.4
V
FT/OUT
5.5
V
3
3.5(4)
V
0.8
1
µA
Pull-up supply voltage
(open drain)
VBAT(2)
Battery supply voltage
IBAT
Battery supply current
2.5(3)
TA = 25°C, VCC = 0 V,
oscillator ON, VBAT = 3 V
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted).
2. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
3. After switchover (VSO), VBAT(min) can be 2.0 V for crystal with RS = 40 KΩ.
4. For rechargeable back-up, VBAT(max) may be considered VCC.
Table 8.
Symbol
Crystal electrical characteristics
Parameter(1)(2)(3)
fO
Resonant frequency
RS
Series resistance
CL
Load capacitance
Min
Typ
Max
32.768
kHz
60
12.5
Unit
kΩ
pF
1. These values are externally supplied if using the SO8 package. STMicroelectronics recommends the KDS
DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD)
quartz crystal for industrial temperature operations. KDS can be contacted at [email protected] or
http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T11. Circuit board layout considerations for the 32.768 kHz
crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
3. All SNAPHAT® battery:crystal tops meet these specifications.
20/29
M41T11
DC and AC parameters
Figure 15. Power down/up mode AC waveforms
VCC
VSO
tPD
tREC
SDA
SCL
DON'T CARE
AI00596
Table 9.
Power down/up AC characteristics
Parameter(1)(2)
Symbol
Min
Max
Unit
tPD
SCL and SDA at VIH before power down
0
ns
tREC
SCL and SDA at VIH after power up
10
µs
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
2. VCC fall time should not exceed 5 mV/µs.
Table 10.
Power down/up trip points DC characteristics
Symbol
Parameter(1)(2)
Min
Typ
Max(3)
Unit
VSO(4)
Battery back-up switchover voltage
VBAT – 0.80
VBAT – 0.50
VBAT – 0.30
V
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
2. All voltages referenced to VSS.
3. In 3.3 V application, if initial battery voltage is ≥ 3.4 V, it may be necessary to reduce battery voltage (i.e.,
through wave soldering the battery) in order to avoid inadvertent switchover/deselection for VCC – 10%
operation.
4. Switchover and deselect point.
21/29
Package mechanical data
6
M41T11
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
22/29
M41T11
Package mechanical data
Figure 16. SO8 – 8-lead plastic small outline package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
A1
L
L1
SO-A
1. Drawing is not to scale.
Table 11.
SO8 – 8-lead plastic small outline (150 mils body width) pack. mech. data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.75
Max
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.009
ccc
0.25
0.004
0.010
0.049
0.10
0.004
D
4.90
4.80
5.00
0.193
0.189
0.197
E
6.00
5.80
6.20
0.236
0.228
0.244
E1
3.90
3.80
4.00
0.154
0.150
0.157
e
1.27
–
–
0.050
–
–
h
0.25
0.50
0.010
0.020
k
0°
8°
0°
8°
L
0.40
1.27
0.016
0.050
L1
1.04
0.041
23/29
Package mechanical data
M41T11
Figure 17. SOH28 – 28-lead plastic small outline, battery snaphat package outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
1. Drawing is not to scale.
Table 12.
SOH28 – 28-lead plastic small outline, battery snaphat pack. mech. data
mm
inches
Symb
Typ
Min
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
CP
24/29
Max
1.27
0.050
28
0.10
0.004
M41T11
Package mechanical data
Figure 18. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal package
outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHTK-A
1. Drawing is not to scale.
Table 13.
SH – 4-pin SNAPHAT housing for 48 mAh battery & crystal, package
mechanical data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
9.78
Max
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
25/29
Package mechanical data
M41T11
Figure 19. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package
outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHTK-B
1. Drawing is not to scale.
Table 14.
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package
mech. data
mm
inches
Symb
Typ
Min
A
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
0.335
A2
7.24
8.00
0.285
0.315
A3
26/29
Max
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
0.710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
M41T11
7
Part numbering
Part numbering
Table 15.
Ordering information scheme
Example:
M41T
11
M
6
E
Device type
M41T
Supply voltage
11 = VCC = 2.0 to 5.5 V(1)
Package
M = SO8 (150 mil width)
MH(2) = SOH28
Temperature range
6 = –40 to 85°C
Shipping method
E = ECOPACK® package, tubes
F = ECOPACK® package, tape & reel
1. SOH28 supply voltage is 3.3 V to 5.5 V.
2. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered separately under
the part number “M4Txx-BR12SHx” in plastic tube or “M4Txx-BR12SHxTR” in tape & reel form (see
Table 16).
Caution:
Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will
drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Table 16.
SNAPHAT battery table
Part Number
Description
Package
M4T28-BR12SH
Lithium battery (48 mAh) SNAPHAT
SH
M4T32-BR12SH
Lithium battery (120 mAh) SNAPHAT
SH
27/29
Revision history
8
M41T11
Revision history
Table 17.
28/29
Revision history
Date
Revision
Revision changes
Mar-1999
1.0
First issue
23-Dec-1999
1.1
SOH28 package added
25-Jul-2000
1.2
Crystal electrical characteristics: RS Max changed (Table 8)
12-Dec-2000
1.3
Edit VSO (Table 10)
24-Jan-2001
2.0
Reformatted
27-Feb-2001
3.0
Document status changed
17-Jul-2001
3.1
Change to DC and AC characteristics (Table 7, Table ); added
temp/voltage info. to (Table 6, Table 7, Table 8, Table , Table 9,
Table 10); added SNAPHAT battery table (Table 16).
27-Nov-2001
3.2
Features, (page 1); DC characteristics (Table 7); crystal electrical
(Table 8); power down/up trip points (Table 10) changes; add table
footnotes (Table 5, Table 10, Table 15)
21-Jan-2002
3.3
Fix table footnotes (Table 7, Table 8)
01-May-2002
3.4
Modify reflow time and temperature footnote (Table 4)
03-Jul-2002
3.5
Modify “Clock operation” text, crystal electrical characteristics table
footnote (Table 8)
07-Nov-2002
3.6
Correct figure name in Features on page 1;
15-Jun-2004
4.0
Reformatted; added Lead-free information; updated characteristics
(Figure 12; Table 4, Table 7, Table 15)
14-Dec-2004
5.0
Correct footnote (Table 8)
22-Aug-2006
6
Changed document to new template; changed title on page 1; re-ordered
text and amalgamated figures in Features on page 1; updated package
mechanical data in Section 6: Package mechanical data; amended
footnotes in Table and Table 9; Table 15 ecopack compliant; small text
changes for entire document
03-Oct-2007
7
Added lead-free second level interconnect information to cover page and
Section 6: Package mechanical data; some text changes; updated
Table 4.
02-May-2008
8
Updated Figure 16, Table 11, 15.
M41T11
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29/29