AD ADA4350 Fet input analog front end with adc driver Datasheet

FET Input Analog Front End
with ADC Driver
ADA4350
Data Sheet
FEATURES
GENERAL DESCRIPTION
Low noise, low input bias current FET input amplifier
Very low input bias current: ±0.25 pA typical at 25°C
Low input voltage noise
92 nV/√Hz typical at 10 Hz at 5 V
5 nV/√Hz typical at 100 kHz at ±5 V
Gain bandwidth product: 175 MHz
Input capacitance
3 pF typical, differential mode
2 pF typical, common mode
Integrated gain switching
Sampling and feedback switch off leakage: ±0.5 pA typical
Worst case tON/tOFF times: 105 ns typical/65 ns typical
Integrated analog-to-digital converter (ADC) driver
Differential mode and single-ended mode
Adjustable output common-mode voltage
−5 V to +3.8 V typical for ±5 V supply
Wide output voltage swing: ±4.8 V minimum for ±5 V supply
Linear output current: 18 mA rms typical for ±5 V supply
SPI or parallel switch control of all functions
Wide operating range: 3.3 V to 12 V
Quiescent current: 8.5 mA typical (±5 V full system)
The ADA4350 is an analog front end for photodetectors or other
sensors whose output produces a current proportional to the
sensed parameter or voltage input applications where the system
requires the user to select between very precise gain levels to
maximize the dynamic range.
The ADA4350 integrates a FET input amplifier, a switching network,
and an ADC driver with all functions controllable via a serial
peripheral interface (SPI) or parallel control logic into a single
IC. The FET input amplifier has very low voltage noise and current
noise making it an excellent choice to work with a wide range of
photodetectors, sensors, or precision data acquisition systems.
Its switching network allows the user individual selection of up
to six different, externally configurable feedback networks; by
using external components for the feedback network, the user
can more easily match the system to their desired photodetector or
sensor capacitance. This feature also allows the use of low thermal
drift resistors, if required.
The design of the switches minimizes error sources so that they
add virtually no error in the signal path. The output driver can
be used in either single-ended or a differential mode and is
ideal for driving the input of an ADC.
APPLICATIONS
Current to voltage (I to V) conversions
Photodiode preamplifiers
Chemical analyzers
Mass spectrometry
Molecular spectroscopy
Laser/LED receivers
Data acquisition systems
The ADA4350 can operate from a single +3.3 V supply or a dual
±5 V supply, offering user flexibility when choosing the polarity of
the detector. It is available in a Pb-free, 28-lead TSSOP package and
is specified to operate over the −40°C to +85°C temperature range.
Multifunction pin names may be referenced by their relevant
function only.
FB5
6
5
4
RF1
FB4
7
VIN1
FB3
8
SWA_OUT
FB2
9
SWB_OUT
FB0
FB1
FUNCTIONAL BLOCK DIAGRAM
27
1
28
2
ADA4350
S6
S7
S8
S0
S1
S2
IN-N 10
IN-P 11
P1
3
VOUT1
M1
26
VOUT2
S9
S10
S11
S3
S4
S5
REF
SWITCHING NETWORK
ADC DRIVER
12417-001
SDO/P2
CS/P4
25
SDI/P3
19 20 21 22 23
SCLK/P1
17
LATCH/P0
SWB_IN
FET AMP
16
EN
13
MODE
12
SWA_IN
SPI INTERFACE
Figure 1.
Rev. B
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Last Content Update: 11/01/2016
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ADA4350
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characterisitics .......................................... 17
Applications ....................................................................................... 1
Full System .................................................................................. 17
General Description ......................................................................... 1
FET Input Amplifier .................................................................. 19
Functional Block Diagram .............................................................. 1
ADC Driver ................................................................................. 22
Revision History ............................................................................... 2
Test Circuits..................................................................................... 26
Specifications..................................................................................... 3
Theory of Operation ...................................................................... 27
±5 V Full System ........................................................................... 3
Kelvin Switching Techniques .................................................... 27
±5 V FET Input Amplifier ........................................................... 4
Applications Information .............................................................. 28
±5 V Internal Switching Network and Digital Pins ................. 5
Configuring the ADA4350 .......................................................... 28
±5 V ADC Driver ......................................................................... 6
Selecting the Transimpedance Gain Paths Manually or
Through the Parallel Interface .................................................. 28
5 V Full System ............................................................................. 8
5 V FET Input Amplifier ............................................................. 9
5 V Internal Switching Network and Digital Pins .................. 10
5 V ADC Driver .......................................................................... 11
Timing Specifications ................................................................ 13
Absolute Maximum Ratings .......................................................... 15
Thermal Resistance .................................................................... 15
Maximum Power Dissipation ................................................... 15
ESD Caution ................................................................................ 15
Pin Configuration and Function Descriptions ........................... 16
Selecting the Transimpedance Gain Paths Through the
SPI Interface (Serial Mode) ....................................................... 28
SPICE Model ............................................................................... 30
Transimpedance Amplifier Design Theory ................................ 32
Transimpedance Gain Amplifier Performance ...................... 34
The Effect of Low Feedback Resistor RFx ................................ 35
Using The T Network to Implement Large Feedback
Resistor Values ............................................................................ 36
Outline Dimensions ....................................................................... 37
Ordering Guide .......................................................................... 37
REVISION HISTORY
3/16—Rev. A to Rev. B
Change to Table 15 ......................................................................... 29
12/15—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Changes to Table 5 ............................................................................ 8
Deleted Figure 4; Renumbered Sequentially ............................... 14
Changes to Table 10 ........................................................................ 15
Changes to Table 14 ........................................................................ 29
4/15—Revision 0: Initial Version
Rev. B | Page 2 of 37
Data Sheet
ADA4350
SPECIFICATIONS
±5 V FULL SYSTEM
TA = 25°C, +VS = +5 V, −VS = −5 V, RL = 1 kΩ differential, unless otherwise specified.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
HARMONIC PERFORMANCE
Harmonic Distortion (HD2/HD3)
DC PERFORMANCE
Input Bias Current
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection
OUTPUT CHARACTERISTICS
Linear Output Current
Short-Circuit Current
Settling Time to 0.1%
ANALOG POWER SUPPLY (+VS, −VS)
Operating Range
Quiescent Current
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
DIGITAL SUPPLIES
Digital Supply Range
Quiescent Current
Test Conditions/Comments
Min
Typ
Max
Unit
Gain (G) = −5, VOUT = 200 mV p-p
G = −5, VOUT = 2 V p-p
VOUT = 2 V step, 10% to 90%
20
12
60
MHz
MHz
V/µs
G = −5, fC = 100 kHz
G = −5, fC = 1 MHz
−95/−104
−77/−78
dBc
dBc
At 25°C
At 85°C
±0.25
±8
Common mode
Common mode
Differential mode
Common-mode rejection ratio (CMRR) > 80 dB
CMRR > 68 dB
VCM = ±3.0 V
100
2
3
−4.5
−5
92
VOUT = 4 V p-p, 60 dB spurious-free dynamic
range (SFDR)
Sinking/sourcing
G = −5, VOUT = 2 V step
pA
pA
104
GΩ
pF
pF
V
V
dB
18
mA rms
43/76
100
mA
ns
+3.8
+3.9
3.3
Enabled
M1 disabled (see Figure 1)
All disabled
±1
±25
8.5
7
2
90
85
12
10
V
mA
mA
µA
dB
dB
5.5
V
µA
µA
V
DVDD, DGND
3.3
Enabled
Disabled
50
0.6
≥3.3
+VS to DGND Head Room
Rev. B | Page 3 of 37
ADA4350
Data Sheet
±5 V FET INPUT AMPLIFIER
TA = 25°C, +VS = +5 V, −VS = −5 V, RL = 1 kΩ, unless otherwise specified.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Gain Bandwidth Product
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (HD2/HD3)
Input Voltage Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
Output Voltage Swing
Linear Output Current
Short-Circuit Current
POWER SUPPLY
Operating Range
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Test Conditions/Comments
Min
G = −5, VOUT = 100 mV p-p
G = −5, VOUT = 2 V p-p
Typ
Max
Unit
VOUT = 2 V step, 10% to 90%
G = −5, VOUT = 2 V step
26
24
175
100
28
MHz
MHz
MHz
V/µs
ns
f = 100 kHz, VOUT = 2 V p-p, G = −5
f = 1 MHz, VOUT = 2 V p-p, G = −5
f = 10 Hz
f = 100 kHz
−106/−114
−83/−93
85
5
dBc
dBc
nV/√Hz
nV/√Hz
From −40°C to +85°C
From 25°C to 85°C
At 25°C
At 85°C
At 25°C
At 85°C
VOUT = ±2 V
15
0.1
0.1
±0.25
±8
±0.1
±0.5
115
Common mode
Common mode
Differential mode
CMRR > 80 dB
CMRR > 68 dB
VCM = ±3 V
106
80
1.6
1.0
±1
±25
±0.8
100
2
3
−4.5
−5
92
VOUT = VS ± 10%
G = +21, RF = 1 kΩ, RL open measured at FBx
G = +21, RF = 100 kΩ, RL open measured at FBx
VOUT = 2 V p-p, 60 dB SFDR
Sinking/sourcing
−3.6 to +3.9
−4.7 to +4.8
3.3
90
90
Rev. B | Page 4 of 37
µV
µV/°C
µV/°C
pA
pA
pA
pA
dB
115
GΩ
pF
pF
V
V
V
60
−4.05 to +4.07
−4.9 to +4.86
18
41/45
ns
V
V
mA rms
mA
+3.8
+3.9
12
109
109
V
dB
dB
Data Sheet
ADA4350
±5 V INTERNAL SWITCHING NETWORK AND DIGITAL PINS
TA = 25°C, +VS = +5 V, −VS = −5 V, unless otherwise specified. See Figure 1 for feedback and sampling switches notation.
Table 3.
Parameter
FEEDBACK/SAMPLE ANALOG SWITCH
Analog Signal Range
Switch On-Resistance
Feedback
Sampling
On-Resistance Match Between Channels
Feedback Resistance
Sampling Resistance
SWITCH LEAKAGE CURRENTS
Sampling and Feedback Switch Off Leakage
DYNAMIC CHARACTERISTICS
Power-On Time
Power-Off Time
Off Isolation
Feedback Switches
Sampling Switches
Channel to Channel Crosstalk
Worst Case Switch Feedback Capacitance (Switch Off )
THRESHOLD VOLTAGES FOR DIGITAL INPUT PINS
Symbol
RON, FB
Typ
RON, S
ΔRON, FB
ΔRON, S
tOFF
VIL
V
196
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
2
2
15
14
Ω
Ω
TA = 85°C
±0.5
±40
±1.7
±120
pA
pA
DVDD = 5 V
DVDD = 3.3 V
DVDD = 5 V
DVDD = 3.3 V
RL = 50 Ω, f = 1 MHz
RL = 50 Ω, f = 1 MHz
Input Low Voltage
+5
VCM = 0 V
VCM = 0 V
CFB (OFF)
VIH
Unit
149
195
149
195
297
390
297
388
IS (OFF)
tON
Max
For S0 to S2, VCM = 0 V
TA = 85°C
For S3 to S5, VCM = 0 V
TA = 85°C
For S6 to S8, VCM = 0 V
TA = 85°C
For S9 to S11, VCM = 0 V
TA = 85°C
EN, MODE, DGND, LATCH/P0,
SCLK/P1, SDO/P2, SDI/P3, CS/P4 1
DVDD = 5 V
DVDD = 3.3 V
DVDD = 5 V
DVDD = 3.3 V
DVDD, DGND
196
356
356
76
80
86
90
ns
ns
ns
ns
−92
−118
−86
0.1
dB
dB
dB
pF
2.0
1.5
1.4
1.0
3.3
Enabled
Disabled
+VS to DGND Head Room
1
Min
−5
Input High Voltage
DIGITAL SUPPLIES
Digital Supply Range
Quiescent Current
Test Conditions/Comments
5.5
50
0.6
≥3.3
When referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specification is listed. For full pin names of
multifunction pins, refer to the Pin Configuration and Function Descriptions section.
Rev. B | Page 5 of 37
V
V
V
V
V
µA
µA
V
ADA4350
Data Sheet
±5 V ADC DRIVER
TA = 25°C, +VS = +5 V, −VS = −5 V, unless otherwise specified. See Figure 1 for the P1 and M1 amplifiers. RL = 1 kΩ when differential,
and RL = 500 Ω when single-ended.
Table 4.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Overdrive Recovery Time
Slew Rate
Settling Time 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion (HD2/HD3)
Referred to Input (RTI) Voltage Noise
Referred to Output (RTO) Voltage Noise
Input Current Noise
DC PERFORMANCE
Output Offset Voltage
Output Offset Voltage Drift
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
Gain
Gain Error
Gain Error Drift
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Test Conditions/Comments 1
Min
Typ
Max
Unit
When used differentially, VOUT = 0.1 V p-p
When used differentially, VOUT = 2.0 V p-p
When P1 is used, VOUT = 50 mV p-p
When P1 is used, VOUT = 1.0 V p-p
When M1 is used, VOUT = 50 mV p-p
When M1 is used, VOUT = 1.0 V p-p
Positive recovery/negative recovery for P1
Positive recovery/negative recovery for M1
When differentially used, VOUT = 2 V step
When P1 or M1 is single-ended, VOUT = 1 V step
When used differentially, VOUT = 2 V step
When P1 is used, VOUT = 1 V step
When M1 is used, VOUT = 1 V step
38
16
55
17
45
21
200/180
100/100
57
30
95
80
80
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
V/µs
V/µs
ns
ns
ns
When used differentially, fC = 100 kHz, VOUT = 4 V p-p
When used differentially, fC = 1 MHz, VOUT = 4 V p-p
When P1 is used, fC = 100 kHz, VOUT = 2 V p-p
When P1 is used, fC = 1 MHz, VOUT = 2 V p-p
When M1 is used, fC = 100 kHz, VOUT = 2 V p-p
When M1 is used, fC = 1 MHz, VOUT = 2 V p-p
For P1, f = 10 Hz
For P1, f = 100 kHz
For P1 and M1, f = 10 Hz , measured at VOUT2
For P1 and M1, f = 100 kHz, measured at VOUT2
f = 100 kHz, referred to P1
−105/−109
−75/−73
−112/−108
−75/−73
−98/−103
−70/−69
55
5
95
16
1.1
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
Differential
Differential
Single-ended, P1 only
Single-ended, M1 only
Single-ended, P1 only
Single-ended, M1 only
P1 only at VIN1 pin
P1 only at RF1 pin
M1 at REF pin
P1 only
P1 only, VOUT = ±2 V
M1 only
0.125
0.7
50
40
0.2
0.4
60
60
60
60
112
1.9996
102
1.99
−0.5
0.6
VIN1 and REF
VIN1 and REF
0.5
13
180
180
4.75
3.6
220
325
200
260
2.01
+0.5
1.9
200
1.4
For P1, VCM = ±3.0 V
Rev. B | Page 6 of 37
−5
82
+3.8
100
mV
µV/°C
µV
µV
µV/°C
µV/°C
nA
nA
nA
nA
dB
V/V
%
ppm/°C
MΩ
pF
V
dB
Data Sheet
Parameter
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Common-Mode Voltage Range
Linear Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
1
ADA4350
Test Conditions/Comments 1
Min
Typ
RL = no load, single-ended
RL = 500 Ω, single-ended
±4.8
±4.55
−5
±4.83
±4.6
P1 or M1, VOUT = 2 V p-p, 60 dB SFDR
Differential output, VOUT = 4 V p-p, 60 dB SFDR
P1 or M1, sinking/sourcing
When used differentially at each VOUTx, 30% overshoot,
VOUT = 200 mV p-p
When P1/M1 is used, 30% overshoot, VOUT = 100 mV p-p
3.3
90
86
80
78
For P1
For M1
For P1
For M1
P1 and M1 within this table refer to the amplifiers shown in Figure 1.
Rev. B | Page 7 of 37
Max
Unit
18
18
43/76
33
V
V
V
mA rms
mA rms
mA
pF
47
pF
+3.8
12
106
100
100
90
V
dB
dB
dB
dB
ADA4350
Data Sheet
5 V FULL SYSTEM
TA = 25°C, +VS = 5 V, −VS = 0 V, RF = 1 kΩ differential, unless otherwise specified.
Table 5.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
HARMONIC PERFORMANCE
Harmonic Distortion (HD2/HD3)
Input Voltage Noise
DC PERFORMANCE
Input Bias Current
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection
OUTPUT CHARACTERISTICS
Linear Output Current
Short-Circuit Current
Settling Time to 0.1%
POWER SUPPLY
Operating Range
Quiescent Current
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
DIGITAL SUPPLIES (DVDD, DGND)
Digital Supply Range
Quiescent Current
Test Conditions/Comments
Min
Typ
Max
Unit
G = −5, VOUT = 200 mV p-p
G = −5, VOUT = 1 V p-p
VOUT = 2 V step, 10% to 90%
15
14
30
MHz
MHz
V/µs
G = −5, fC = 100 kHz
G = −5, fC = 1 MHz
f = 10 Hz
f = 100 kHz
−85/−94
−66/−75
92
4.4
dBc
dBc
nV/√Hz
nV/√Hz
At 25°C
At 85°C
±0.35
±8.5
Common mode
Common mode
Differential mode
CMRR > 80 dB
CMRR > 68 dB
VCM = ±0.5 V
100
2
3
0.5
0
88
VOUT = 1 V p-p, 60 dB SFDR
Sinking/sourcing, RL < 1 Ω
G = −5, VOUT = 2 V step
pA
pA
94
GΩ
pF
pF
V
V
dB
9
41/63
130
mA rms
mA
ns
3.8
3.9
3.3
Enabled
M1 disabled (see Figure 1)
All disabled
±1.6
±30
8
6.5
2
86
80
12
9
V
mA
mA
µA
dB
dB
5.5
V
µA
µA
V
DVDD, DGND
3.3
Enabled
Disabled
+VS to DGND Head Room
Rev. B | Page 8 of 37
50
0.6
≥3.3
Data Sheet
ADA4350
5 V FET INPUT AMPLIFIER
TA = 25°C, +VS = 5 V, −VS = 0 V, RL = 1 kΩ, unless otherwise specified.
Table 6.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Gain Bandwidth Product
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (HD2/HD3)
Input Voltage Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
Output Voltage Swing
Linear Output Current
Short-Circuit Current
POWER SUPPLY
Operating Range
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
Test Conditions/Comments
Min
G = −5, VOUT = 100 mV p-p
G = −5, VOUT = 1 V p-p
Typ
Max
Unit
VOUT = 2 V step, 10% to 90%
G = −5, VOUT = 2 V step
25
24
175
56
60
MHz
MHz
MHz
V/µs
ns
f = 100 kHz, VOUT = 1 V p-p, G = −5
f = 1 MHz, VOUT = 1 V p-p, G = −5
f = 10 Hz
f = 100 kHz
−113/−117
−82/−83
92
4.4
dBc
dBc
nV/√Hz
nV/√Hz
From −40°C to +85°C
From 25°C to 85°C
At 25°C
At 85°C
At 25°C
At 85°C
VOUT = 1.5 V to 3.5 V
25
0.1
0.05
±0.35
±8.5
±0.25
±0.4
102
Common mode
Common mode
Differential mode
CMRR > 80 dB
CMRR > 68 dB
VCM = ± 0.5V
98
80
1.5
1
±1.6
±30
±1.25
100
2
3
0.5
0
88
VOUT = VS ± 10%, positive/negative
G = +21, RF = 1 kΩ, RL open measured at FBx
G = +21, RF = 100 kΩ, RL open measured at FBx
VOUT = 1 V p-p, 60 dB SFDR
Sinking/sourcing
1.15 to 3.46
0.27 to 4.80
3.3
90
86
Rev. B | Page 9 of 37
µV
µV/°C
µV/°C
pA
pA
pA
pA
dB
94
GΩ
pF
pF
V
V
dB
60/50
0.86 to 3.66
0.08 to 4.87
10
32/38
ns
V
V
mA rms
mA
3.8
3.9
12
100
100
V
dB
dB
ADA4350
Data Sheet
5 V INTERNAL SWITCHING NETWORK AND DIGITAL PINS
TA = 25°C, +VS = 5 V, −VS = 0 V, unless otherwise specified. See Figure 1 for sampling and feedback switches position.
Table 7.
Parameter
FEEDBACK/SAMPLE ANALOG SWITCH
Analog Signal Range
Switch On Resistance
Feedback
Sampling
On-Resistance Match Between Channels
Feedback Resistance
Sampling Resistance
SWITCH LEAKAGE CURRENTS
Sampling and Feedback Switch Off Leakage
DYNAMIC CHARACTERISTICS
Power-On Time
Power-Off Time
Off Isolation
Feedback Switches
Sampling Switches
Channel to Channel Crosstalk
Worst Case Switch Feedback Capacitance (Switch Off )
THRESHOLD VOLTAGES FOR DIGITAL INPUT PINS
Symbol
RON, FB
Typ
RON, S
ΔRON, FB
ΔRON, S
VIL
V
390
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
3
3
21
23
Ω
Ω
TA = 85°C
±0.4
±30
±1.2
±80
pA
pA
DVDD = 3.3 V
DVDD = 3.3 V
RL = 50 Ω, f = 1 MHz
RL = 50 Ω, f = 1 MHz
Input Low Voltage
5
VCM = 2.5 V
VCM = 2.5 V
CFB (OFF)
VIH
Unit
308
382
308
384
610
762
612
764
IS (OFF)
tON
tOFF
Max
S0 to S2, VCM = 2.5 V
TA = 85°C
S3 to S5, VCM = 2.5 V
TA = 85°C
S6 to S8, VCM = 2.5 V
TA = 85°C
S9 to S11, VCM = 2.5 V
TA = 85°C
EN, MODE, DGND, LATCH/P0,
SCLK/P1, SDO/P2, SDI/P3, CS/P4 1
DVDD = 5 V
DVDD = 3.3 V
DVDD = 5 V
DVDD = 3.3 V
DVDD, DGND
390
770
770
105
65
ns
ns
−93
−116
−83
0.1
dB
dB
dB
pF
2.0
1.5
1.4
1.0
3.3
Enabled
Disabled
+VS to DGND Head Room
1
Min
0
Input High Voltage
DIGITAL SUPPLIES
Digital Supply Range
Quiescent Current
Test Conditions/Comments
5.5
50
0.6
≥3.3
When referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specification is listed. For full pin names of
multifunction pins, refer to the Pin Configuration and Function Descriptions section.
Rev. B | Page 10 of 37
V
V
V
V
V
µA
µA
V
Data Sheet
ADA4350
5 V ADC DRIVER
TA = 25°C, +VS = 5 V, −VS = 0 V, unless otherwise specified. See Figure 1 for the P1 and M1 amplifiers, RL = 1 kΩ when differential, and RL =
500 Ω when single-ended.
Table 8.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Overdrive Recovery Time
Slew Rate
Settling Time 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion (HD2/HD3)
Referred to Input (RTI) Voltage Noise
Referred to Output (RTO) Voltage Noise
Input Current Noise
DC PERFORMANCE
Output Offset Voltage
Input Offset Voltage Drift
Output Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Open-Loop Gain
Gain
Gain Error
Gain Error Drift
Test Conditions/Comments 1
Min
Typ
Max
Unit
When used differentially, VOUT = 0.1 V p-p
When used differentially, VOUT = 2.0 V p-p
When P1 is used, VOUT = 50 mV p-p
When P1 is used, VOUT = 1.0 V p-p
When M1 is used, VOUT = 50 mV p-p
When M1 is used, VOUT = 1.0 V p-p
For P1, positive recovery/negative recovery
For M1, positive recovery/negative recovery
When differentially used, VOUT = 2 V step
When P1 or M1 is single-ended, VOUT = 1 V step
When used differentially, VOUT = 2 V step
When P1 is used, VOUT = 1 V step
When M1 is used, VOUT = 1 V step
33
16
47
16
37
18
200/200
140/120
37
20
75
60
60
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
V/µs
V/µs
ns
ns
ns
When used differentially, fC = 100 kHz,
VOUT = 1 V p-p
When used differentially, fC = 1 MHz,
VOUT = 1 V p-p
When P1 is used, fC = 100 kHz, VOUT = 500 mV p-p
When P1 is used, fC = 1 MHz, VOUT = 500 mV p-p
When M1 is used, fC = 100 kHz, VOUT = 500 mV p-p
When M1 is used, fC = 1 MHz, VOUT = 500 mV p-p
For P1, f = 10 Hz
For P1, f = 100 kHz
For P1and M1, f = 10 Hz, measured at VOUT2
For P1 and M1, f = 100 kHz, measured at VOUT2
f = 100 kHz, referred to P1
−117/−116
dBc
−80/−85
dBc
−108/−115
−80/−83
−103/−107
−75/−78
60
5.2
140
18
1.1
dBc
dBc
dBc
dBc
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
Differential
Differential
Single-ended, P1 only
Single-ended, M1 only
Single-ended, P1 only
Single-ended, M1 only
P1 only at VIN1 pin
P1 only at RF1 pin
M1 only at REF pin
P1 only
P1 only, VOUT = 1.5 V to 3.5 V
M1 only
0.15
0.6
60
70
0.1
0.3
60
60
60
60
100
1.9995
94
1.99
−0.5
0.6
Rev. B | Page 11 of 37
0.75
16
275
250
5.9
4.5
230
350
200
270
2.01
+0.5
3.4
mV
µV/°C
µV
µV
µV/°C
µV/°C
nA
nA
nA
nA
dB
V/V
%
ppm/°C
ADA4350
Parameter
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Common-Mode Voltage Range
Linear Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Positive Power Supply Rejection Ratio
Negative Power Supply Rejection Ratio
1
Data Sheet
Test Conditions/Comments 1
Min
VIN1 and REF
VIN1 and REF
Typ
Max
200
1.4
For P1, VCM = ±0.5 V
RL = no load, single-ended
RL = 500 Ω, single-ended
0
84
0.15 to 4.85
0.28 to 4.72
0
For P1or M1, VOUT = 1 V p-p, 60 dB SFDR
Differential output, VOUT = 1 V p-p, 60 dB SFDR
For P1 or M1, sinking/sourcing
When used differentially at each VOUTx,
30% overshoot, VOUT = 100 mV p-p
When P1/M1 is used, 30% overshoot,
VOUT = 50 mV p-p
3.3
86
80
80
76
For P1
For M1
For P1
For M1
P1 and M1 within this table refer to the amplifiers shown in Figure 1.
Rev. B | Page 12 of 37
3.9
94
0.125 to 4.875
0.24 to 4.76
Unit
MΩ
pF
V
dB
4
10
41/63
33
V
V
V
mA rms
mA rms
mA
pF
47
pF
3.9
12
104
94
92
88
V
dB
dB
dB
dB
Data Sheet
ADA4350
TIMING SPECIFICATIONS
All input signals are specified with tR = tF = 2 ns (10% to 90% of DVDD) and timed from a voltage threshold level of VTH = 1.3 V at
DVDD = 3.3 V or VTH =1.7 V at DVDD = 5 V. Guaranteed by characterization; not production tested. See Figure 2 and Figure 3.
Table 9.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11 2
t12
Description 1
SCLK period.
SCLK positive pulse width.
SCLK negative pulse width.
CS setup time. The time required to begin sampling data after CS goes low.
CS hold time. The amount of time required for CS to be held low after the last data bit
is sampled before bringing CS high. Data is latched on the CS rising edge. If LATCH is
held low, data is also applied on the CS rising edge.
CS positive pulse width. The amount of time required between consecutive words.
Data setup time. The amount of time the data bit (SDI) must be set before sampling
on the falling edge of SCLK.
Data hold time. The amount of time SDI must be held after the falling edge of SCLK
for valid data to be sampled.
Data latched to the internal switches updated. The amount of time it takes from the
latched data being applied until the internal switches are updated.
LATCH disabled referenced from the rising edge of CS.
LATCH enabled referenced from the falling edge of LATCH.
LATCH negative pulse width.
SCLK rising edge to SDO valid. The amount of time between the SCLK rising edge
and the valid SDO transitions (CLSDO 3 = 20 pF).
CS rising edge to the SCLK falling edge. The amount of time required to prevent a
25th SCLK edge from being recognized (only 24 bits allowed for valid word).
DVDD = 3.3 V
Min
Max
20
10
10
1
7
DVDD = 5 V
Min
Max
20
10
10
1
5
Unit
ns
ns
ns
ns
ns
2
1
1
1
ns
ns
2
2
ns
145
3
140
ns
10
ns
ns
3
15
1
1
ns
When referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specification is listed. For full pin names of
multifunction pins, refer to the Pin Configuration and Function Descriptions section.
This is while in daisy-chain mode and in readback mode.
3
CLSDO is the capacitive load on the SDO output.
1
2
Timing Diagrams for Serial Mode
LATCH ENABLED: LATCHED DATA APPLIED ON FALLING EDGE OF LATCH
LATCH
VTH
LATCH DISABLED: DATA LATCHED AND APPLIED ON RISING EDGE OF CS
t10
t6
VTH
CS
t1
t4
t5
VTH
SCLK
t2
t8
SDI
23
22
21
20
19
18
17
16
t3
15
14
13
12
11
10
9
8
7
t7
6
5
4
3
2
1
0
VTH
t9
INTERNAL
SWITCHES
POSITION
SWITCHES
UPDATED
INTERNAL
SWITCHES
POSITION
SWITCHES
UPDATED
Figure 2. Write Operation
Rev. B | Page 13 of 37
12417-055
t9
ADA4350
LATCH
Data Sheet
LATCH DISABLED: DATA LATCHED AND APPLIED ON RISING EDGE OF CS
t6
t12
READ COMMAND LATCHED
ON RISING EDGE OF CS
CS
READBACK COMPLETED ON
RISING EDGE OF CS
VTH
SCLK
SDI
VTH
23
22
21
20
19
3
4
1
2
0
VTH
NOP COMMAND
READ COMMAND: INPUT WORD SPECIFIES REGISTER TO BE READ
t11
23
22
21
20
19
4
UNDEFINED
3
2
1
0
23
22
21
20
19
4
3
2
1
0
READBACK: SELECTED REGISTER DATA CLOCKED OUT
Figure 3. Read Operation
Rev. B | Page 14 of 37
VTH
12417-056
SDO
Data Sheet
ADA4350
ABSOLUTE MAXIMUM RATINGS
Table 10.
Rating
14 V
5.5 V
See Figure 4
±Vs ± 0.3V
±0.7 V
20 mA
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, θJA is
specified for a device soldered in a circuit board for surfacemount packages. Table 11 lists the θJA for the ADA4350.

V 2
 − OUT

RL

Consider rms output voltages. If RL is referenced to −VS, as in
single-supply operation, the total drive power is +VS × IOUT. If
the rms signal levels are indeterminate, consider the worst case,
when VOUT = +VS/4 for RL to midsupply for dual supplies and
VOUT = +VS/2 for single supply.
PD = (+ VS × I S ) +
(VOUT )2
RL
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
and exposed pad from metal traces, through holes, ground, and
power planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a JEDEC standard
4-layer board. θJA values are approximations.
TJ = 150°C
Unit
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4350 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the ADA4350. Exceeding a junction temperature of 175°C for
an extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
2.5
2.0
28-LEAD TSSOP
1.5
1.0
0.5
0
–55 –45 –35 –25 –15 –5
5
15
25
35
45
AMBIENT TEMPERAURE (°C)
55
65
75
85
12417-102
θJA
72.4
 ± VS
V
× OUT
PD = (± VS × I S ) + 
2
RL

3.0
Table 11. Thermal Resistance
Package Type
28-Lead TSSOP
PD = Quiescent Power + (Total Drive Power − Load Power)
MAXIMUM POWER DISSIPATION (W)
Parameter
Analog Supply Voltage
Digital Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Input Current (IN-N, IN-P, VIN1, RF1, and REF)
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
The quiescent power dissipation is the voltage between the supply
pins (±VS) multiplied by the quiescent current (IS).
Figure 4. Maximum Power Dissipation vs. Ambient Temperature for a
4-Layer Board
ESD CAUTION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the ADA4350 output load drive.
Rev. B | Page 15 of 37
ADA4350
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
28
VIN1
2
27
SWA_OUT
VOUT1 3
26
VOUT2
RF1
FB5
4
25
REF
FB4
5
24
DVDD
FB3
6
23
CS/P4
FB2
7
ADA4350
22
8
TOP VIEW
(Not to Scale)
SDI/P3
FB1
21
SDO/P2
SCLK/P1
FB0 9
20
IN-N 10
19
LATCH/P0
IN-P 11
18
DGND
SWA_IN 12
17
MODE
SWB_IN 13
16
EN
–VS 14
15
+VS
12417-002
SWB_OUT 1
Figure 5. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Mnemonic
SWB_OUT
RF1
VOUT1
FB5
FB4
FB3
FB2
FB1
FB0
IN-N
IN-P
SWA_IN
SWB_IN
−VS
+VS
EN
MODE
DGND
LATCH/P0
SCLK/P1
SDO/P2
SDI/P3
CS/P4
DVDD
REF
VOUT2
SWA_OUT
VIN1
Description
Switch Group B (S3 to S5 and S9 to S11) Output.
Feedback Resistor for Output Differential Amplifier.
Differential Amplifier Output 1.
Feedback Pin 5 for FET Input Amplifier.
Feedback Pin 4 for FET Input Amplifier.
Feedback Pin 3 for FET Input Amplifier.
Feedback Pin 2 for FET Input Amplifier.
Feedback Pin 1 for FET Input Amplifier.
Feedback Pin 0 for FET Input Amplifier.
FET Input Amplifier Inverting Input.
FET Input Amplifier Noninverting Input.
Switch Group A (S0 to S2 and S6 to S8) Input.
Switch Group B (S3 to S5 and S9 to S11) Input.
Analog Negative Supply.
Analog Positive Supply.
Enable Pin.
Mode Pin. Use this pin to switch between the SPI interface and the parallel interface.
Digital Ground.
Latch Bit in the Serial Mode (LATCH). Parallel Data Bit 0 in parallel mode (P0).
Digital Clock in Serial Mode (SCLK). Parallel Data Bit 1 in parallel mode (P1).
Serial Data Out in Serial Mode (SDO). Parallel Data Bit 2 in parallel mode (P2).
Serial Data In in Serial Mode (SDI). Parallel Data Bit 3 in parallel mode (P3).
Select Bit in Serial Mode (CS). Parallel Data Bit 4 in parallel mode (P4).
Digital Positive Supply.
Reference for the ADC Driver at M1.
Differential Amplifier Output 2.
Switch Group A (S0 to S2 and S6 to S8) Output.
Differential Amplifier Noninverting Input.
Rev. B | Page 16 of 37
Data Sheet
ADA4350
TYPICAL PERFORMANCE CHARACTERISITICS
FULL SYSTEM
These plots are for the full system, which includes the FET input amplifier, the switching network, and the ADC driver. Unless otherwise stated,
RL = 1 kΩ differential. For Vs = ±5 V, DVDD = +5 V, and for Vs = +5 V (or ±2.5 V), DVDD = +3.3 V.
2
–40
VS = ±5V
NORMALIZED CLOSED-LOOP GAIN (dB)
1
TIA GAIN = –5, ADC DRIVER GAIN = +1
RF = 5kΩ
VOUT = 4V p-p
–50
0
–60
VS = +5V
DISTORTION (dBc)
–1
–2
–3
–4
–5
–6
–70
VS = +5V, HD2
–80
VS = +5V, HD3
–90
VS = ±5V, HD3
–100
–7
RF = 5kΩ
VOUT = 200mV p-p
G = –5
100
1000
NORMALIZED CLOSED-LOOP GAIN (dB)
INPUT REFERRED VOLTAGE NOISE (nV/√Hz)
VOUT = 1V p-p
0
–1
–2
VOUT = 2V p-p
–4
VOUT = 200mV p-p
–5
–6
–7
–8
Vs = ±5V
G = –5
RF = 5kΩ
–10
0.1
1
10
100
FREQUENCY (MHz)
1
VS = ±5V
OUTPUT VOLTAGE (V)
VS = ±2.5V
0
–0.5
–1.0
TIME (100ns/DIV)
12417-206
–1.5
–2.0
10
1k
100
10k
100k
1M
10M
100M
Figure 10. Input Referred Voltage Noise vs. Frequency
1.0
0.5
1
FREQUENCY (Hz)
SUPPLY CURRENT [ENABLE AND M1 DISABLE] (mA)
1.5
G = –5
VOUT = 2V p-p
RF = 5kΩ
VS = ±5V
10
Figure 7. Frequency Response for Various Voltage Outputs,
See Test Circuit in Figure 49
2.0
5
100
12417-005
–9
1
Figure 9. Harmonic Distortion vs. Frequency for Various Supplies,
See Test Circuit in Figure 48
2
–3
0.1
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response for Various Supplies,
See Test Circuit in Figure 49
1
0.01
12417-208
10
FREQUENCY (MHz)
12
60
VS = ±5V
DIGITAL
10
50
ENABLE
8
40
M1 DISABLE
6
30
4
20
10
2
ALL DISABLE
0
–40
0
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 8. Large Signal Step Response, G = −5 for Various Supplies
Figure 11. Supply Current vs. Temperature at Different Modes
Rev. B | Page 17 of 37
SUPPLY CURRENT [DIGITAL AND ALL DISABLE] (µA)
1
12417-207
VS = ±5V, HD2
–120
0.001
12417-211
–9
0.1
–110
12417-004
–8
ADA4350
–50
Data Sheet
600
VS = ±5V
VS = ±5 V
–60
500
SWTICH ON RESISTANCE (Ω)
–PSRR
+PSRR
–80
–90
–100
SAMPLE SWITCH AT 25°C
300
FEEDBACK SWITCH AT 85°C
200
FEEDBACK SWITCH AT 25°C
1
10
100
FREQUENCY (kHz)
12417-012
100
–110
0.1
0.3
0.2
0.1
0
VS = ±5V
VOUT = 4V p-p
TIA GAIN = –5, ADC DRIVER GAIN = +1
–0.3
0
20
40
60
80
100 120 140 160 180 200 220 240
TIME (ns)
12417-318
–0.1
–0.2
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
COMMON-MODE VOLTAGE (VCM)
Figure 14. Switch On-Resistance vs. Common-Mode Voltage at
Switches for Various Temperature
Figure 12. PSRR vs. Frequency
SETTLING TIME (%)
SAMPLE SWITCH AT 85°C
400
Figure 13. 0.1% Settling Time, See Test Circuit in Figure 49
Rev. B | Page 18 of 37
12417-114
PSRR (dB)
–70
Data Sheet
ADA4350
FET INPUT AMPLIFIER
Unless otherwise stated, RL = 1 kΩ. For Vs = ±5 V, DVDD = +5 V, and for Vs = ±2.5 V, DVDD = +3.3 V.
3
0
–3
–6
G = +10
RF = 9kΩ
–9
–12
G = –5
RF = 5kΩ
–15
–18
0.1
1
10
100
FREQUENCY (MHz)
–3
–6
–9
G = +10
RF = 9kΩ
–12
G = –5
RF = 5kΩ
–15
1
10
1.5
VS = ±2.5V
OUTPUT VOLTAGE (V)
0
–3
–6
G = +10
RF = 9kΩ
–9
G = –5
VOUT = 2V p-p
1.0
G = +2
RF = 1kΩ
CF = 3pF
3
100
Figure 18. Large Signal Frequency Response for Various Gains, VS = 5 V,
See Test Circuit Diagrams in Figure 50 and Figure 51
VS = 5V
VOUT = 100mV p-p
VS = ±5V
0.5
0
–0.5
–12
10
100
FREQUENCY (MHz)
–1.5
TIME (100ns/DIV)
Figure 16. Small Signal Frequency Response for Various Gains, VS = 5 V,
See Test Circuit Diagrams in Figure 50 and Figure 51
6
3
Figure 19. Large Signal Step Response for Various Supplies, G = −5
0.3
VS = ±5V
VOUT = 2V p-p
G = +2
RF = 1kΩ,
CF = 3pF
VS = ±5V
VOUT = 2V STEP
G = –5
RF = 5kΩ
TIME = 10ns/DIV
0.2
SETTLING TIME (%)
0
–3
–6
–9
G = +10
RF = 9kΩ
–15
G = –5
RF = 5kΩ
–18
0.1
1
10
FREQUENCY (MHz)
0
–0.1
–0.2
100
–0.3
12417-213
–12
0.1
TIME (10ns/DIV)
Figure 17. Large Signal Frequency Response for Various Gains, VS = ±5 V,
See Test Circuit Diagrams in Figure 50 and Figure 51
Rev. B | Page 19 of 37
Figure 20. 0.1% Settling Time
12417-118
1
12417-217
–1.0
G = –5
RF = 5kΩ
–15
–18
0.1
NORMALIZED CLOSED-LOOP GAIN (dB)
G = +2
RF = 1kΩ
CF = 3pF
0
FREQUENCY (MHz)
12417-216
NORMALIZED CLOSED-LOOP GAIN (dB)
6
VS = 5V
VOUT = 1V p-p
–18
0.1
Figure 15. Small Signal Frequency Response for Various Gains, VS = ±5 V,
See Test Circuit Diagrams in Figure 50 and Figure 51
9
3
12417-215
G = +2
RF = 1kΩ
CF = 3pF
NORMALIZED CLOSED-LOOP GAIN (dB)
6
6
VS = ±5V
VOUT = 100mV p-p
12417-214
NORMALIZED CLOSED-LOOP GAIN (dB)
9
ADA4350
NUMBER OF PARTS
–65
–70
–75
–80
HD2
–95
–100
–105
–110
60
40
1
10
FREQUENCY (MHz)
0
12417-219
0.1
80
20
HD3
0.01
100
–0.8
–0.6
Figure 21. Distortion (HD2/HD3) vs. Frequency, G = −5
0
0.2
0.4
0.6
0.8
140
VS = ±5V
0
–20
OPEN-LOOP GAIN (dB)
120
100
10
GAIN
–40
100
–60
80
–80
60
–100
PHASE
40
–120
20
–140
0
1
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–160
–20
1
10
40
100
1k
10k
100k
1M
10M
100M
–180
1G
FREQUENCY (Hz)
Figure 25. Open-Loop Gain and Phase vs. Frequency
Figure 22. Input Voltage Noise
–20
VS = ±5V
326 UNITS
x = –0.88µV
σ = 13.58µV
VS = ±5V
–30
–40
–50
CMRR (dB)
30
20
–60
–70
–80
–90
10
–100
–40
–30
–20 –10
0
10
20
30
INPUT OFFSET VOLTAGE (µV)
40
50
–120
100
1k
10k
100k
FREQUENCY (Hz)
Figure 26. CMRR vs Frequency
Figure 23. Input Offset Voltage
Rev. B | Page 20 of 37
1M
10M
12417-126
–110
0
12417-122
NUMBER OF PARTS
–0.2
Figure 24. Input Offset Voltage Drift
12417-212
INPUT REFERRED VOLTAGE NOISE (nV/√Hz)
1000
–0.4
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
12417-124
–85
–90
–115
–120
0.001
VS = ±5V
640 UNITS
X = 0.1µV/°C
σ = 0.25µV/°C
120
PHASE (Degrees)
–50
–55
–60
DISTORTION (dBc)
140
VS = ±5V
G = –5
VOUT = 2V p-p
RL = 1kΩ
12417-125
–40
–45
Data Sheet
Data Sheet
6
VS = ±5V
INPUT AND OUTPUT VOLTAGE (V)
–20
PSRR (dB)
–40
–60
–PSRR
–80
–100
VIN × 6
VOUT
4
VS = ±5V
G = +6
RL = 1kΩ
2
0
–2
–4
1k
10k
100k
FREQUENCY (Hz)
1M
10M
12417-127
+PSRR
–120
100
Figure 27. PSRR vs Frequency
–6
TIME (100ns/DIV)
Figure 28. Output Overdrive Recovery when Used as an Amplifier
Rev. B | Page 21 of 37
12417-030
0
ADA4350
ADA4350
Data Sheet
ADC DRIVER
Unless stated otherwise, RL = 1 kΩ differential, and RL = 500 Ω when single-ended. For VS = ±5 V, DVDD = +5 V, and for VS = +5 V (or ±2.5 V),
DVDD = +3.3 V.
0
DIFFERENTIAL
–3
SINGLE-ENDED
OUTPUT AT VOUT2
–6
SINGLE-ENDED
OUTPUT AT VOUT2
0
DIFFERENTIAL
–3
SINGLE-ENDED
OUTPUT AT VOUT1
–6
VS = ±5V
RF = 1kΩ
VOUT (SINGLE-ENDED) = 1V p-p
VOUT (DIFFERENTIAL) = 2V p-p
P1 GAIN = 1
SINGLE-ENDED
OUTPUT AT VOUT1
1
10
100
FREQUENCY (MHz)
–9
0.1
12417-034
–9
0.1
0.75
DIFFERENTIAL
VS = ±5V
G = +1
VOUT1
0.50
VS = 5V
RF = 1kΩ
VOUT (SINGLE-ENDED) = 1V p-p
VOUT (DIFFERENTIAL) = 2V p-p
P1 GAIN = 1
–9
0.1
1
10
100
–0.25
–0.75
TIME (100ns/DIV)
Figure 30. Large Signal Frequency Response, VS = 5 V
Figure 33. Large Signal Step Response (Single-Ended Output), VS = ±5 V
1.5
VS = ±5V
RF = 1kΩ
VOUT (SINGLE-ENDED) = 50mV p-p
VOUT (DIFFERENTIAL) = 100mV p-p
P1 GAIN = 1
1.0
AMPLITUDE (V)
3
0
–0.50
FREQUENCY (MHz)
6
0
DIFFERENTIAL
–3
–9
0.1
1
0
–0.5
SINGLE-ENDED
OUTPUT AT VOUT1
–1.0
10
FREQUENCY (MHz)
Figure 31. Small Signal Frequency Response, VS = ±5 V
100
VS = ±5V
G = +1
RL = 1kΩ
0.5
SINGLE-ENDED
OUTPUT AT VOUT2
–1.5
12417-036
–6
VOUT2
12417-134
–6
SINGLE-ENDED
OUTPUT AT VOUT1
0.25
TIME (100ns/DIV)
12417-135
–3
AMPLITUDE (V)
0
12417-230
NORMALIZED MAGNITUDE (dB)
100
Figure 32. Large Signal Frequency Response, VS =±5 V
3
NORMALIZED MAGNITUDE (dB)
10
FREQUENCY (MHz)
Figure 29. Small Signal Frequency Response, VS = 5 V
SINGLE-ENDED
OUTPUT AT VOUT2
1
12417-232
3
3
VS = 5V
RF = 1kΩ
VOUT (SINGLE-ENDED) = 50mV p-p
VOUT (DIFFERENTIAL) = 100mV p-p
P1 GAIN = 1
NORMALIZED MAGNITUDE (dB)
NORMALIZED MAGNITUDE (dB)
6
Figure 34. Large Signal Step Response (Differential Output), VS = ±5 V
Rev. B | Page 22 of 37
Data Sheet
ADA4350
0.35
40
0.30
0.25
35
0.20
VOUT1
0.10
VOUT2
NUMBER OF PARTS
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.30
20
15
5
VS = ±2.5V
G = +1
12417-235
–0.40
25
10
–0.25
–0.35
30
TIME (100ns/DIV)
0
–400 –350 –300 –250 –200 –150 –100 –50
0
50
12417-141
AMPLITUDE (V)
0.15
VS = ±5V
326 UNITS
x = –35.9µV
σ = 85.18µV
100 150
OUTPUT OFFSET VOLTAGE (µV)
Figure 35. Large Signal Step Response (Single-Ended Output), VS = ±2.5 V
0.75
Figure 38. Differential Output Offset Voltage
180
VS = ±2.5V
G = +1
160
0.50
NUMBER OF PARTS
AMPLITUDE (V)
140
0.25
0
–0.25
VS = ±5V
640 UNITS
X = 0.51µV/°C
σ = 1.37µV/°C
120
100
80
60
40
–0.50
–0.75
TIME (100ns/DIV)
0
–4.8
–3.2
–1.6
0
1.6
3.2
4.8
12417-237
12417-137
20
6.4
OFFSET VOLTAGE DRIFT (µV/°C)
Figure 36. Large Signal Step Response (Differential Output), VS = ±2.5 V
–40
–60
–70
50
–80
–90
–100
40
VS = ±5V
326 UNITS
FOR P1:
x = –11.87µV
σ = 37.1µV
FOR M1:
x = 6.17µV
σ = 30.27µV
30
20
–110
10
–130
0.001
0.01
0.1
1
FREQUENCY (MHz)
5
0
–200 –170 –140 –110
–80
–50
–20
10
40
OFFSET VOLTAGE (µV)
Figure 40. Single-Ended Output Offset Voltage
Figure 37. Harmonic Distortion vs. Frequency
Rev. B | Page 23 of 37
70
100
12417-241
–120
12417-138
DISTORTION (dBc)
–50
60
VS = ±5V
VOUT = 4V p-p DIFFERENTIAL, 2V p-p SINGLE-ENDED
G = +1
HD2, DIFFERENTIAL
HD2, SINGLE-ENDED OUTPUT AT VOUT1
HD2, SINGLE-ENDED OUTPUT AT VOUT2
HD3, DIFFERENTIAL
HD3, SINGLE-ENDED OUTPUT AT VOUT1
HD3, SINGLE-ENDED OUTPUT AT VOUT2
NUMBER OF PARTS
–30
Figure 39. Differential Output Offset Voltage Drift
ADA4350
Data Sheet
6
180
NUMBER OF PARTS
140
120
VS = ±5V
G = +2
RF = 1kΩ
RL = 500Ω
VOUT
INPUT AND OUTPUT VOLTAGE (V)
160
VS = ±5V
640 UNITS
FOR P1:
x = –0.06µV/°C
σ = 0.54µV/°C
FOR M1:
x = –0.22µV/°C
σ = 0.4µV/°C
100
80
60
40
4
VIN × 2
2
0
–2
–4
–2.0
–1.4
–0.8
–0.2
0.4
1.0
1.6
2.2
2.8
OFFSET VOLTAGE DRIFT (µV/°C)
–6
12417-239
0
–2.6
TIME (100ns/DIV)
Figure 41. Single-Ended Offset Voltage Drift
–20
–30
12417-051
20
Figure 44. Output Overdrive Recovery (M1 Only)
0
VS = ±5V
VCM = ±0.5V
VS = ±5V
–20
–40
–40
PSRR (dB)
CMRR (dB)
–50
–60
–70
–PSRR
–60
+PSRR
–80
–80
–90
–100
0.01
0.1
1
10
FREQUENCY (MHz)
–120
12417-049
–110
0.001
4
2
1k
10k
100k
1M
Figure 45. PSRR vs. Frequency (P1 Only)
VS = ±5V
G = +2
RF = 1kΩ
RL = 500Ω
VIN × 2
0
–2
–4
–6
TIME (100ns/DIV)
12417-050
INPUT AND OUTPUT VOLTAGE (V)
VOUT
100
FREQUENCY (Hz)
Figure 42. CMRR vs. Frequency
6
10
Figure 43. Output Overdrive Recovery (P1 Only)
Rev. B | Page 24 of 37
10M
12417-139
–100
Data Sheet
1000
100
10
1
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
VS = ±5V
100
10
1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
12417-243
OUTPUT REFERRED VOLTAGE NOISE (nV/√Hz)
VS = ±5V
12417-242
INPUT REFERRED VOLTAGE NOISE (nV/√Hz)
1000
ADA4350
Figure 47. Output Referred Voltage Noise vs. Frequency, P1 and M1,
See Test Circuit Diagram in Figure 53
Figure 46. Input Referred Voltage Noise vs. Frequency, P1 Only,
See Test Circuit Diagram in Figure 52
Rev. B | Page 25 of 37
ADA4350
Data Sheet
TEST CIRCUITS
5kΩ
1kΩ
FUNCTION
GENERATOR
P1
VOUT1
LPF
500Ω
825Ω
1kΩ
G = –5
MEASURE
DISTORTION WITH
DIFFERENTIAL
OUTPUT
500Ω
1kΩ
M1
FET AMP
VOUT2
12417-058
500Ω
DIFFERENTIAL GAIN = 1
ADC DRIVER
Figure 48. Harmonic Distortion for Full System
5kΩ
1kΩ
VIN
P1
VOUT1
500Ω
825Ω
MEASURE PARAMETERS
AT DIFFERENTIAL
OUTPUT
1kΩ
G = –5
500Ω
1kΩ
M1
FET AMP
VOUT2
12417-059
500Ω
DIFFERENTIAL GAIN = 1
ADC DRIVER
Figure 49. Full System Measurement for Other Parameters
CF
RF
MEASURE
FREQUENCY
RESPONSE
RG
MEASURE OUTPUT
NOISE HERE
FET
AMP
RL
G=1+
RF
VN G = +1
INPUT REFERRED NOISE VN = OUTPUT NOISE
12417-148
AC SIGNAL
OF DIFFERENCE
FREQUENCY
RG
Figure 50. Frequency Response for FET Input Amplifier,
Noninverting Gain Configuration
12417-150
P1
Figure 52. Input Referred Voltage Noise for P1
INSIDE CHIP
CF
1kΩ
RF
MEASURE
FREQUENCY
RESPONSE
RG
1kΩ
M1
MEASURE OUTPUT
REFERED VOLTAGE
NOISE HERE
500Ω
G=
–RF
RG
Figure 51. Frequency Response for FET Input Amplifier,
Inverting Gain Configuration
Figure 53. Output Referred Voltage Noise for P1 and M1
Rev. B | Page 26 of 37
12417-151
FET
AMP
12417-149
AC SIGNAL
OF DIFFERENCE
FREQUENCY
P1
Data Sheet
ADA4350
THEORY OF OPERATION
KELVIN SWITCHING TECHNIQUES
Traditional gain selectable amplifiers use analog switches in a
feedback loop to connect discrete external resistors and capacitors
to the inverting input by selecting the appropriate feedback
path. This approach introduces several errors due to the nonideal
nature of the analog switches in the loop. For example, the
on-resistance of the analog switch causes voltage and temperature
dependent gain errors, while the leakage current causes offset
errors, especially at high temperature. The Kelvin switching
technique solves this problem by introducing two switches in
each gain selection loop, one to connect the transimpedance/
op amp output to the feedback network, and the other to connect
the feedback network output to the downstream components.
Figure 54 shows a programmable gain transimpedance amplifier
with Kelvin switching.
CF1
RF1
CF2
HIGH IMPEDANCE LOAD
EXAMPLE
RF2
S1B
V1
S2B
S1A
V2
S2A
VOUT
Although this technique requires using twice as many switches,
the voltage (Vx) in the center node is no longer switch dependent;
it is only dependent on the current across the selected resistor
(see Equation 1 through Equation 3).
V1 = VOUT × (RF2/(RF2 + RS1B))
(2)
V1 = −IPHOTO × RF2
(3)
where:
VOUT is the output of the first amplifier.
IPHOTO is the current from the photodiode.
RF2 is the feedback resistor of Transimpedance Path 2.
RS1B is the switch resistance of the S1B switch.
The switches shown on the right (S2A and S2B) in Figure 54
only have a small output impedance and contribute negligible
error if the amplifier drives a high impedance load. In the case
of the ADA4350, the high impedance load is the integrated
ADC driver.
12417-103
NOTES
1. S1A, S1B, S2A, AND S2B ARE THE ANALOG SWITCHES.
RFx ARE THE FEEDBACK RESISTORS SPECIFIC TO EACH
TRANSIMPEDANCE PATH. CFx ARE THE FEEDBACK CAPACITORS
SPECIFIC TO EACH TRANSIMPEDANCE PATH.
(1)
Substituting Equation 1 into Equation 2,
RL
IPHOTO
VOUT = −IPHOTO × (RF2 + RS1B)
Figure 54. Programmable Gain Transimpedance Amplifier with Kelvin
Switching
Rev. B | Page 27 of 37
ADA4350
Data Sheet
APPLICATIONS INFORMATION
CONFIGURING THE ADA4350
Setting more than one Px pin to Logic 1 results in connecting
the selected gain paths in parallel.
See the EVAL-ADA4350RUZ-P user guide for details on the
basic configuration of the ADA4350, and how to use the
evaluation board. For more details on configuring the ADC
driver in a different gain setting, see the ADA4941-1 data sheet.
Table 13. Manual Mode or Parallel Mode Operation
Bit On
P0
P1
P2
P3
P4
The gain settings of the ADA4350 can be chosen via the SPI
interface or manually through a 5-lead DIP switch.
SELECTING THE TRANSIMPEDANCE GAIN PATHS
MANUALLY OR THROUGH THE PARALLEL
INTERFACE
Switch Closed
S0 and S6
S1 and S7
S2 and S8
S3 and S9
S4 and S10
Gain Path Selected
FB0
FB1
FB2
FB3
FB4
SELECTING THE TRANSIMPEDANCE GAIN PATHS
THROUGH THE SPI INTERFACE (SERIAL MODE)
In the manual mode (or parallel mode), only five out of the six
transimpedance paths can be accessed (FB0 to FB4). Figure 55
shows the simplified schematics of the ADA4350 and the positions
of FB0 to FB4. In this example, the first two feedback paths
(FB0 and FB1) are configured as two different transimpedance
gain paths.
For serial mode operation, set the EN pin (Pin 16) to Logic 1
and the MODE pin (Pin 17) to Logic 0. In serial mode, Pin 19
is LATCH, Pin 20 is SCLK, Pin 21 is SDO, Pin 22 is SDI, and Pin 23
is CS. Serial mode operation uses a 24-bit command to configure
each individual switch, S0 through S11, as well as additional
options. Table 14 shows the 24-bit map used in serial mode
operation. Table 15 shows the example codes that select the
various transimpedance gain paths.
To operate in manual mode or in parallel mode, set the EN pin
(Pin 16) and the MODE pin (Pin 17) to Logic 1. In this mode,
Pin 19 to Pin 23 represent P0 through P4, respectively. To select
one gain, set the corresponding Px pin to Logic 1, and set all
other Px pins to Logic 0. Table 13 shows the relationship between
the gain select switches (P0 through P4) and the gain path
selected.
Multifunction pin names may be referenced by their relevant
function only.
CF1
RF1
4
RF1
5
VIN1
FB5
6
SWA_OUT
FB3
7
FB4
8
FB2
FB0
9
FB1
RF0
SWB_OUT
CF0
27
1
28
2
ADA4350
11
S9
S10
S11
S3
S4
S5
P1
3
VOUT1
M1
26
VOUT2
SDO/P2
REF
CS/P4
25
SDI/P3
19 20 21 22 23
SCLK/P1
17
SWITCHING NETWORK
Figure 55. Simplified Schematic
Rev. B | Page 28 of 37
ADC DRIVER
12417-101
FET AMP
16
MODE
13
LATCH/P0
12
EN
SPI INTERFACE
SWA_IN
IN-P
S6
S7
S8
S0
S1
S2
10
SWB_IN
IN-N
Data Sheet
ADA4350
Table 14. 24-Bit Map Used in Serial Mode Operation
Bit No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13 1
14
15
16
17
18
19
20
21
22
23
1
Function
S0 on/off control. Write 1 to this bit to close Switch S0.
S1 on/off control. Write 1 to this bit to close Switch S1.
S2 on/off control. Write 1 to this bit to close Switch S2.
S3 on/off control. Write 1 to this bit to close Switch S3.
S4 on/off control. Write 1 to this bit to close Switch S4.
S5 on/off control. Write 1 to this bit to close Switch S5.
S6 on/off control. Write 1 to this bit to close Switch S6.
S7 on/off control. Write 1 to this bit to close Switch S7.
S8 on/off control. Write 1 to this bit to close Switch S8.
S9 on/off control. Write 1 to this bit to close Switch S9.
S10 on/off control. Write 1 to this bit to close Switch S10.
S11 on/off control. Write 1 to this bit to close Switch S11.
Reserved. Set to logic low.
Optional internal 1 pF feedback capacitor between the inverting input and the output of the amplifier.
Write 1 to this bit to turn the capacitor on.
Disable the SDO pin. Write 1 to this bit to disable the SDO pin.
Disable the M1 amplifier. Write 1 to this bit to disable the M1 amplifier.
Reserved. Set to logic low.
Reserved. Set to logic low.
Reserved. Set to logic low.
Reserved. Set to logic low.
Reserved. Set to logic low.
Reserved. Set to logic low.
Reserved. Set to logic low.
Read/write bit. Set to 1 to read and set to 0 to write.
Default Setting
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The optional internal 1 pF feedback capacitor provides a quick and convenient way to compensate the TIA when using a high value feedback resistor (>1 MΩ).
Table 15. Serial Mode Operation
Command (Hex Code Format, B23…B0)
00 00 41(MSB Side)
00 20 41
00 00 82
00 01 04
00 02 08
00 04 10
00 08 20
Switch Closed
S0 and S6
S0 and S6
S1 and S7
S2 and S8
S3 and S9
S4 and S10
S5 and S11
Rev. B | Page 29 of 37
Gain Path Selected
FB0
FB0, optional internal feedback capacitor on
FB1
FB2
FB3
FB4
FB5
ADA4350
Data Sheet
SPICE MODEL
The EN and MODE inputs are internally set to high and low,
respectively, and are not accessible in this model. Figure 56
shows the recommended symbol pins when creating the
ADA4350 symbol in the SPICE simulator.
5
4
FB1
FB2
FB3
FB4
FB5
10
IN_N
11
IN_P
15
VCC
14
VEE
24
DVDD
18
DGND
27
1
28
2
RF1
6
VIN1
7
SWA_OUT
8
SWB_OUT
9
FB0
The SPICE model only supports parallel mode operation.
Pin P5 enables parallel mode and allows full switching network
functionality.
VOUT1 3
ADA4350
U1
SCLK/P1
SDO/P2
SDI/P3
CS/P4
19
20
21
22
23
25
12417-200
LATCH/P0
13
REF
SWB_IN
12
P5
SWA_IN
VOUT2 26
Figure 56. Recommended Symbol Layout
Table 16. Model Pin Descriptions
Symbol Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Model Node
N10
N11
VCC
VEE
VDD
DGND
N12
N13
PO
P1
P2
P3
P4
P5
N25
N26
N3
N2
N28
27
1
4
5
6
7
8
9
Pin No.
10
11
15
14
24
18
12
13
19
20
21
22
23
Not applicable
25
26
3
2
28
27
1
4
5
6
7
8
9
Rev. B | Page 30 of 37
Mnemonic
IN_N
IN_P
VCC
VEE
DVDD
DGND
SWA_IN
SWB_IN
LATCH/P0
SCLK/P1
SDO/P2
SDI/P3
CS/P4
P5
REF
VOUT2
VOUT1
RF1
VIN1
SWA_OUT
SWB_OUT
FB5
FB4
FB3
FB2
FB1
FB0
Data Sheet
ADA4350
C6
R6
300kΩ
C5
R5
100kΩ
C4
R4
30kΩ
C3
R3
10kΩ
C2
R2
3kΩ
C1
7
6
5
4
27
1
28
FB2
FB3
FB4
FB5
SWA_OUT
SWB_OUT
VIN1
10 IN_N
CPHOTODIODE
2
RF1
8
FB1
AC 1 0 SlNE
(0 1m 1k 0 0)
I1
9
FB0
R1
1kΩ
VOUT1 3
VOUT1
VOUT2 26
VOUT2
11 IN_P
ADA4350
15 VCC
U1
SWB_IN
LATCH/P0
SCLK/P1
SDO/P2
SDI/P3
CS/P4
18 DGND
SWA_IN
24 DVDD
–5
V3
12
13
19
20
21
22
23
Figure 57. SPICE Schematic Example to Test Basic Functionality
Rev. B | Page 31 of 37
25
12417-201
–5
V2
P5
14 VEE
REF
5
V1
ADA4350
Data Sheet
TRANSIMPEDANCE AMPLIFIER DESIGN THEORY
Because its low input bias current minimizes the dc error at the
preamp output, the ADA4350 works well in photodiode preamp
applications. In addition, its high gain bandwidth product and
low input capacitance maximizes the signal bandwidth of the
photodiode preamp. Figure 58 shows the transimpedance
amplifier model of the ADA4350.
CF
Equating the zero frequency, fZ, with the fX frequency maximizes
the signal bandwidth with a 45° phase margin. Calculate fX as
follows because fX is the geometric mean of fP and fGBW:
fx 
CF 
CM
CS
+
VB
VOUT
CD
RSH = 1011 Ω
CM
12417-157
IPHOTO
ADA4350
(7)
By combining Equation 5, Equation 6, and Equation 7, the CF
value that produces fX is defined by
RF
–
f P  fGBW
CS
2π  RF  fGBW
(8)
The frequency response in this case shows approximately 2 dB
peaking and 15% overshoot. Doubling CF and cutting the
bandwidth in half results in a flat frequency response with
approximately 5% transient overshoot.
OPEN-LOOP GAIN
Figure 58. Transimpedance Amplifier Model of the ADA4350
I PHOTO  RF
1  sC F RF
(4)
fX
where:
IPHOTO is the output current of the photodiode.
RF is the feedback resistor.
CF is the feedback capacitance.
G = R2C1s
G=1
log f
fP
The signal bandwidth is 1/(RF × CF), as determined by Equation 4.
In general, set RF such that the maximum attainable output
voltage corresponds to the maximum diode current, IPHOTO,
allowing the use of the full output swing.
fP = 1/2πRFCS
(5)
With the additional pole from the open-loop response of the
amplifier, the two-pole system results in peaking and instability
due to an insufficient phase margin (see gray lines for the noise
gain and phase in Figure 59).
0°
–45°
PHASE (°)
The signal bandwidth attainable with this preamp is a function
of RF, the gain bandwidth product (fGBW) of the amplifier, and
the total capacitance at the amplifier summing junction, including
CS and the amplifier input capacitance of CD and CM. RF and the
total capacitance produce a pole with the loop frequency (fP).
–90°
1
2πRF C F
log f
–135°
–180°
Figure 59. Noise Gain and Phase Bode Plot of the Transimpedance Amplifier
Design Without Compensation
Adding CF to the feedback loop creates a zero in the loop
transmission that compensates for the effect of the input pole,
which stabilizes the photodiode preamp design because of the
increased phase margin (see the gray lines for the noise gain and
phase in Figure 60). It also sets the signal bandwidth, fZ (see the
I to V gain line for the signal gain in Figure 60). The signal
bandwidth and the zero frequency, fZ, are determined by
fz 
fGBW
12417-158
VOUT 
|A| (dB)
The basic transfer function in Equation 4 describes the
transimpedance gain of the photodiode preamp.
(6)
Rev. B | Page 32 of 37
Data Sheet
ADA4350
The dominant output noise sources in the transimpedance
amplifier design are the input voltage noise of the amplifier,
VNOISE, and the resistor noise due to RF. The effect due to the
current noise is negligible in comparison. The gray line in
Figure 60 shows the noise gain and phase over frequencies for
the transimpedance amplifier. The noise bandwidth is at the fN
frequency, and is calculated by
|A (s)|
OPEN-LOOP GAIN
fX
I TO V GAIN
fZ
fN
fN 
G = 1 + CS/CF
G = RFCS(s)
G=1
fGBW
Table 17. RMS Noise Contributions of Transimpedance
Amplifier
90°
Contributor
RF
PHASE (°)
45°
0°
f
VNOISE
–45°
12417-159
–90°
–135°
(9)
Table 17 shows the dominant noise sources (RF and VNOISE) for
the transimpedance amplifier when it has a 45° phase margin for
the maximum bandwidth, and in this case, fZ = fX = fN.
f
fP
f GBW
(C S  C F ) / C F
Figure 60. Signal and Noise Gain and Phase of the Transimpedance Amplifier
Design with Compensation
Rev. B | Page 33 of 37
Expression
4kT  RF  f N 
VNOISE 
π
2
CS  CM  CF  2CD  
CF
π
 fN
2
ADA4350
Data Sheet
CF4
RF4
CF3
RF3
CF2
RF2
CF1
RF1
CF0
RF0
IPHOTO
CD = 91pF TO 100nF
S0
S6
S1
S7
S2
S8
S3
S9
S4
S10
100Ω
NOTES
1. RFx ARE THE FEEDBACK RESISTORS SPECIFIC TO EACH TRANSIMPEDANCE PATH. CFx ARE THE FEEDBACK
CAPACITORS SPECIFIC TO EACH TRANSIMPEDANCE PATH.
12417-065
TIA
Figure 61. ADA4350 Configured as a Transimpedance Amplifier with Five Different Gains
1M
TRANSIMPEDANCE GAIN AMPLIFIER
PERFORMANCE
CD = 91pF
RF0 = 1kΩ
RF1 = 3kΩ
RF2 = 10kΩ
RF3 = 30kΩ
RF4 = 100kΩ
1k
CD = 91pF
RF0 = 1kΩ, CF0 = 15pF
RF1 = 3kΩ, CF1 = 6.8pF
RF2 = 10kΩ, CF2 = 3.3pF
RF3 = 30kΩ, CF3 = 2.2pF
RF4 = 100kΩ, CF4 = 1pF
0.01k
0.1M
1M
10M
100M
FREQUENCY (Hz)
0.1k
CD = 1nF
RF0 = 1kΩ, CF0 = 33pF
RF1 = 3kΩ, CF1 = 15pF
RF2 = 10kΩ, CF2 = 10pF
RF3 = 30kΩ, CF3 = 5.6pF
RF4 = 100kΩ, CF4 = 3.3pF
0.01k
10k
100k
1M
10M
Figure 63. Transimpedance vs. Frequency, CD = 1 nF
10k
0.1k
1k
FREQUENCY (Hz)
12417-166
TRANSIMPEDANCE (Ω)
100k
10k
Figure 62. Transimpedance vs. Frequency, CD = 91 pF
Rev. B | Page 34 of 37
100M
12417-167
1M
100k
TRANSIMPEDANCE (Ω)
Figure 61 shows the ADA4350 configured as a transimpedance
amplifier with five different gains. The photodiode sensor
capacitance, CD, varies from 91 pF to 100 nF to showcase the
transimpedance gain performance at various frequency. Figure 62
to Figure 65 shows the transimpedance vs. frequency at different
CD settings. Note that the compensation capacitors, CF0 to CF4,
correct for the inherent instability of the transimpedance
configuration. Capacitors chosen were such that the transimpedance gain response compensates for the maximum
bandwidth and is close to having a 45° phase margin.
Data Sheet
ADA4350
NORMALIZED GAIN (dB)
10k
1k
CD = 10nF
RF0 = 1kΩ, CF0 = 100pF
RF1 = 3kΩ, CF1 = 56pF
RF2 = 10kΩ, CF2 = 33pF
RF3 = 30kΩ, CF3 = 18 pF
RF4 = 100kΩ, CF4 = 10pF
0.1k
0.01k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
12417-168
RFx = 250Ω, CFx = 33pF
RFx = 500Ω, CFx = 20pF
100k
10M
1M
100M
FREQUENCY (Hz)
To mitigate this effect, use an additional snubber circuit at the
output of the FET input amplifier, as shown in Figure 68. In this
configuration, the feedback resistor (RFx) is 68 Ω, and the capacitance
of the photodiode is 40 pF.
1M
TRANSIMPEDANCE (Ω)
RFx = 125Ω, CFx =47pF
Figure 67. Normalized Frequency Response with Decreasing RF (See Figure 66)
Figure 64. Transimpedance vs. Frequency, CD = 10 nF
CD = 100nF
RF0 = 1kΩ, CF0 = 300pF
RF1 = 3kΩ, CF1 = 180pF
RF2 = 10kΩ, CF2 = 100pF
RF3 = 30kΩ, CF3 = 56pF
RF4 = 100kΩ, CF4 = 33pF
100k
RFx = 68Ω, CFx = 100pF
100pF
10k
68Ω
–
1k
IPHOTO
+
RS
CS
TIA
CD = 40pF
0.1k
1kΩ
12417-068
TRANSIMPEDANCE (Ω)
100k
11
10 CD = 91pF
9
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
10k
12417-067
1M
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 65. Transimpedance vs. Frequency, CD = 100 nF
THE EFFECT OF LOW FEEDBACK RESISTOR RFx
As the load of the transimpedance amplifier increases, excessive
peaking in the frequency response can be observed when the RFx
value is too small. This peaking can persist even when excessive
CFx overcompensates for it. Figure 66 shows the ADA4350
configured with a photodiode capacitance value of 91 pF and
a 1 kΩ transimpedance load. Figure 67 shows the normalized
frequency response of this configuration. By decreasing RF from
500 Ω to 68 Ω, the peaking in the frequency response increases
progressively. The large peaking translates to a huge overshoot
in the pulse response, which is an undesirable result.
Figure 69 shows the effect of various snubber circuits clamping
down the peaking. Without the snubber circuit, there is 6 dB of
peaking when an overcompensated CFx of 100 pF is used. With
the snubber circuits, the bandwidth is restricted to approximately
10 MHz. To compromise between the peaking and the bandwidth,
adjust the values of the snubber circuit.
6
3
NORMALIZED GAIN (dB)
0.01k
10k
12417-169
Figure 68. Snubber Circuit Added to Mitigate Peaking
CFx*
RF = 68Ω
CF = 100pF
CD = 40pF
RL = 1kΩ
NO SNUBBER
RS = 10Ω, CS = 5.6nF
0
RS = 10Ω, CS = 10nF
–3
RS = 10Ω,CS = 33nF
–6
TIA
CD = 91pF
*OVERCOMPENSATES
1kΩ
1M
10M
FREQUENCY (Hz)
12417-066
+
–9
100k
VOUT
IPHOTO
100M
12417-069
RFx
–
Figure 69. Effect of Snubber Circuits on the Transimpedance Frequency Response
(See Figure 68)
Figure 66. Transimpedance Amplifier Circuit
Rev. B | Page 35 of 37
ADA4350
Data Sheet
USING THE T NETWORK TO IMPLEMENT LARGE
FEEDBACK RESISTOR VALUES
Large feedback resistors (>1 MΩ) can cause the two following
issues in the transimpedance amplifier design:
The T network (the RFx, R2, and R1 resistors) maintains the
transimpedance gain and signal bandwidth with a lower
feedback resistor and a resistive gain network, as shown in
Figure 70.
CFx
0.5pF
R2
1MΩ
R1
3.3pF
RFx
IPHOTO
Figure 71 shows the ADA4350 configured as a 1 MΩ transimpedance path and its T network equivalent. Figure 72 compares
the performance of the 1 MΩ path and the equivalent T network
with and without compensation capacitors.
TIA
100kΩ
VOUT
RL
1kΩ
111Ω
12417-268
ZF
As compared to a standard TIA design, the T network is noisier
because the dominant voltage noise density is amplified by the
gain factor 1 + R2/R1.
CD = 91pF
IPHOTO
Figure 70. T Network
The relationship between the transimpedance VOUT/IPHOTO and
the T network resistors (RFx, R1, and R2) can be expressed as
10M
(10)
where:
VOUT is the output voltage of the TIA.
IPHOTO is the input photodiode current.
ZF = RFx/((RFx × CFx)s + 1), where RFx and CFx are the feedback
resistor and capacitor, respectively, of any of the chosen
transimpedance gain paths.
R1 and R2 are the T network gain resistors.
RL
Figure 71. 1 MΩ Transimpedance Path and its Equivalent T Network
TRANSIMPEDANCE (Ω)

VOUT
R2 R2 

  Z F   1 

I PHOTO
R1 Z F 

VOUT
TIA
VS = ±5V, DVDD = +5V
CD = 91pF
1M
100k
10k
If ZF >> R2, the transimpedance equation is simplified to
RF x
VOUT
R2 

 1 

(R Fx  C Fx )s  1 
I PHOTO
R1 
1k
10k
RF = 1MΩ
1MΩ T NETWORK EQUIVALENT
RF = 1MΩ, CF = 500fF
1MΩ T NETWORK EQUIVALENT, CF = 3.3pF
100k
1M
10M
FREQUENCY (Hz)
Figure 72. Comparing the 1 MΩ Transimpedance Path and
T Network Performance
Rev. B | Page 36 of 37
12417-070

If the parasitic capacitance of the feedback resistor exceeds
the optimal compensation value, it can significantly reduce
the TIA signal bandwidth.
If the required compensation capacitance is too low
(<1 pF), it is not practical to choose a feedback capacitor.
12417-269

Therefore, as compared to the standard TIA design, the T network
uses a feedback resistor value that is 1/(1 + R1/R2) smaller to
obtain the same transimpedance. This eliminates the concern of
the high parasitic capacitance associated with the large feedback
resistor. To maintain the same signal bandwidth (or same pole),
increase CF by a factor of 1 + R2/R1 to eliminate concerns of an
impractical small compensation capacitor.
Data Sheet
ADA4350
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
0.15
0.05
COPLANARITY
0.10
0.30
0.19
1.20 MAX
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 73. 28-Lead Thin Shrink Small Outline Package [TSSOP],
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADA4350ARUZ
ADA4350ARUZ-R7
EVAL-ADA4350RUZ-P
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board for 28-Lead TSSOP, Precision Version with Guard Rings
Z = RoHS Compliant Part.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12417-0-3/16(B)
Rev. B | Page 37 of 37
Package Option
RU-28
RU-28