ATMEL AT90S8535 8-bit microcontroller with 8k bytes in-system programmable flash Datasheet

Features
• AVR® – High-performance and Low-power RISC Architecture
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– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
Data and Nonvolatile Program Memories
– 8K Bytes of In-System Programmable Flash
SPI Serial Interface for In-System Programming
Endurance: 1,000 Write/Erase Cycles
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Software Security
Peripheral Features
– 8-channel, 10-bit ADC
– Programmable UART
– Master/Slave SPI Serial Interface
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare and
Capture Modes and Dual 8-, 9-, or 10-bit PWM
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset Circuit
– Real-time Clock (RTC) with Separate Oscillator and Counter Mode
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power Save and Power-down
Power Consumption at 4 MHz, 3V, 20°C
– Active: 6.4 mA
– Idle Mode: 1.9 mA
– Power-down Mode: <1 µA
I/O and Packages
– 32 Programmable I/O Lines
– 40-lead PDIP, 44-lead PLCC, 44-lead TQFP, and 44-pad MLF
Operating Voltages
– VCC: 4.0 - 6.0V AT90S8535
– VCC: 2.7 - 6.0V AT90LS8535
Speed Grades:
– 0 - 8 MHz for the AT90S8535
– 0 - 4 MHz for the AT90LS8535
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90S8535
AT90LS8535
Rev. 1041H–11/01
1
Pin Configurations
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AT90S/LS8535
1041H–11/01
AT90S/LS8535
Description
The AT90S8535 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S8535
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
Block Diagram
Figure 1. The AT90S8535 Block Diagram
PA0 - PA7
PC0 - PC7
PORTA DRIVERS
PORTC DRIVERS
VCC
GND
DATA DIR.
REG. PORTA
DATA REGISTER
PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
ANALOG MUX
ADC
OSCILLATOR
AGND
AREF
XTAL1
INTERNAL
OSCILLATOR
OSCILLATOR
TIMING AND
CONTROL
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
DECODER
CONTROL
LINES
XTAL2
RESET
TIMER/
COUNTERS
X
Y
Z
INTERRUPT
UNIT
ALU
EEPROM
STATUS
REGISTER
ANALOG
COMPARATOR
+
-
PROGRAMMING
LOGIC
UART
SPI
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
PORTB DRIVERS
PORTD DRIVERS
PB0 - PB7
PD0 - PD7
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The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The AT90S8535 provides the following features: 8K bytes of In-System Programmable
Flash, 512 bytes EEPROM, 512 bytes SRAM, 32 general-purpose I/O lines, 32 generalpurpose working registers, Real-time Clock (RTC), three flexible timer/counters with
compare modes, internal and external interrupts, a programmable serial UART, 8-channel, 10-bit ADC, programmable Watchdog Timer with internal oscillator, an SPI serial
port and three software-selectable power-saving modes. The Idle Mode stops the CPU
while allowing the SRAM, timer/counters, SPI port and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power
Save Mode, the timer oscillator continues to run, allowing the user to maintain a timer
base while the rest of the device is sleeping.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface or by a conventional nonvolatile memory programmer.
By combining an 8-bit RISC CPU with In-System Programmable Flash on a monolithic
chip, the Atmel AT90S8535 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The AT90S8535 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators and evaluation kits.
Pin Descriptions
VCC
Digital supply voltage.
GND
Digital ground.
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,
they will source current if the internal pull-up resistors are activated.
Port A also serves as the analog inputs to the A/D Converter.
The Port A pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. Port B also serves the functions of various
special features of the AT90S8535 as listed on page 78.
The Port B pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port C (PC7..PC0)
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Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output
buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source
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AT90S/LS8535
current if the pull-up resistors are activated. Two Port C pins can alternatively be used
as oscillator for Timer/Counter2.
The Port C pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output
buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features of the AT90S8535 as listed
on page 86.
The Port D pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
AVCC
AVCC is the supply voltage pin for Port A and the A/D Converter. If the ADC is not used,
this pin must be connected to VCC. If the ADC is used, this pin must be connected to
VCC via a low-pass filter. See page 68 for details on operation of the ADC.
AREF
AREF is the analog reference input for the A/D Converter. For ADC operations, a voltage in the range 2V to AVCC must be applied to this pin.
AGND
Analog ground. If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND.
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Clock Options
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can
be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used.
Figure 2. Oscillator Connections
MAX 1 HC BUFFER
HC
C2
C1
XTAL2
XTAL1
GND
Note:
External Clock
When using the MCU Oscillator as a clock for an external device, an HC buffer should be
connected as indicated in the figure.
To drive the device from an external clock source, XTAL2 should be left unconnected
while XTAL1 is driven as shown in Figure 3.
Figure 3. External Clock Drive Configuration
Timer Oscillator
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For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly
between the pins. No external capacitors are needed. The oscillator is optimized for use
with a 32,768 Hz watch crystal. Applying an external clock source to TOSC1 is not
recommended.
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AT90S/LS8535
Architectural
Overview
The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle,
one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from
the register file, the operation is executed and the result is stored back in the register file
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing, enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the constant table look-up function. These added function registers are the 16-bit X-register, Y-register, and Z-register.
Figure 4. The AT90S8535 AVR RISC Architecture
Data Bus 8-bit
4K X 16
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Interrupt
Unit
SPI
Unit
Serial
UART
8-bit
Timer/Counter
ALU
16-bit
Timer/Counter
with PWM
512 x 8
Data
SRAM
8-bit
Timer/Counter
with PWM
Watchdog
Timer
512 x 8
EEPROM
Analog to Digital
Converter
32
I/O Lines
Analog
Comparator
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S8535 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be
used on the register file as well. This is enabled by the fact that the register file is
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assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be
accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters, A/D converters and other I/O functions. The I/O memory can
be accessed directly or as the Data Space locations following those of the register file,
$20 - $5F.
The AVR uses a Harvard architecture concept – with separate memories and buses for
program and data. The program memory is executed with a two-stage pipeline. While
one instruction is being executed, the next instruction is pre-fetched from the program
memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory.
With the relative jump and call instructions, the whole 4K address space is directly
accessed. Most AVR instructions have a single 16-bit word format. Every program
memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the stack. The stack is effectively allocated in the general data SRAM and
consequently, the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 10-bit stack pointer (SP) is read/write-accessible in the
I/O space.
The 512 bytes data SRAM can be easily accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 5. Memory Maps
Program Memory
Data Memory
$000
Data Memory
$000
32 Gen. Purpose $0000
Working Registers $001F
$0020
64 I/O Registers
Program Flash
(4K x 16)
EEPROM
(512 x 8)
$005F
$0060
$1FF
Internal SRAM
(512 x 8)
$025F
$FFF
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program
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memory. The different interrupts have priority in accordance with their interrupt vector
position. The lower the interrupt vector address, the higher the priority.
General-purpose
Register File
Figure 6 shows the structure of the 32 general-purpose working registers in the CPU.
Figure 6. AVR CPU General-purpose Working Registers
7
0
Addr.
R0
$00
R1
$01
R2
$02
…
R13
$0D
General
R14
$0E
Purpose
R15
$0F
Working
R16
$10
Registers
R17
$11
…
R26
$1A
X-register low byte
R27
$1B
X-register high byte
R28
$1C
Y-register low byte
R29
$1D
Y-register high byte
R30
$1E
Z-register low byte
R31
$1F
Z-register high byte
All the register operating instructions in the instruction set have direct and single-cycle
access to all registers. The only exception is the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the
LDI instruction for load immediate constant data. These instructions apply to the second
half of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND,
and OR and all other operations between two registers or on a single register apply to
the entire register file.
As shown in Figure 6, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any
register in the file.
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X-register, Y-register and Zregister
The registers R26..R31 have some added functions to their general-purpose usage.
These registers are address pointers for indirect addressing of the Data Space. The
three indirect address registers, X, Y, and Z, are defined in Figure 7.
Figure 7. X-, Y-, and Z-register
15
X-register
0
7
0
7
R27 ($1B)
0
R26 ($1A)
15
Y-register
0
7
0
7
R29 ($1D)
0
R28 ($1C)
15
Z-register
0
7
0
R31 ($1F)
7
0
R30 ($1E)
In the different addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different
instructions).
ALU – Arithmetic Logic
Unit
The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main
categories: arithmetic, logical and bit functions.
In-System Programmable The AT90S8535 contains 8K bytes On-chip, In-System Programmable Flash memory
for program storage. Since all instructions are 16- or 32-bit words, the Flash is orgaFlash Program Memory
nized as 4K x 16. The Flash memory has an endurance of at least 1000 write/erase
cycles. The AT90S8535 Program Counter (PC) is 12 bits wide, thus addressing the
4096 program memory addresses.
See page 99 for a detailed description on Flash data downloading.
See page 12 for the different program memory addressing modes.
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AT90S/LS8535
SRAM Data Memory
Figure 8 shows how the AT90S8535 SRAM memory is organized.
Figure 8. SRAM Organization
Register File
Data Address Space
R0
R1
R2
...
$0000
$0001
$0002
...
R29
R30
R31
I/O Registers
$00
$01
$02
...
$001D
$001E
$001F
$3D
$3E
$3F
$005D
$005E
$005F
Internal SRAM
$0060
$0061
...
$0020
$0021
$0022
...
$025E
$025F
The lower 608 data memory locations address the Register file, the I/O memory and the
internal data SRAM. The first 96 locations address the Register file + I/O memory, and
the next 512 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the
register file, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode features 63 address locations reached from the
base address given by the Y- or Z-registers.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented and incremented.
The 32 general-purpose working registers, 64 I/O registers and the 512 bytes of internal
data SRAM in the AT90S8535 are all accessible through all these addressing modes.
See the next section for a detailed description of the different addressing modes.
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Program and Data
Addressing Modes
The AT90S8535 AVR RISC microcontroller supports powerful and efficient addressing
modes for access to the program memory (Flash) and data memory (SRAM, register file
and I/O memory). This section describes the different addressing modes supported by
the AVR architecture. In the figures, OP means the operation code part of the instruction
word. To simplify, not all figures show the exact location of the addressing bits.
Register Direct, Single
Register Rd
Figure 9. Direct Single Register Addressing
The operand is contained in register d (Rd).
Register Direct, Two Registers
Rd And Rr
Figure 10. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d
(Rd).
I/O Direct
Figure 11. I/O Direct Addressing
Operand address is contained in six bits of the instruction word. n is the destination or
source register address.
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AT90S/LS8535
Data Direct
Figure 12. Direct Data Addressing
Data Space
20 19
31
OP
$0000
16
Rr/Rd
16 LSBs
15
0
$025F
A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify
the destination or source register.
Data Indirect with
Displacement
Figure 13. Data Indirect with Displacement
Data Space
$0000
15
0
Y OR Z - REGISTER
15
10
OP
6 5
n
0
a
025F
Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word.
Data Indirect
Figure 14. Data Indirect Addressing
Data Space
$0000
15
0
X, Y OR Z - REGISTER
$025F
Operand address is the contents of the X-, Y-, or the Z-register.
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Data Indirect with Predecrement
Figure 15. Data Indirect Addressing with Pre-decrement
Data Space
$0000
15
0
X, Y OR Z - REGISTER
-1
$025F
The X-, Y-, or the Z-register is decremented before the operation. Operand address is
the decremented contents of the X-, Y-, or the Z-register.
Data Indirect with Postincrement
Figure 16. Data Indirect Addressing with Post-increment
Data Space
$0000
15
0
X, Y OR Z - REGISTER
1
$025F
The X-, Y-, or the Z-register is incremented after the operation. Operand address is the
content of the X-, Y-, or the Z-register prior to incrementing.
Constant Addressing Using
the LPM Instruction
Figure 17. Code Memory Constant Addressing
$FFF
Constant byte address is specified by the Z-register contents. The 15 MSBs select word
address (0 - 4K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =
1).
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AT90S/LS8535
Indirect Program Addressing,
IJMP and ICALL
Figure 18. Indirect Program Memory Addressing
$FFF
Program execution continues at address contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register).
Relative Program Addressing,
RJMP and RCALL
Figure 19. Relative Program Memory Addressing
+1
$FFF
Program execution continues at address PC + k + 1. The relative address k is from 2048 to 2047.
EEPROM Data Memory
The AT90S8535 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described on page 51 specifying the EEPROM address registers, the
EEPROM data register and the EEPROM control register.
For the SPI data downloading, see page 99 for a detailed description.
Memory Access Times
and Instruction
Execution Timing
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks and functions per power-unit.
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Figure 20. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 21 shows the internal timing concept for the register file. In a single clock cycle
an ALU operation using two register operands is executed and the result is stored back
to the destination register.
Figure 21. Single Cycle ALU Operation
T1
T2
T3
T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The internal data SRAM access is performed in two System Clock cycles as described
in Figure 22.
Figure 22. On-chip Data SRAM Access Cycles
T1
T2
T3
T4
System Clock Ø
WR
Data
RD
16
Address
Write
Data
Prev. Address
Read
Address
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AT90S/LS8535
I/O Memory
The I/O space definition of the AT90S8535 is shown in Table 1.
Table 1. AT90S8535 I/O Space
I/O Address
(SRAM Address)
Name
Function
$3F ($5F)
SREG
Status REGister
$3E ($5E)
SPH
Stack Pointer High
$3D ($5D)
SPL
Stack Pointer Low
$3B ($5B)
GIMSK
General Interrupt MaSK register
$3A ($5A)
GIFR
General Interrupt Flag Register
$39 ($59)
TIMSK
$38 ($58)
TIFR
$35 ($55)
MCUCR
MCU general Control Register
$34 ($45)
MCUSR
MCU general Status Register
$33 ($53)
TCCR0
Timer/Counter0 Control Register
$32 ($52)
TCNT0
Timer/Counter0 (8-bit)
$2F ($4F)
TCCR1A
Timer/Counter1 Control Register A
$2E ($4E)
TCCR1B
Timer/Counter1 Control Register B
$2D ($4D)
TCNT1H
Timer/Counter1 High Byte
$2C ($4C)
TCNT1L
Timer/Counter1 Low Byte
$2B ($4B)
OCR1AH
Timer/Counter1 Output Compare Register A High Byte
$2A ($4A)
OCR1AL
Timer/Counter1 Output Compare Register A Low Byte
$29 ($49)
OCR1BH
Timer/Counter1 Output Compare Register B High Byte
$28 ($48)
OCR1BL
Timer/Counter1 Output Compare Register B Low Byte
$27 ($47)
ICR1H
T/C 1 Input Capture Register High Byte
$26 ($46)
ICR1L
T/C 1 Input Capture Register Low Byte
$25 ($45)
TCCR2
Timer/Counter2 Control Register
$24 ($44)
TCNT2
Timer/Counter2 (8-bit)
$23 ($43)
OCR2
Timer/Counter2 Output Compare Register
$22 ($42)
ASSR
Asynchronous Mode Status Register
$21 ($41)
WDTCR
Watchdog Timer Control Register
$1F ($3E)
EEARH
EEPROM Address Register High Byte
$1E ($3E)
EEARL
EEPROM Address Register Low Byte
$1D ($3D)
EEDR
EEPROM Data Register
$1C ($3C)
EECR
EEPROM Control Register
$1B ($3B)
PORTA
Data Register, Port A
$1A ($3A)
DDRA
Data Direction Register, Port A
$19 ($39)
PINA
Input Pins, Port A
$18 ($38)
PORTB
Timer/Counter Interrupt MaSK register
Timer/Counter Interrupt Flag register
Data Register, Port B
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Table 1. AT90S8535 I/O Space (Continued)
I/O Address
(SRAM Address)
Name
Function
$17 ($37)
DDRB
Data Direction Register, Port B
$16 ($36)
PINB
Input Pins, Port B
$15 ($35)
PORTC
Data Register, Port C
$14 ($34)
DDRC
Data Direction Register, Port C
$13 ($33)
PINC
Input Pins, Port C
$12 ($32)
PORTD
Data Register, Port D
$11 ($31)
DDRD
Data Direction Register, Port D
$10 ($30)
PIND
Input Pins, Port D
$0F ($2F)
SPDR
SPI I/O Data Register
$0E ($2E)
SPSR
SPI Status Register
$0D ($2D)
SPCR
SPI Control Register
$0C ($2C)
UDR
UART I/O Data Register
$0B ($2B)
USR
UART Status Register
$0A ($2A)
UCR
UART Control Register
$09 ($29)
UBRR
UART Baud Rate Register
$08 ($28)
ACSR
Analog Comparator Control and Status Register
$07 ($27)
ADMUX
ADC Multiplexer Select Register
$06 ($26)
ADCSR
ADC Control and Status Register
$05 ($25)
ADCH
ADC Data Register High
$04 ($24)
ADCL
ADC Data Register Low
Note:
Reserved and unused locations are not shown in the table.
All AT90S8535 I/Os and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions transferring data between the 32 general-purpose working registers and the I/O space. I/O registers within the address range $00 $1F are directly bit-accessible using the SBI and CBI instructions. In these registers,
the value of single bits can be checked by using the SBIS and SBIC instructions. Refer
to the instruction set section for more details. When using the I/O specific commands IN
and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as
SRAM, $20 must be added to these addresses. All I/O register addresses throughout
this document are shown with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O register, writing a “1” back into any
flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers
$00 to $1F only.
The I/O and peripherals control registers are explained in the following sections.
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AT90S/LS8535
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AT90S/LS8535
Status Register – SREG
The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:
Bit
7
6
5
4
3
2
1
0
$3F ($5F)
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after
an interrupt has occurred and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
into T by the BST instruction and a bit in T can be copied into a bit in a register in the
register file by the BLD instruction.
• Bit 5 – H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4 – S: Sign Bit, S = N⊄⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruction Set description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the
Instruction Set description for detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
See the Instruction Set description for detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logic operation. See the
Instruction Set description for detailed information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruction Set description for detailed information.
Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by
software.
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1041H–11/01
Stack Pointer – SP
The AT90S8535 Stack Pointer is implemented as two 8-bit registers in the I/O space
locations $3E ($5E) and $3D ($5D). As the AT90S8535 data memory has $25F locations, 10 bits are used.
Bit
15
14
13
12
11
10
9
8
$3E ($5E)
–
–
–
–
–
–
SP9
SP8
SPH
$3D ($5D)
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
Read/Write
Initial Value
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt stacks are located. This stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when
data is pushed onto the stack with the PUSH instruction and it is decremented by 2
when an address is pushed onto the stack with subroutine calls and interrupts. The
Stack Pointer is incremented by 1 when data is popped from the stack with the POP
instruction and it is incremented by 2 when an address is popped from the stack with
return from subroutine RET or return from interrupt RETI.
Reset and Interrupt
Handling
The AT90S8535 provides 16 different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space.
All interrupts are assigned individual enable bits that must be set (one) together with the
I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 (the External
Interrupt Request 0), etc.
Table 2. Reset and Interrupt Vectors
20
Vector No.
Program Address
Source
Interrupt Definition
1
$000
RESET
Hardware Pin, Power-on Reset and
Watchdog Reset
2
$001
INT0
External Interrupt Request 0
3
$002
INT1
External Interrupt Request 1
4
$003
TIMER2 COMP
Timer/Counter2 Compare Match
5
$004
TIMER2 OVF
Timer/Counter2 Overflow
6
$005
TIMER1 CAPT
Timer/Counter1 Capture Event
7
$006
TIMER1 COMPA
Timer/Counter1 Compare Match A
8
$007
TIMER1 COMPB
Timer/Counter1 Compare Match B
9
$008
TIMER1 OVF
Timer/Counter1 Overflow
10
$009
TIMER0 OVF
Timer/Counter0 Overflow
11
$00A
SPI, STC
SPI Serial Transfer Complete
12
$00B
UART, RX
UART, Rx Complete
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Table 2. Reset and Interrupt Vectors (Continued)
Vector No.
Program Address
Source
Interrupt Definition
13
$00C
UART, UDRE
UART Data Register Empty
14
$00D
UART, TX
UART, Tx Complete
15
$00E
ADC
ADC Conversion Complete
16
$00F
EE_RDY
EEPROM Ready
17
$010
ANA_COMP
Analog Comparator
The most typical and general program setup for the Reset and Interrupt vector
addresses are:
Address Labels
Code
$000
rjmp
RESET
; Reset Handler
$001
rjmp
EXT_INT0
; IRQ0 Handler
$002
rjmp
EXT_INT1
; IRQ1 Handler
$003
rjmp
TIM2_COMP
; Timer2 Compare Handler
$004
rjmp
TIM2_OVF
; Timer2 Overflow Handler
$005
rjmp
TIM1_CAPT
; Timer1 Capture Handler
$006
rjmp
TIM1_COMPA
; Timer1 CompareA Handler
$007
rjmp
TIM1_COMPB
; Timer1 CompareB Handler
$008
rjmp
TIM1_OVF
$009
rjmp
TIM0_OVF
; Timer0 Overflow Handler
$00a
rjmp
SPI_STC;
; SPI Transfer Complete Handler
$00b
rjmp
UART_RXC
; UART RX Complete Handler
$00c
rjmp
UART_DRE
; UDR Empty Handler
$00d
rjmp
UART_TXC
; UART TX Complete Handler
$00e
Handler
rjmp
ADC
; ADC Conversion Complete Interrupt
$00f
rjmp
EE_RDY
; EEPROM Ready Handler
$010
rjmp
ANA_COMP
; Analog Comparator Handler
ldi
r16, high(RAMEND); Main program start
$012
out
SPH,r16
$013
ldi
r16, low(RAMEND) ;
$014
out
SPL,r16
$015
<instr> xxx
$011
…
Reset Sources
MAIN:
…
…
Comments
; Timer1 Overflow Handler
…
The AT90S8535 has three sources of reset:
•
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (VPOT).
•
External Reset. The MCU is reset when a low level is present on the RESET pin for
more than 50 ns.
•
Watchdog Reset. The MCU is reset when the Watchdog timer period expires and
the Watchdog is enabled.
During reset, all I/O registers are set to their initial values and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP
(relative jump) instruction to the reset handling routine. If the program never enables an
interrupt source, the interrupt vectors are not used and regular program code can be
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1041H–11/01
placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 3
defines the timing and electrical parameters of the reset circuitry.
Figure 23. Reset Logic
Table 3. Reset Characteristics (VCC = 5.0V)
Symbol
VPOT(1)
Parameter
Min
Typ
Max
Units
Power-on Reset Threshold (rising)
1.0
1.4
1.8
V
Power-on Reset Threshold (falling)
0.4
0.6
0.8
V
VRST
RESET Pin Threshold Voltage
tTOUT
Reset Delay Time-out Period
FSTRT Unprogrammed
11.0
16.0
21.0
ms
tTOUT
Reset Delay Time-out Period
FSTRT Programmed
1.0
1.1
1.2
ms
Note:
0.6 VCC
V
1. The Power-on Reset will not work unless the supply voltage has been below VPOT
(falling).
Table 4. Number of Watchdog Oscillator Cycles
FSTRT
Power-on Reset
Time-out at VCC = 5V
Number of WDT Cycles
Programmed
1.1 ms
1K
Unprogrammed
16.0 ms
16K
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As
shown in Figure 23, an internal timer clocked from the Watchdog Timer oscillator prevents the MCU from starting until after a certain period after VCC has reached the Poweron Threshold voltage (VPOT), regardless of the VCC rise time (see Figure 24).
The user can select the start-up time according to typical oscillator start-up time. The
number of WDT oscillator cycles is shown in Table 4. The frequency of the Watchdog
oscillator is voltage-dependent as shown in “Typical Characteristics” on page 107.
If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via
an external pull-up resistor. By holding the pin low for a period after V CC has been
applied, the Power-on Reset period can be extended. Refer to Figure 25 for a timing
example of this.
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AT90S/LS8535
1041H–11/01
AT90S/LS8535
Figure 24. MCU Start-up, RESET Tied to VCC.
VCC
RESET
VPOT
VRST
tTOUT
TIME-OUT
INTERNAL
RESET
Figure 25. MCU Start-up, RESET Controlled Externally
VCC
RESET
VPOT
VRST
TIME-OUT
tTOUT
INTERNAL
RESET
External Reset
An external reset is generated by a low level on the RESET pin. Reset pulses longer
than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not
guaranteed to generate a reset. When the applied signal reaches the Reset Threshold
Voltage (VRST) on its positive edge, the delay timer starts the MCU after the Time-out
period tTOUT has expired.
Figure 26. External Reset during Operation
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1041H–11/01
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period
tTOUT. Refer to page 49 for details on operation of the Watchdog.
Figure 27. Watchdog Reset during Operation
MCU Status Register –
MCUSR
The MCU Status Register provides information on which reset source caused an MCU
reset.
Bit
7
6
5
4
3
2
1
0
$34 ($54)
–
–
–
–
–
–
EXTRF
PORF
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
MCUSR
See Bit Description
• Bits 7..2 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read as zero.
• Bit 1 – EXTRF: External Reset Flag
After a power-on reset, this bit is undefined (X). It can only be set by an External Reset.
A Watchdog Reset will leave this bit unchanged. The bit is cleared by writing a logical
zero to the bit.
• Bit 0 – PORF: Power-on Reset Flag
This bit is only set by a Power-on Reset. A Watchdog Reset or an External Reset will
leave this bit unchanged. The bit is cleared by writing a logical zero to the bit.
To summarize, Table 5 shows the value of these two bits after the three modes of reset.
Table 5. PORF and EXTRF Values after Reset
Reset Source
EXTRF
PORF
Power-on Reset
Undefined
1
External Reset
1
Unchanged
Unchanged
Unchanged
Watchdog Reset
To make use of these bits to identify a reset condition, the user software should clear
both the PORF and EXTRF bits as early as possible in the program. Checking the
PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before
an External or Watchdog Reset occurs, the source of reset can be found by using Table
6.
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AT90S/LS8535
1041H–11/01
AT90S/LS8535
Table 6. Reset Source Identification
Interrupt Handling
EXTRF
PORF
Reset Source
0
0
Watchdog Reset
0
1
Power-on Reset
1
0
External Reset
1
1
Power-on Reset
The AT90S8535 has two 8-bit interrupt mask control registers: GIMSK (General Interrupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding
interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until
the interrupt is enabled or the flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one) and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by
software.
General Interrupt Mask
Register – GIMSK
Bit
7
6
5
4
3
2
1
0
$3B ($5B)
INT1
INT0
–
–
–
–
–
–
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
GIMSK
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory
address $002. See also “External Interrupts.”
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is configured as an output. The corre-
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1041H–11/01
sponding interrupt of External Interrupt Request 0 is executed from program memory
address $001. See also “External Interrupts.”
• Bits 5.0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read as zero.
General Interrupt Flag
Register – GIFR
Bit
7
6
5
4
3
2
1
0
$3A ($5A)
INTF1
INTF0
–
–
–
–
–
–
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
GIFR
• Bit 7 – INTF1: External Interrupt Flag1
When an edge or logical change on the INT1 pin triggers an interrupt request, INTF1
becomes set (one). This flag is always cleared (0) when the pin is configured for lowlevel interrupts, as the state of a low-level interrupt can be determined by reading the
PIN register.
If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the
interrupt address $002. For edge and logic change interrupts, this flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical “1” to it.
• Bit 6 – INTF0: External Interrupt Flag0
When an edge or logical change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). This flag is always cleared (0) when the pin is configured for lowlevel interrupts, as the state of a low-level interrupt can be determined by reading the
PIN register.
If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the
interrupt address $001. For edge and logic change interrupts, this flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical “1” to it.
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read as zero.
Timer/Counter Interrupt Mask
Register – TIMSK
Bit
7
6
5
4
3
2
1
0
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
–
TOIE0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Initial Value
0
0
0
0
0
0
0
0
$39 ($59)
TIMSK
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at
vector $003) is executed if a compare match in Timer/Counter2 occurs (i.e., when the
OCF2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set
in the Timer/Counter Interrupt Flag Register [TIFR]).
26
AT90S/LS8535
1041H–11/01
AT90S/LS8535
• Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt
(at vector $005) is executed if a capture-triggering event occurs on pin 20, PD6 (ICP)
(i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 4 – OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at
vector $006) is executed if a CompareA match in Timer/Counter1 occurs (i.e., when the
OCF1A bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 3 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at
vector $007) is executed if a CompareB match in Timer/Counter1 occurs (i.e., when the
OCF1B bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$008) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set
in the Timer/Counter Interrupt Flag Register [TIFR]).
• Bit 1 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8535 and always reads zero.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector
$009) is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set
in the Timer/Counter Interrupt Flag Register [TIFR]).
Timer/Counter Interrupt Flag
Register – TIFR
Bit
7
6
5
4
3
2
1
0
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
–
TOV0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Initial Value
0
0
0
0
0
0
0
0
$38 ($58)
TIFR
• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when compare match occurs between the Timer/Counter2
and the data in OCR2 (Output Compare Register2). OCF2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by
writing a logical “1” to the flag. When the I-bit in SREG and OCIE2 (Timer/Counter2
Compare Match Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2
Compare Match Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE2
(Ti mer /Counter 2 O v erfl ow Inte rr upt Enabl e) and TOV 2 ar e s et ( one ), the
Timer/Counter2 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter1 advances from $0000.
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1041H–11/01
• Bit 5 – ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit
and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture Interrupt is executed.
• Bit 4 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1A (Output Compare Register 1A). OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare Match InterruptA Enable) and the OCF1A are set (one), the
Timer/Counter1 Compare A Match Interrupt is executed.
• Bit 3 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1B (Output Compare Register 1B). OCF1B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1B is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1B
(Timer/Counter1 Compare Match InterruptB Enable) and the OCF1B are set (one), the
Timer/Counter1 Compare Match B Interrupt is executed.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1
(Ti mer /Counter 1 O v erfl ow Inte rr upt Enabl e) and TOV 1 ar e s et ( one ), the
Timer/Counter1 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter1 advances from $0000.
• Bit 1 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8535 and always reads zero.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0
(Ti mer /Counter 0 O v erfl ow Inte rr upt Enabl e) and TOV 0 ar e s et ( one ), the
Timer/Counter0 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter1 advances from $0000.
External Interrupts
The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs.
This feature provides a way of generating a software interrupt. The external interrupts
can be triggered by a falling or rising edge or a low level. This is set up as indicated in
the specification for the MCU Control Register (MCUCR). When the external interrupt is
enabled and is configured as level-triggered, the interrupt will trigger as long as the pin
is held low.
The external interrupts are set up as described in the specification for the MCU Control
Register (MCUCR).
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AT90S/LS8535
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. Four clock cycles after the interrupt flag has been set, the program vector
address for the actual interrupt handling routine is executed. During this 4-clock-cycle
period, the Program Counter (2 bytes) is pushed onto the stack and the Stack Pointer is
decremented by 2. The vector is normally a relative jump to the interrupt routine and this
jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served.
A return from an interrupt handling routine (same as for a subroutine call routine) takes
four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is
popped back from the stack, the Stack Pointer is incremented by 2 and the I-flag in
SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
MCU Control Register –
MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit
7
6
5
4
3
2
1
0
$35 ($55)
–
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8535 and always reads zero.
• Bit 6 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP
instruction is executed. To avoid the MCU entering the Sleep Mode unless it is the programmer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the
execution of the SLEEP instruction.
• Bits 5, 4 – SM1/SM0: Sleep Mode Select Bits 1 and 0
These bits select between the three available sleep modes as shown in Table 7.
Table 7. Sleep Mode Select
SM1
SM0
Sleep Mode
0
0
Idle
0
1
Reserved
1
0
Power-down
1
1
Power Save
• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bits 1 and 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the
corresponding interrupt mask in the GIMSK is set. The level and edges on the external
INT1 pin that activate the interrupt are defined in Table 8.
29
1041H–11/01
Table 8. Interrupt 1 Sense Control
ISC11
ISC10
Description
0
0
The low level of INT1 generates an interrupt request.
0
1
Reserved
1
0
The falling edge of INT1 generates an interrupt request.
1
1
The rising edge of INT1 generates an interrupt request.
The value on the INT pin is sampled before detecting edges. If edge interrupt is
selected, pulses that last longer than one CPU clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate
an interrupt request as long as the pin is held low.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bits 1 and 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask is set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 9.
Table 9. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
0
The low level of INT0 generates an interrupt request.
0
1
Reserved
1
0
The falling edge of INT0 generates an interrupt request.
1
1
The rising edge of INT0 generates an interrupt request.
The value on the INT pin is sampled before detecting edges. If edge interrupt is
selected, pulses that last longer than one CPU clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate
an interrupt request as long as the pin is held low.
Sleep Modes
To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a
SLEEP instruction must be executed. The SM0 and SM1 bits in the MCUCR register
select which sleep mode (Idle, Power-down or Power Save) will be activated by the
SLEEP instruction. See Table 7.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up,
executes the interrupt routine and resumes execution from the instruction following
SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset
occurs during Sleep Mode, the MCU wakes up and executes from the Reset vector.
Idle Mode
30
When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the
Idle Mode, stopping the CPU but allowing SPI, UARTs, Analog Comparator, ADC,
Timer/Counters, Watchdog and the interrupt system to continue operating. This enables
the MCU to wake up from external triggered interrupts as well as internal ones like the
Timer Overflow and UART Receive Complete interrupts. If wake-up from the Analog
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Comparator Interrupt is not required, the Analog Comparator can be powered down by
setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This
will reduce power consumption in Idle Mode. When the MCU wakes up from Idle Mode,
the CPU starts program execution immediately.
Power-down Mode
When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the
Power-down mode. In this mode, the external oscillator is stopped while the external
interrupts and the Watchdog (if enabled) continue operating. Only an external reset, a
Watchdog reset (if enabled) or an external level interrupt can wake up the MCU.
Note that when a level-triggered interrupt is used for wake-up from power-down, the low
level must be held for a time longer than the reset delay Time-out period tTOUT.
When waking up from Power-down mode, a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable
after having been stopped. The wake-up period is equal to the reset period, as shown in
Table 3 on page 22.
If the wake-up condition disappears before the MCU wakes up and starts to execute,
e.g., a low-level on is not held long enough, the interrupt causing the wake-up will not be
executed.
Power Save Mode
When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power
Save Mode. This mode is identical to Power -down, with one exception: If
Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set,
Timer/Counter2 will run during sleep. In addition to the power-down wake-up sources,
the device can also wake up from either a Timer Overflow or Output Compare event
from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK and the global interrupt enable bit in SREG is set.
When waking up from Power Save Mode by an external interrupt, two instruction cycles
are executed before the interrupt flags are updated. When waking up by the asynchronous timer, three instruction cycles are executed before the flags are updated. During
these cycles, the processor executes instructions, but the interrupt condition is not readable and the interrupt routine has not started yet.
When waking up from Power Save Mode by an asynchronous timer interrupt, the part
will wake up even if global interrupts are disabled. To ensure that the part executes the
interrupt routine when waking up, also set the global interrupt enable bit in SREG.
If the asynchronous timer is not clocked asynchronously, Power-down mode is recommended instead of Power Save Mode because the contents of the registers in the
asynchronous timer should be considered undefined after wake-up in Power Save
Mode, even if AS2 is 0.
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1041H–11/01
Timer/Counters
The AT90S8535 provides three general-purpose Timer/Counters – two 8-bit T/Cs and
one 16-bit T/C. Timer/Counter2 can optionally be asynchronously clocked from an external oscillator. This oscillator is optimized for use with a 32.768 kHz watch crystal,
enabling use of Timer/Counter2 as a Real-time Clock (RTC). Timer/Counters 0 and 1
have individual prescaling selection from the same 10-bit prescaling timer.
Timer/Counter2 has its own prescaler. These Timer/Counters can either be used as a
timer with an internal clock time base or as a counter with an external pin connection
that triggers the counting.
Timer/Counter
Prescalers
Figure 28. Prescaler for Timer/Counter0 and 1
TCK0
TCK1
For Timer/Counters 0 and 1, the four different prescaled selections are: CK/8, CK/64,
CK/256 and CK/1024, where CK is the oscillator clock. For the two Timer/Counters 0
and 1, CK, external source and stop can also be selected as clock sources.
Figure 29. Timer/Counter2 Prescaler
CK
PCK2
PCK2/1024
PCK2/256
PCK2/128
PCK2/64
AS2
PCK2/32
PCK2/8
10-BIT T/C PRESCALER
TOSC1
0
CS20
CS21
CS22
TIMER/COUNTER2 CLOCK SOURCE
TCK2
32
AT90S/LS8535
1041H–11/01
AT90S/LS8535
The clock source for Timer/Counter2 prescaler is named PCK2. PCK2 is by default connected to the main system clock (CK). By setting the AS2 bit in ASSR, Timer/Counter2
prescaler is asynchronously clocked from the PC6(TOSC1) pin. This enables use of
Timer/Counter2 as a Real-time Clock (RTC). When AS2 is set, pins PC6(TOSC1) and
PC7(TOSC2) are disconnected from Port C. A crystal can then be connected between
the PC6(TOSC1) and PC7(TOSC2) pins to serve as an independent clock source for
Timer/Counter2. The oscillator is optimized for use with a 32.768 kHz crystal. Applying
an external clock source to TOSC1 is not recommended.
8-bit Timer/Counter0
Figure 30 shows the block diagram for Timer/Counter0.
The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external
pin. In addition, it can be stopped as described in the specification for the
Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the
Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the
Timer/Counter0 Control Register (TCCR0). The interrupt enable/disable settings for
Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register (TIMSK).
When Timer/Counter0 is externally clocked, the external signal is synchronized with the
oscillator frequency of the CPU. To assure proper sampling of the external clock, the
minimum time between two external clock transitions must be at least one internal CPU
clock period. The external clock signal is sampled on the rising edge of the internal CPU
clock.
The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage
with the lower prescaling opportunities. Similarly, the high prescaling opportunities make
the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions.
Figure 30. Timer/Counter0 Block Diagram
TOIE0
7
CS00
CS01
CS02
T/C0 CONTROL
REGISTER (TCCR0)
TOV0
TOV1
OCF1A
ICF1
OCF1B
TIMER INT. FLAG
REGISTER (TIFR)
OCF2
TIMER INT. MASK
REGISTER (TIMSK)
TOV2
OCIE1A
TOIE1
OCIE1B
TICIE1
TOIE2
OCIE2
8-BIT DATA BUS
T/C0 OVERFLOW IRQ
0
TIMER/COUNTER0
(TCNT0)
T/C CLK SOURCE
CONTROL
LOGIC
CK
T0
33
1041H–11/01
Timer/Counter0 Control
Register – TCCR0
Bit
7
6
5
4
3
2
1
0
$33 ($53)
–
–
–
–
–
CS02
CS01
CS00
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR0
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read zero.
• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0
The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer/Counter0.
Table 10. Clock 0 Prescale Select
CS02
CS01
CS00
Description
0
0
0
Stop, Timer/Counter0 is stopped.
0
0
1
CK
0
1
0
CK/8
0
1
1
CK/64
1
0
0
CK/256
1
0
1
CK/1024
1
1
0
External Pin T0, falling edge
1
1
1
External Pin T0, rising edge
The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes
are scaled directly from the CK oscillator clock. If the external pin modes are used, the
corresponding setup must be performed in the actual Data Direction Control Register
(cleared to zero gives an input pin).
Timer Counter 0 – TCNT0
Bit
7
6
5
4
3
2
1
0
$32 ($52)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCNT0
The Timer/Counter0 is realized as an up-counter with read and write access. If the
Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues
counting in the clock cycle following the write operation.
34
AT90S/LS8535
1041H–11/01
AT90S/LS8535
16-bit Timer/Counter1
Figure 31 shows the block diagram for Timer/Counter1.
Figure 31. Timer/Counter1 Block Diagram
TOV0
8 7
CS11
CS10
CS12
CTC1
ICNC1
ICES1
PWM11
T/C1 CONTROL
REGISTER B (TCCR1B)
PWM10
COM1B1
COM1B0
COM1A1
TOV1
OCF1A
OCF1B
T/C1 CONTROL
REGISTER A (TCCR1A)
COM1A0
OCF1A
TOV1
ICF1
T/C1 COMPARE T/C1 INPUT
MATCHB IRQ CAPTURE IRQ
TIMER INT. FLAG
REGISTER (TIFR)
ICF1
15
OCF1B
OCF2
TOIE0
TOIE1
OCIE1A
OCIE1B
TICIE1
TOIE2
OCIE2
8-BIT DATA BUS
TIMER INT. MASK
REGISTER (TIMSK)
TOV2
T/C1 COMPARE
MATCHA IRQ
T/C1 OVERFLOW IRQ
0
T/C1 INPUT CAPTURE REGISTER (ICR1)
CK
CONTROL
LOGIC
T1
CAPTURE
TRIGGER
15
8 7
0
15
8
7
T/C CLEAR
T/C CLOCK SOURCE
TIMER/COUNTER1 (TCNT1)
UP/DOWN
0
15
15
8
7
8
7
0
16 BIT COMPARATOR
16 BIT COMPARATOR
0
TIMER/COUNTER1 OUTPUT COMPARE REGISTER A
15
8
7
0
TIMER/COUNTER1 OUTPUT COMPARE REGISTER B
The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an external pin. In addition, it can be stopped as described in the specification for the
Timer/Counter1 Control Registers (TCCR1A and TCCR1B). The different status flags
(Overflow, Compare Match and Capture Event) and control signals are found in the
Timer/Counter1 Control Registers (TCCR1A and TCCR1B). The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register
(TIMSK).
When Timer/Counter1 is externally clocked, the external signal is synchronized with the
oscillator frequency of the CPU. To assure proper sampling of the external clock, the
minimum time between two external clock transitions must be at least one internal CPU
clock period. The external clock signal is sampled on the rising edge of the internal CPU
clock.
The 16-bit Timer/Counter1 features both a high-resolution and a high-accuracy usage
with the lower prescaling opportunities. Similarly, the high prescaling opportunities
makes the Timer/Counter1 useful for lower speed functions or exact timing functions
with infrequent actions.
The Timer/Counter1 supports two Output Compare functions using the Output Compare
Register 1A and B (OCR1A and OCR1B) as the data sources to be compared to the
Timer/Counter1 contents. The Output Compare functions include optional clearing of
35
1041H–11/01
the counter on compareA match and actions on the Output Compare pins on both compare matches.
Timer/Counter1 can also be used as an 8-, 9- or 10-bit Pulse Width Modulator. In this
mode the counter and the OCR1A/OCR1B registers serve as a dual glitch-free standalone PWM with centered pulses. Refer to page 40 for a detailed description of this
function.
The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1
contents to the Input Capture Register (ICR1), triggered by an external event on the
Input Capture Pin (ICP). The actual capture event settings are defined by the
Timer/Counter1 Control Register (TCCR1B). In addition, the Analog Comparator can be
set to trigger the input capture. Refer to “Analog Comparator” on page 66 for details on
this. The ICP pin logic is shown in Figure 32.
Figure 32. ICP Pin Schematic Diagram
If the Noise Canceler function is enabled, the actual trigger condition for the capture
event is monitored over four samples and all four must be equal to activate the capture
flag. The input pin signal is sampled at XTAL clock frequency.
Timer/Counter1 Control
Register A – TCCR1A
Bit
7
6
5
4
3
2
1
0
COM1A1
COM1A0
COM1B1
COM1B0
–
–
PWM11
PWM10
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
$2F ($4F)
TCCR1A
• Bits 7, 6 – COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a
compare match in Timer/Counter1. Any output pin actions affect pin OC1A (Output
CompareA pin 1). This is an alternative function to an I/O port and the corresponding
direction control bit must be set (one) to control an output pin. The control configuration
is shown in Table 11.
• Bits 5, 4 – COM1B1, COM1B0: Compare Output Mode1B, Bits 1 and 0
The COM1B1 and COM1B0 control bits determine any output pin action following a
compare match in Timer/Counter1. Any output pin actions affect pin OC1B (Output
CompareB). This is an alternative function to an I/O port and the corresponding direction
control bit must be set (one) to control an output pin. The control configuration is given in
Table 11.
36
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Table 11. Compare 1 Mode Select
COM1X1
COM1X0
0
0
Timer/Counter1 disconnected from output pin OC1X
0
1
Toggle the OC1X output line.
1
0
Clear the OC1X output line (to zero).
1
Set the OC1X output line (to one).
1
Note:
Description
X = A or B.
In PWM mode, these bits have a different function. Refer to Table 15 for a detailed
description. When changing the COM1X1/COM1X0 bits, Output Compare Interrupt 1
must be disabled by clearing their Interrupt Enable bits in the TIMSK Register. Otherwise an interrupt can occur when the bits are changed.
• Bits 3..2 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read zero.
• Bits 1..0 – PWM11, PWM10: Pulse Width Modulator Select Bits
These bits select PWM operation of Timer/Counter1 as specified in Table 12. This mode
is described on page 40.
Table 12. PWM Mode Select
Timer/Counter1 Control
Register B – TCCR1B
PWM11
PWM10
0
0
PWM operation of Timer/Counter1 is disabled
0
1
Timer/Counter1 is an 8-bit PWM
1
0
Timer/Counter1 is a 9-bit PWM
1
1
Timer/Counter1 is a 10-bit PWM
Bit
Description
7
6
5
4
3
2
1
0
$2E ($4E)
ICNC1
ICES1
–
–
CTC1
CS12
CS11
CS10
Read/Write
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR1B
• Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)
When the ICNC1 bit is cleared (zero), the Input Capture Trigger Noise Canceler function
is disabled. The input capture is triggered at the first rising/falling edge sampled on the
ICP (input capture pin) as specified. When the ICNC1 bit is set (one), four successive
samples are measured on the ICP (input capture pin), and all samples must be high/low
according to the input capture trigger specification in the ICES1 bit. The actual sampling
frequency is XTAL clock frequency.
• Bit 6 – ICES1: Input Capture1 Edge Select
While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the
Input Capture Register (ICR1) on the falling edge of the input capture pin (ICP). While
the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register (ICR1) on the rising edge of the input capture pin (ICP).
• Bits 5, 4 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read zero.
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1041H–11/01
• Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match
When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock
cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the compare match is
detected in the CPU clock cycle following the match, this function will behave differently
when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used
and the compareA register is set to C, the timer will count as follows if CTC1 is set:
... | C-2 | C-1 | C | 0 | 1 |...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,
0, 0, 0, 0, 0, 0 |1,1,1,1,1,1,1,1|...
In PWM mode, this bit has no effect.
• Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0
The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1.
Table 13. Clock 1 Prescale Select
CS12
CS11
CS10
Description
0
0
0
Stop, the Timer/Counter1 is stopped.
0
0
1
CK
0
1
0
CK/8
0
1
1
CK/64
1
0
0
CK/256
1
0
1
CK/1024
1
1
0
External Pin T1, falling edge
1
1
1
External Pin T1, rising edge
The Stop condition provides a Timer Enable/Disable function. The CK down divided
modes are scaled directly from the CK oscillator clock. If the external pin modes are
used, the corresponding setup must be performed in the actual Direction Control Register (cleared to zero gives an input pin).
Timer/Counter1 – TCNT1H
AND TCNT1L
Bit
$2D ($4D)
15
14
13
12
11
10
9
TCNT1H
$2C ($4C)
Read/Write
Initial Value
8
MSB
LSB
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCNT1L
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To
ensure that both the high and low bytes are read and written simultaneously when the
CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and
ICR1. If the main program and also interrupt routines perform access to registers using
38
AT90S/LS8535
1041H–11/01
AT90S/LS8535
TEMP, interrupts must be disabled during access from the main program (and from
interrupt routines if interrupts are allowed from within interrupt routines).
•
TCNT1 Timer/Counter1 Write:
When the CPU writes to the high byte TCNT1H, the written data is placed in the
TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is
combined with the byte data in the TEMP register, and all 16 bits are written to the
TCNT1 Timer/Counter1 register simultaneously. Consequently, the high byte
TCNT1H must be accessed first for a full 16-bit register write operation.
•
TCNT1 Timer/Counter1 Read:
When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent
to the CPU and the data of the high byte TCNT1H is placed in the TEMP register.
When the CPU reads the data in the high byte TCNT1H, the CPU receives the data
in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for
a full 16-bit register read operation.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read
and write access. If Timer/Counter1 is written to and a clock source is selected, the
Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value.
Timer/Counter1 Output
Compare Register – OCR1AH
AND OCR1AL
Bit
$2B ($4B)
15
14
13
12
11
10
9
OCR1AH
$2A ($4A)
Read/Write
Initial Value
Timer/Counter1 Output
Compare Register – OCR1BH
AND OCR1BL
Bit
$29 ($49)
LSB
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
MSB
Initial Value
OCR1AL
OCR1BH
$28 ($48)
Read/Write
8
MSB
LSB
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OCR1BL
The output compare registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the
Timer/Counter1 Control and Status registers. A compare match only occurs if
Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A
or OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag in the CPU clock cycle following the
compare event.
Since the Output Compare Registers (OCR1A and OCR1B) are 16-bit registers, a temporary register (TEMP) is used when OCR1A/B are written to ensure that both bytes are
updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the
data is temporarily stored in the TEMP register. When the CPU writes the low byte,
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1041H–11/01
OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or
OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a
full 16-bit register write operation.
The TEMP register is also used when accessing TCNT1 and ICR1. If the main program
and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program.
Timer/Counter1 Input Capture
Register – ICR1H AND ICR1L
Bit
15
$27 ($47)
14
13
12
11
10
9
8
MSB
ICR1H
$26 ($46)
LSB
7
Read/Write
Initial Value
6
5
4
3
2
1
ICR1L
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The Input Capture Register is a 16-bit read-only register.
When the rising or falling edge (according to the input capture edge setting [ICES1]) of
the signal at the input capture pin (ICP) is detected, the current value of the
Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time,
the input capture flag (ICF1) is set (one).
Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register
(TEMP) is used when ICR1 is read to ensure that both bytes are read simultaneously.
When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of
the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in
the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently,
the low-byte ICR1L must be accessed first for a full 16-bit register read operation.
The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the
main program and interrupt routines perform access to registers using TEMP, interrupts
must be disabled during access from the main program.
Timer/Counter1 In PWM Mode
When the PWM mode is selected, Timer/Counter1, the Output Compare Register1A
(OCR1A) and the Output Compare Register1B (OCR1B) form a dual 8-, 9- or 10-bit,
free-running, glitch-free and phase-correct PWM with outputs on the PD5(OC1A) and
PD4(OC1B) pins. Timer/Counter1 acts as an up/down counter, counting up from $0000
to TOP (see Table 14), where it turns and counts down again to zero before the cycle is
repeated. When the counter value matches the contents of the 10 least significant bits of
OCR1A or OCR1B, the PD5(OC1A)/PD4(OC1B) pins are set or cleared according to
the settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1
Control Register (TCCR1A). Refer to Table 15 for details.
Table 14. Timer TOP Values and PWM Frequency
PWM Resolution
Timer TOP value
Frequency
8-bit
$00FF (255)
fTCK1/510
9-bit
$01FF (511)
fTCK1/1022
10-bit
$03FF(1023)
fTCK1/2046
Note that if the Compare Register contains the TOP value and the prescaler is not in
use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the
40
AT90S/LS8535
1041H–11/01
AT90S/LS8535
up-counting and down-counting values are reached simultaneously. When the prescaler
is in use (CS12..CS10 ≠ 001 or 000), the PWM output goes active when the counter
reaches TOP value, but the down-counting compare match is not interpreted to be
reached before the next time the counter reaches the TOP value, making a one-period
PWM pulse.
Table 15. Compare1 Mode Select in PWM Mode
COM1X1
COM1X0
0
0
Not connected
0
1
Not connected
1
0
Cleared on compare match, up-counting. Set on compare match,
down-counting (non-inverted PWM).
1
1
Cleared on compare match, down-counting. Set on compare match,
up-counting (inverted PWM).
Note:
Effect on OCX1
X = A or B
Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written,
are transferred to a temporary location. They are latched when Timer/Counter1 reaches
the value TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the
event of an unsynchronized OCR1A/OCR1B write. See Figure 33 for an example.
Figure 33. Effects of Unsynchronized OCR1 Latching
Compare Value changes
Counter Value
Compare Value
PWM Output OC1X
Synchronized
OCR1X Latch
Compare Value changes
Counter Value
Compare Value
PWM Output OC1X
Unsynchronized
OCR1X Latch
Glitch
Note: X = A or B
During the time between the write and the latch operations, a read from OCR1A or
OCR1B will read the contents of the temporary location. This means that the most
recently written value always will read out of OCR1A/B.
When the OCR1A/OCR1B contains $0000 or TOP, the output OC1A/OC1B is updated
to low or high on the next compare match according to the settings of
COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 16.
Table 16. PWM Outputs OCR1X = $0000 or TOP
COM1X1
COM1X0
OCR1X
Output OC1X
1
0
$0000
L
41
1041H–11/01
Table 16. PWM Outputs OCR1X = $0000 or TOP
Note:
COM1X1
COM1X0
OCR1X
Output OC1X
1
0
TOP
H
1
1
$0000
H
1
X=A
1
TOP
L
In PWM mode, the Timer Overflow Flag1 (TOV1) is set when the counter advances from
$0000. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode,
i.e., it is executed when TOV1 is set, provided that Timer Overflow Interrupt1 and global
interrupts are enabled. This also applies to the Timer Output Compare1 flags and
interrupts.
8-bit Timer/Counter2
Figure 34 shows the block diagram for Timer/Counter2.
Figure 34. Timer/Counter2 Block Diagram
T/C2 OVER- T/C2 COMPARE
FLOW IRQ
MATCH IRQ
8-BIT DATA BUS
7
0
TIMER/COUNTER2
(TCNT2)
CS20
CS21
CS22
CTC2
COM20
PWM2
T/C2 CONTROL
REGISTER (TCCR2)
COM21
TOV0
TOV1
OCF1B
OCF1A
ICF1
TOV2
TIMER INT. FLAG
REGISTER (TIFR)
OCF2
TIMER INT. MASK
REGISTER (TIMSK)
TOV2
OCF2
TOIE0
TOIE1
OCIE1A
OCIE1B
TICIE1
TOIE2
OCIE2
8-BIT ASYNCH T/C2 DATA BUS
T/C CLEAR
T/C CLK SOURCE
UP/DOWN
CK
CONTROL
LOGIC
TOSC1
7
0
8-BIT COMPARATOR
0
OUTPUT COMPARE
REGISTER2 (OCR2)
CK
PCK2
ICR2UB
OCR2UB
AS2
ASYNCH. STATUS
REGISTER (ASSR)
TC2UB
7
SYNCH UNIT
The 8-bit Timer/Counter2 can select clock source from PCK2 or prescaled PCK2. It can
also be stopped as described in the specification for the Timer/Counter Control Register
(TCCR2).
The different status flags (Overflow and Compare Match) are found in the
Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the
42
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Timer/Counter Control Register (TCCR2). The interrupt enable/disable settings are
found in the Timer/Counter Interrupt Mask Register (TIMSK).
This module features a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for
lower speed functions or exact timing functions with infrequent actions.
The Timer/Counter supports an Output Compare function using the Output Compare
Register (OCR2) as the data source to be compared to the Timer/Counter contents.The
Output Compare function includes optional clearing of the counter on compare match
and action on the Output Compare Pin, PD7(OC2), on compare match. Writing to
PORTD7 does not set the OC2 value to a predetermined value.
Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode,
Timer/Counter2 and the Output Compare Register serve as a glitch-free, stand-alone
PWM with centered pulses. Refer to page 45 for a detailed description of this function.
Timer/Counter2 Control
Register – TCCR2
Bit
7
6
5
4
3
2
1
0
$25 ($45)
–
PWM2
COM21
COM20
CTC2
CS22
CS21
CS20
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR2
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8535 and always reads as zero.
• Bit 6 – PWM2: Pulse Width Modulator Enable
When set (one), this bit enables PWM mode for Timer/Counter2. This mode is described
on page 45.
• Bits 5, 4 – COM21, COM20: Compare Output Mode, Bits 1 and 0
The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an
alternative function to an I/O port and the corresponding direction control bit must be set
(one) to control an output pin. The control configuration is shown in Table 17.
Table 17. Compare Mode Select
COM21
COM20
0
0
Timer/Counter disconnected from output pin OC2
0
1
Toggle the OC2 output line.
1
0
Clear the OC2 output line (to zero).
1
Note:
Description
1
Set the OC2 output line (to one).
In PWM mode, these bits have a different function. Refer to Table 19 for a detailed
description.
• Bit 3 – CTC2: Clear Timer/Counter on Compare Match
When the CTC2 control bit is set (one), Timer/Counter2 is reset to $00 in the CPU clock
cycle after a compare match. If the control bit is cleared, Timer/Counter2 continues
counting and is unaffected by a compare match. Since the compare match is detected in
the CPU clock cycle following the match, this function will behave differently when a
prescaling higher than 1 is used for the timer. When a prescaling of 1 is used and the
compare2 register is set to C, the timer will count as follows if CTC2 is set:
... | C-2 | C-1 | C | 0 | 1 |...
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1041H–11/01
When the prescaler is set to divide by 8, the timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,
0, 0, 0, 0, 0, 0 | 1, 1, 1,...
In PWM mode, this bit has no effect.
• Bits 2, 1, 0 – CS22, CS21, CS20: Clock Select Bits 2, 1 and 0
The Clock Select bits 2,1 and 0 define the prescaling source of Timer/Counter2.
Table 18. Timer/Counter2 Prescale Select
CS22
CS21
CS20
Description
0
0
0
Timer/Counter2 is stopped.
0
0
1
PCK2
0
1
0
PCK2/ 8
0
1
1
PCK2/ 32
1
0
0
PCK2/ 64
1
0
1
PCK2/128
1
1
0
PCK2/256
1
1
1
PCK2/1024
The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes
are scaled directly from the CK oscillator clock.
Timer/Counter2 – TCNT2
Bit
7
6
5
4
3
2
1
0
$24 ($44)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCNT2
This 8-bit register contains the value of Timer/Counter2.
Timer/Counter2 is realized as an up or up/down (in PWM mode) counter with read and
write access. If the Timer/Counter2 is written to and a clock source is selected, it continues counting in the timer clock cycle following the write operation.
Timer/Counter2 Output
Compare Register – OCR2
Bit
7
6
5
4
3
2
1
0
$23 ($43)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
OCR2
The Output Compare Register is an 8-bit read/write register.
The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A
compare match only occurs if Timer/Counter2 counts to the OCR2 value. A software
write that sets TCNT2 and OCR2 to the same value does not generate a compare
match.
A compare match will set the compare interrupt flag in the CPU clock cycle following the
compare event.
44
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Timer/Counter2 in PWM Mode
When the PWM mode is selected, Timer/Counter2 and the Output Compare Register
(OCR2) form an 8-bit, free-running, glitch-free and phase correct PWM with outputs on
the PD7(OC2) pin. Timer/Counter2 acts as an up/down counter, counting up from $00 to
$FF, where it turns and counts down again to zero before the cycle is repeated. When
the counter value matches the contents of the Output Compare Register, the PD7(OC2)
pin is set or cleared according to the settings of the COM21/COM20 bits in the
Timer/Counter2 Control Register (TCCR2). Refer to Table 19 for details.
Table 19. Compare Mode Select in PWM Mode
COM21
COM20
Effect on Compare Pin
0
0
Not connected
0
1
Not connected
1
0
Cleared on compare match, up-counting. Set on compare match, downcounting (non-inverted PWM).
1
1
Cleared on compare match, down-counting time-out. Set on compare
match, up-counting (inverted PWM).
Note that in PWM mode, the Output Compare Register is transferred to a temporary
location when written. The value is latched when the Timer/Counter reaches $FF. This
prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. See Figure 35 for an example.
Figure 35. Effects of Unsynchronized OCR Latching
Compare Value changes
Counter Value
Compare Value
PWM Output
Synchronized OCR Latch
Compare Value changes
Counter Value
Compare Value
PWM Output
Unsynchronized OCR Latch
Glitch
During the time between the write and the latch operation, a read from OCR2 will read
the contents of the temporary location. This means that the most recently written value
always will read out of OCR2.
When the OCR register (not the temporary register) is updated to $00 or $FF, the PWM
output changes to low or high immediately according to the settings of COM21/COM20.
This is shown in Table 20.
Table 20. PWM Outputs OCR2 = $00 or $FF
COM21
COM20
OCR2
Output PWM2
1
0
$00
L
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1041H–11/01
Table 20. PWM Outputs OCR2 = $00 or $FF
COM21
COM20
OCR2
Output PWM2
1
0
$FF
H
1
1
$00
H
1
1
$FF
L
In PWM mode, the Timer Overflow Flag (TOV2) is set when the counter advances from
$00. Timer Overflow Interrupt2 operates exactly as in normal Timer/Counter mode, i.e.,
it is executed when TOV2 is set, provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flag and interrupt.
The frequency of the PWM will be Timer Clock Frequency divided by 510.
Asynchronous Status
Register – ASSR
Bit
7
6
5
4
3
2
1
0
$22 ($22)
–
–
–
–
AS2
TCN2UB
OCR2UB
TCR2UB
Read/Write
R
R
R
R
R/W
R
R
R
Initial Value
0
0
0
0
0
0
0
0
ASSR
• Bit 7..4 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read as zero.
• Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is set (one), Timer/Counter2 is clocked from the TOSC1 pin. Pins PC6 and
PC7 become connected to a crystal oscillator and cannot be used as general I/O pins.
When cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK.
When the value of this bit is changed, the contents of TCNT2, OCR2 and TCCR2 might
get corrupted.
• Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes
set (one). When TCNT2 has been updated from the temporary storage register, this bit
is cleared (zero) by hardware. A logical “0” in this bit indicates that TCNT2 is ready to be
updated with a new value.
• Bit 1 – OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes
set (one). When OCR2 has been updated from the temporary storage register, this bit is
cleared (zero) by hardware. A logical “0” in this bit indicates that OCR2 is ready to be
updated with a new value.
• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes
set (one). When TCCR2 has been updated from the temporary storage register, this bit
is cleared (zero) by hardware. A logical “0” in this bit indicates that TCCR2 is ready to be
updated with a new value.
If a write is performed to any of the three Timer/Counter2 registers while its Update Busy
flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2 and TCCR2 are different. When reading
TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the
temporary storage register is read.
46
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Asynchronous Operation of
Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
•
Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter2, the timer registers TCNT2, OCR2 and TCCR2 might get corrupted.
A safe procedure for switching clock source is:
1. Disable the Timer/Counter2 interrupts OCIE2 and TOIE2.
2. Select clock source by setting AS2 as appropriate.
3. Write new values to TCNT2, OCR2 and TCCR2.
4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB and
TCR2UB.
5. Clear the Timer/Counter2 interrupt flags.
6. Clear the TOV2 and OCF2 flags in TIFR.
7. Enable interrupts, if needed.
•
When writing to one of the registers TCNT2, OCR2 or TCCR2, the value is
transferred to a temporary register and latched after two positive edges on TOSC1.
The user should not write a new value before the contents of the temporary register
have been transferred to their destination. Each of the three mentioned registers
have their individual temporary register. For example, writing to TCNT2 does not
disturb an OCR2 write in progress. To detect that a transfer to the destination
register has taken place, an Asynchronous Status Register (ASSR) has been
implemented.
•
When entering a Power Save Mode after having written to TCNT2, OCR2 or
TCCR2, the user must wait until the written register has been updated if
Timer/Counter2 is used to wake up the device. Otherwise, the MCU will go to sleep
before the changes have had any effect. This is extremely important if the Output
Compare2 interrupt is used to wake up the device; Output Compare is disabled
during write to OCR2 or TCNT2. If the write cycle is not finished (i.e., the user goes
to sleep before the OCR2UB bit returns to zero), the device will never get a compare
match and the MCU will not wake up.
•
If Timer/Counter2 is used to wake up the device from Power Save Mode,
precautions must be taken if the user wants to re-enter Power Save Mode: The
interrupt logic needs one TOSC1 cycle to be reset. If the time between wake up and
re-entering Power Save Mode is less than one TOSC1 cycle, the interrupt will not
occur and the device will fail to wake up. If the user is in doubt whether the time
before re-entering Power Save is sufficient, the following algorithm can be used to
ensure that one TOSC1 cycle has elapsed:
1. Write a value to TCCR2, TCNT2 or OCR2.
2. Wait until the corresponding Update Busy flag in ASSR returns to zero.
3. Enter Power Save Mode.
•
When the asynchronous operation is selected, the 32 kHz oscillator for
Timer/Counter2 is always running, except in Power-down mode. After a power-up
reset or wake-up from power-down, the user should be aware of the fact that this
oscillator might take as long as one second to stabilize. The user is advised to wait
for at least one second before using Timer/Counter2 after power-up or wake-up from
power-down. The content of all Timer/Counter2 registers must be considered lost
after a wake-up from power-down due to the unstable clock signal upon start-up,
regardless of whether the oscillator is in use or a clock signal is applied to the TOSC
pin.
•
Description of wake-up from Power Save Mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake-up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at
47
1041H–11/01
least one before the processor can read the counter value. After wake-up, the MCU
is halted for four cycles, it executes the interrupt routine, and resumes execution
from the instruction following SLEEP.
•
48
During asynchronous operation, the synchronization of the interrupt flags for the
asynchronous timer takes three processor cycles plus one timer cycle. The timer is
therefore advanced by at least 1 before the processor can read the timer value
causing the setting of the interrupt flag. The output compare pin is changed on the
timer clock and is not synchronized to the processor clock.
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip oscillator. By controlling the
Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in
Table 21. See characterization data for typical values at other VCC levels. The WDR
(Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle
periods can be selected to determine the reset period. If the reset period expires without
another Watchdog reset, the AT90S8535 resets and executes from the reset vector. For
timing details on the Watchdog reset, refer to page 22.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be
followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 36. Watchdog Timer
Oscillator
1 MHz at VCC = 5V
350 kHz at VCC = 3V
Watchdog Timer Control
Register – WDTCR
Bit
7
6
5
4
3
2
1
0
$21 ($41)
–
–
–
WDTOE
WDE
WDP2
WDP1
WDP0
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
WDTCR
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will
not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.
Refer to the description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled and if the WDE is cleared
(zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be
followed:
49
1041H–11/01
1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must
be written to WDE even though it is set to “1” before the disable operation starts.
2. Within the next four clock cycles, write a logical “0” to WDE. This disables the
Watchdog.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
time-out periods are shown in Table 21.
Table 21. Watchdog Timer Prescale Select
Number of WDT
Oscillator Cycles
Typical Time-out
at VCC = 3.0V
Typical Time-out
at VCC = 5.0V
0
16K cycles
47 ms
15 ms
0
1
32K cycles
94 ms
30 ms
0
1
0
64K cycles
0.19 s
60 ms
0
1
1
128K cycles
0.38 s
0.12 s
1
0
0
256K cycles
0.75 s
0.24 s
1
0
1
512K cycles
1.5 s
0.49 s
1
1
0
1,024K cycles
3.0 s
0.97 s
1
1
1
2,048K cycles
6.0 s
1.9 s
WDP2
WDP1
WDP0
0
0
0
Note:
50
The frequency of the Watchdog oscillator is voltage-dependent as shown in the Electrical
Characteristics section.
The WDR (Watchdog Reset) instruction should always be executed before the Watchdog
Timer is enabled. This ensures that the reset period will be in accordance with the
Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the
Watchdog Timer may not start to count from zero.
To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset
before changing the Watchdog Timer Prescale Select.
AT90S/LS8535
1041H–11/01
AT90S/LS8535
EEPROM Read/Write
Access
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 2.5 - 4 ms, depending on the VCC voltages. A
self-timing function lets the user software detect when the next byte can be written. A
special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to
accept new data.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
EEPROM Address Register –
EEARH and EEARL
Bit
15
14
13
12
11
10
9
8
$1F ($3F)
–
–
–
–
–
–
–
EEAR8
EEARH
$1E ($3E)
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
7
6
5
4
3
2
1
0
Read/Write
Initial Value
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
The EEPROM address registers (EEARH and EEARL) specify the EEPROM address in
the 512-byte EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 511.
EEPROM Data Register –
EEDR
Bit
7
6
5
4
3
2
1
0
$1D ($3D)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EEDR
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to
the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
EEPROM Control Register –
EECR
Bit
7
6
5
4
3
2
1
0
$1C ($3C)
–
–
–
–
EERIE
EEMWE
EEWE
EERE
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EECR
• Bit 7..4 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is
enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt
generates a constant interrupt when EEWE is cleared (zero).
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1041H–11/01
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to “1” causes the EEPROM to be
written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the
selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE
has been set (one) by software, hardware clears the bit to zero after four clock cycles.
See the description of the EEWE bit for a EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable signal (EEWE) is the write strobe to the EEPROM. When
address and data are correctly set up, the EEWE bit must be set to write the value into
the EEPROM. The EEMWE bit must be set when the logical “1” is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed
when writing the EEPROM (the order of steps 2 and 3 is unessential):
1. Wait until EEWE becomes zero.
2. Write new EEPROM address to EEARL and EEARH (optional).
3. Write new EEPROM data to EEDR (optional).
4. Write a logical “1” to the EEMWE bit in EECR (to be able to write a logical “1” to
the EEMWE bit, the EEWE bit must be written to “0” in the same cycle).
5. Within four clock cycles after setting EEMWE, write a logical “1” to EEWE.
Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR and EEDR registers will
be modified, causing the interrupted EEPROM access to fail. It is recommended to have
the global interrupt flag cleared during the four last steps to avoid these problems.
When the write access time (typically 2.5 ms at VCC = 5V or 4 ms at VCC = 2.7V) has
elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit
and wait for a zero before writing the next byte. When EEWE has been set, the CPU is
halted for two clock cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable signal (EERE) is the read strobe to the EEPROM. When
the correct address is set up in the EEAR register, the EERE bit must be set. When the
EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register.
The EEPROM read access takes one instruction and there is no need to poll the EERE
bit. When EERE has been set, the CPU is halted for four clock cycles before the next
instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation
is in progress when new data or address is written to the EEPROM I/O registers, the
write operation will be interrupted and the result is undefined.
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Prevent EEPROM
Corruption
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the
same as for board level systems using the EEPROM and the same design solutions
should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage for executing instructions is too low.
EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply
voltage. This is best done by an external low VCC Reset Protection circuit, often
referred to as a Brown-out Detector (BOD). Please refer to application note AVR
180 for design considerations regarding power-on reset and low-voltage
detection.
2. Keep the AVR core in Power-down Sleep Mode during periods of low VCC. This
will prevent the CPU from attempting to decode and execute instructions, effectively protecting the EEPROM registers from unintentional writes.
3. Store constants in Flash memory if the ability to change memory contents from
software is not required. Flash memory cannot be updated by the CPU and will
not be subject to corruption.
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Serial Peripheral
Interface – SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the AT90S8535 and peripheral devices or between several AVR devices. The
AT90S8535 SPI features include the following:
• Full-duplex, 3-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Four Programmable Bit Rates
• End-of-transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
Figure 37. SPI Block Diagram
The interconnection between master and slave CPUs with SPI is shown in Figure 38.
The PB7(SCK) pin is the clock output in the Master Mode and is the clock input in the
Slave Mode. Writing to the SPI Data Register of the master CPU starts the SPI clock
generator and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI)
pin of the slave CPU. After shifting one byte, the SPI clock generator stops, setting the
end-of-transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR register is set, an interrupt is requested. The Slave Select input, PB4(SS), is set low to select
an individual slave SPI device. The two shift registers in the master and the slave can be
considered as one distributed 16-bit circular shift register. This is shown in Figure 38.
When data is shifted from the master to the slave, data is also shifted in the opposite
direction, simultaneously. During one shift cycle, data in the master and the slave is
interchanged.
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AT90S/LS8535
Figure 38. SPI Master-slave Interconnection
MSB
MASTER
LSB
MISO
MISO
8 BIT SHIFT REGISTER
SPI
CLOCK GENERATOR
MSB
MASTER
LSB
8 BIT SHIFT REGISTER
MOSI
MOSI
SCK
SCK
SS
VCC
SS
The system is single-buffered in the transmit direction and double-buffered in the
receive direction. This means that bytes to be transmitted cannot be written to the SPI
Data Register before the entire shift cycle is completed. When receiving data, however,
a received byte must be read from the SPI Data Register before the next byte has been
completely shifted in. Otherwise, the first byte is lost.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is
overridden according to Table 22.
Table 22. SPI Pin Overrides
Pin
Direction, Master SPI
Direction, Slave SPI
MOSI
User Defined
Input
MISO
Input
User Defined
SCK
User Defined
Input
SS
User Defined
Input
Note:
See “Alternate Functions of Port B” on page 79 for a detailed description of how to
define the direction of the user-defined SPI pins.
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1041H–11/01
SS Pin Functionality
When the SPI is configured as a master (MSTR in SPCR is set), the user can determine
the direction of the SS pin. If SS is configured as an output, the pin is a general output
pin, which does not affect the SPI system. If SS is configured as an input, it must be held
high to ensure master SPI operation. If the SS pin is driven low by peripheral circuitry
when the SPI is configured as master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starting to send
data to it. To avoid bus contention, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a
result of the SPI becoming a slave, the MOSI and SCK pins become inputs.
2. The SPIF flag in SPSR is set and if the SPI interrupt is enabled and the I-bit in
SREG are set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master Mode and there exists a
possibility that SS is driven low, the interrupt should always check that the MSTR bit is
still set. Once the MSTR bit has been cleared by a slave select, it must be set by the
user to re-enable the SPI Master Mode.
When the SPI is configured as a slave, the SS pin is always input. When SS is held low,
the SPI is activated and MISO becomes an output if configured so by the user. All other
pins are inputs. When SS is driven high, all pins are inputs and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once
the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI
will stop sending and receiving immediately and both data received and data sent must
be considered as lost.
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits CPHA and CPOL. The SPI data transfer formats
are shown in Figure 39 and Figure 40.
Figure 39. SPI Transfer Format with CPHA = 0 and DORD = 0
SCK CYCLE#
(FOR REFERENCE)
1
2
3
4
5
6
7
8
MSB
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(FROM MASTER)
MISO
(FROM SLAVE)
MSB
*
SS (TO SLAVE)
SAMPLE
*Not defined but normally MSB of character just received.
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AT90S/LS8535
Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0
SPI Control Register – SPCR
Bit
7
6
5
4
3
2
1
0
$0D ($2D)
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set
and the global interrupts are enabled.
• Bit 6 – SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI Mode when set (one) and Slave SPI Mode when cleared
(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared and SPIF in SPSR will become set. The user will then have to set MSTR to reenable SPI Master Mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is
low when idle. Refer to Figure 39. and Figure 40. for additional information.
• Bit 2 – CPHA: Clock Phase
Refer to Figure 40 or Figure 41 for the functionality of this bit.
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• Bits 1,0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and
SPR0 have no effect on the slave. The relationship between SCK and the oscillator
clock frequency fcl is shown in Table 23.
Table 23. Relationship between SCK and the Oscillator Frequency
SPR1
SPR0
SCK Frequency
0
0
fcl/4
0
1
fcl/16
1
0
fcl/64
1
1
fcl/128
SPI Status Register – SPSR
Bit
7
6
5
4
3
2
1
0
$0E ($2E)
SPIF
WCOL
–
–
–
–
–
–
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
SPSR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and
is driven low when the SPI is in Master Mode, this will also set the SPIF flag. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set
(one), then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write Collision flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register with WCOL set (one) and then accessing the SPI Data Register.
• Bit 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and will always read as zero.
The SPI interface on the AT90S8535 is also used for program memory and EEPROM
downloading or uploading. See page 99 for serial programming and verification.
SPI Data Register – SPDR
Bit
7
6
5
4
3
2
1
0
$0F ($2F)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
X
X
X
X
X
X
X
X
SPDR
Undefined
The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift Register. Writing to the register initiates data transmission.
Reading the register causes the Shift Register Receive buffer to be read.
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AT90S/LS8535
UART
The AT90S8535 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are:
• Baud Rate Generator that can Generate a Large Number of Baud Rates (bps)
• High Baud Rates at Low XTAL Frequencies
• 8 or 9 Bits Data
• Noise Filtering
• Overrun Detection
• Framing Error Detection
• False Start Bit Detection
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Buffered Transmit and Receive
Data Transmission
A block schematic of the UART transmitter is shown in Figure 41.
Figure 41. UART Transmitter
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data
Register, UDR. Data is transferred from UDR to the Transmit shift register when:
•
A new character is written to UDR after the stop bit from the previous character has
been shifted out. The shift register is loaded immediately.
•
A new character is written to UDR before the stop bit from the previous character
has been shifted out. The shift register is loaded when the stop bit of the character
currently being transmitted is shifted out.
If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDR to the
shift register. The UDRE (UART Data Register Empty) bit in the UART Status Register,
USR, is set. When this bit is set (one), the UART is ready to receive the next character.
At the same time as the data is transferred from UDR to the 10(11)-bit shift register, bit 0
of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word
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1041H–11/01
is selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in
UCR is transferred to bit 9 in the Transmit shift register.
On the baud rate clock following the transfer operation to the shift register, the start bit is
shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has been
shifted out, the shift register is loaded if any new data has been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR
register to send when the stop bit is shifted out, the UDRE flag will remain set until UDR
is written again. When no new data has been written and the stop bit has been present
on TXD for one bit length, the TX Complete flag (TXC) in USR is set.
The TXEN bit in UCR enables the UART Transmitter when set (one). When this bit is
cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART
Transmitter will be connected to PD1, which is forced to be an output pin regardless of
the setting of the DDD1 bit in DDRD.
Data Reception
Figure 42 shows a block diagram of the UART Receiver.
Figure 42. UART Receiver
The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times
the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as
the falling edge of a start bit and the start bit detection sequence is initiated. Let sample
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AT90S/LS8535
1 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples the
RXD pin at samples 8, 9 and 10. If two or more of these three samples are found to be
logical “1”s, the start bit is rejected as a noise spike and the receiver starts looking for
the next 1-to-0 transition.
If however, a valid start bit is detected, sampling of the data bits following the start bit is
performed. These bits are also sampled at samples 8, 9 and 10. The logical value found
in at least two of the three samples is taken as the bit value. All bits are shifted into the
Transmitter Shift register as they are sampled. Sampling of an incoming character is
shown in Figure 43.
Figure 43. Sampling Received Data
When the stop bit enters the receiver, the majority of the three samples must be one to
accept the stop bit. If two or more samples are logical “0”s, the Framing Error (FE) flag in
the UART Status Register (USR) is set. Before reading the UDR register, the user
should always check the FE bit to detect framing errors.
Whether or not a valid stop bit is detected at the end of a character reception cycle, the
data is transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically
separate registers, one for transmitted data and one for received data. When UDR is
read, the Receive Data register is accessed and when UDR is written, the Transmit
Data register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the RXB8 bit in UCR is loaded with bit 9 in the Transmit Shift
register when data is transferred to UDR.
If, after having received a character, the UDR register has not been read since the last
receive, the OverRun (OR) flag in UCR is set. This means that the last data byte shifted
into the shift register could not be transferred to UDR and has been lost. The OR bit is
buffered and is updated when the valid data byte in UDR is read. Thus, the user should
always check the OR bit after reading the UDR register in order to detect any overruns if
the baud rate is high or CPU load is high.
When the RXEN bit in the UCR register is cleared (zero), the receiver is disabled. This
means that the PD0 pin can be used as a general I/O pin. When RXEN is set, the UART
Receiver will be connected to PD0, which is forced to be an input pin regardless of the
setting of the DDD0 bit in DDRD. When PD0 is forced to input by the UART, the
PORTD0 bit can still be used to control the pull-up resistor on the pin.
When the CHR9 bit in the UCR register is set, transmitted and received characters are
9 bits long, plus start and stop bits. The ninth data bit to be transmitted is the TXB8 bit in
UCR register. This bit must be set to the wanted value before a transmission is initiated
by writing to the UDR register. The ninth data bit received is the RXB8 bit in the UCR
register.
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UART Control
UART I/O Data Register – UDR
Bit
7
6
5
4
3
2
1
0
$0C ($2C)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
UDR
The UDR register is actually two physically separate registers sharing the same I/O
address. When writing to the register, the UART Transmit Data register is written. When
reading from UDR, the UART Receive Data register is read.
UART Status Register – USR
Bit
7
6
5
4
3
2
1
0
$0B ($2B)
RXC
TXC
UDRE
FE
OR
–
–
–
Read/Write
R
R/W
R
R
R
R
R
R
Initial Value
0
0
1
0
0
0
0
0
USR
The USR register is a read-only register providing information on the UART status.
• Bit 7 – RXC: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regardless of any detected framing errors. When the RXCIE
bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is
set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used,
the UART Receive Complete Interrupt routine must read UDR in order to clear RXC,
otherwise a new interrupt will occur once the interrupt routine terminates.
• Bit 6 – TXC: UART Transmit Complete
This bit is set (one) when the entire character (including the stop bit) in the Transmit
Shift register has been shifted out and no new data has been written to UDR. This flag is
especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after
completing the transmission.
When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete
interrupt to be executed. TXC is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical
“1” to the bit.
• Bit 5 – UDRE: UART Data Register Empty
This bit is set (one) when a character written to UDR is transferred to the Transmit Shift
register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission.
When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven
data transmission is used, the UART Data Register Empty Interrupt routine must write
UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates.
UDRE is set (one) during reset to indicate that the transmitter is ready.
• Bit 4 – FE: Framing Error
This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incoming character is zero.
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AT90S/LS8535
The FE bit is cleared when the stop bit of received data is one.
• Bit 3 – OR: OverRun
This bit is set if an Overrun condition is detected, i.e., when a character already present
in the UDR register is not read before the next character has been shifted into the
Receiver Shift register. The OR bit is buffered, which means that it will be set once the
valid data still in UDR is read.
The OR bit is cleared (zero) when data is received and transferred to UDR.
• Bits 2..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and will always read as zero.
UART Control Register – UCR
Bit
7
6
5
4
3
2
1
0
$0A ($2A)
RXCIE
TXCIE
UDRIE
RXEN
TXEN
CHR9
RXB8
TXB8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
W
Initial Value
0
0
0
0
0
0
1
0
UCR
• Bit 7 – RXCIE: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete Interrupt routine to be executed provided that global interrupts are enabled.
• Bit 6 – TXCIE: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete Interrupt routine to be executed provided that global interrupts are enabled.
• Bit 5 – UDRIE: UART Data Register Empty Interrupt Enable
When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data
Register Empty Interrupt routine to be executed provided that global interrupts are
enabled.
• Bit 4 – RXEN: Receiver Enable
This bit enables the UART receiver when set (one). When the receiver is disabled, the
RXC, OR and FE status flags cannot become set. If these flags are set, turning off
RXEN does not cause them to be cleared.
• Bit 3 – TXEN: Transmitter Enable
This bit enables the UART transmitter when set (one). When disabling the transmitter
while transmitting a character, the transmitter is not disabled before the character in the
shift register plus any following character in UDR has been completely transmitted.
• Bit 2 – CHR9: 9 Bit Characters
When this bit is set (one), transmitted and received characters are 9 bits long, plus start
and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in UCR,
respectively. The ninth data bit can be used as an extra stop bit or a parity bit.
• Bit 1 – RXB8: Receive Data Bit 8
When CHR9 is set (one), RXB8 is the ninth data bit of the received character.
• Bit 0 – TXB8: Transmit Data Bit 8
When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted.
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Baud Rate Generator
The baud rate generator is a frequency divider which generates baud rates according to
the following equation:
f CK
BAUD = ------------------------------------16(UBRR + 1 )
•
BAUD = Baud rate
•
fCK = Crystal clock frequency
•
UBRR = Contents of the UART Baud Rate register, UBRR (0 - 255)
For standard crystal frequencies, the most commonly used baud rates can be generated
by using the UBRR settings in Table 24. UBRR values that yield an actual baud rate differing less than 2% from the target baud rate are boldface in the table. However, using
baud rates that have more than 1% error is not recommended. High error ratings give
less noise resistance.
Table 24. UBRR Settings at Various Crystal Frequencies (Examples)
Baud Rate
1 MHz %Error 1.8432 MHz %Error
2 MHz %Error 2.4576 MHz %Error
2400 UBRR=
25
0.2 UBRR=
47
0.0 UBRR=
51
0.2 UBRR=
63
0.0
4800 UBRR=
12
0.2 UBRR=
23
0.0 UBRR=
25
0.2 UBRR=
31
0.0
6
7.5 UBRR=
9600 UBRR=
11
0.0 UBRR=
12
0.2 UBRR=
15
0.0
3
7.8 UBRR=
8
3.7 UBRR=
10
3.1
14400 UBRR=
7
0.0 UBRR=
2
7.8 UBRR=
6
7.5 UBRR=
19200 UBRR=
5
0.0 UBRR=
7
0.0
1
7.8 UBRR=
3
7.8 UBRR=
4
6.3
28800 UBRR=
3
0.0 UBRR=
1
22.9 UBRR=
2
7.8 UBRR=
38400 UBRR=
2
0.0 UBRR=
3
0.0
0
7.8 UBRR=
1
7.8 UBRR=
2
12.5
57600 UBRR=
1
0.0 UBRR=
0
22.9 UBRR=
1
33.3 UBRR=
1
22.9 UBRR=
76800 UBRR=
1
0.0
0
84.3 UBRR=
0
7.8 UBRR=
0
25.0
115200 UBRR=
0
0.0 UBRR=
Baud Rate 3.2768 MHz %Error 3.6864 MHz %Error
4 MHz %Error
4.608 MHz %Error
2400 UBRR=
84
0.4 UBRR=
95
0.0 UBRR= 103
0.2 UBRR= 119
0.0
4800 UBRR=
42
0.8 UBRR=
47
0.0 UBRR=
51
0.2 UBRR=
59
0.0
9600 UBRR=
20
1.6 UBRR=
23
0.0 UBRR=
25
0.2 UBRR=
29
0.0
16
2.1 UBRR=
14400 UBRR=
13
1.6 UBRR=
15
0.0 UBRR=
19
0.0
10
3.1 UBRR=
19200 UBRR=
11
0.0 UBRR=
12
0.2 UBRR=
14
0.0
8
3.7 UBRR=
28800 UBRR=
6
1.6 UBRR=
7
0.0 UBRR=
9
0.0
4
6.3 UBRR=
6
7.5 UBRR=
7
6.7
38400 UBRR=
5
0.0 UBRR=
3
12.5 UBRR=
3
7.8 UBRR=
57600 UBRR=
3
0.0 UBRR=
4
0.0
2
12.5 UBRR=
2
7.8 UBRR=
3
6.7
76800 UBRR=
2
0.0 UBRR=
1
12.5 UBRR=
1
7.8 UBRR=
2
20.0
115200 UBRR=
1
0.0 UBRR=
Baud Rate 7.3728 MHz %Error
8 MHz %Error
9.216 MHz %Error 11.059 MHz %Error
2400 UBRR= 191
0.0 UBRR= 207
0.2 UBRR= 239
0.0 UBRR= 287
4800 UBRR=
95
0.0 UBRR= 103
0.2 UBRR= 119
0.0 UBRR= 143
0.0
9600 UBRR=
47
0.0 UBRR=
51
0.2 UBRR=
59
0.0 UBRR=
71
0.0
14400 UBRR=
31
0.0 UBRR=
34
0.8 UBRR=
39
0.0 UBRR=
47
0.0
19200 UBRR=
23
0.0 UBRR=
25
0.2 UBRR=
29
0.0 UBRR=
35
0.0
16
2.1 UBRR=
28800 UBRR=
15
0.0 UBRR=
19
0.0 UBRR=
23
0.0
38400 UBRR=
11
0.0 UBRR=
12
0.2 UBRR=
14
0.0 UBRR=
17
0.0
8
3.7 UBRR=
57600 UBRR=
7
0.0 UBRR=
9
0.0 UBRR=
11
0.0
6
7.5 UBRR=
7
6.7 UBRR=
76800 UBRR=
5
0.0 UBRR=
8
0.0
3
7.8 UBRR=
115200 UBRR=
3
0.0 UBRR=
4
0.0 UBRR=
5
0.0
Note:
64
Maximum baud rate to each frequency.
AT90S/LS8535
1041H–11/01
AT90S/LS8535
UART Baud Rate Register –
UBRR
Bit
7
6
5
4
3
2
1
0
$09 ($29)
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
UBRR
The UBRR register is an 8-bit read/write register that specifies the UART Baud Rate
according to the equation on the previous page.
65
1041H–11/01
Analog Comparator
The Analog Comparator compares the input values on the positive input PB2 (AIN0) and
negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher
than the voltage on the negative input PB3 (AIN1), the Analog Comparator Output
(ACO) is set (one). The comparator’s output can be set to trigger the Timer/Counter1
Input Capture function. In addition, the comparator can trigger a separate interrupt,
exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding
logic is shown in Figure 44.
Figure 44. Analog Comparator Block Diagram
Analog Comparator Control
and Status Register – ACSR
Bit
7
6
5
4
3
2
1
0
$08 ($28)
ACD
–
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
Read/Write
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
N/A
0
0
0
0
0
ACSR
• Bit 7 – ACD: Analog Comparator Disable
When this bit is set (one), the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. When changing the ACD bit,
the Analog Comparator interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise an interrupt can occur when the bit is changed.
• Bit 6 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8535 and will always read as zero.
• Bit 5 – ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logical “1” to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator interrupt is activated. When cleared (zero), the interrupt is disabled.
66
AT90S/LS8535
1041H–11/01
AT90S/LS8535
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly
connected to the Input Capture front-end logic, making the comparator utilize the noise
canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When
cleared (zero), no connection between the Analog Comparator and the Input Capture
function is given. To make the comparator trigger the Timer/Counter1 Input Capture
interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).
• Bits 1,0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events trigger the Analog Comparator interrupt.
The different settings are shown in Table 25.
Table 25. ACIS1/ACIS0 Settings
ACIS1
ACIS0
0
0
Comparator Interrupt on Output Toggle
0
1
Reserved
1
0
Comparator Interrupt on Falling Output Edge
1
1
Comparator Interrupt on Rising Output Edge
Note:
Interrupt Mode
When changing the ACIS1/ACIS0 bits, the Analog Comparator interrupt must be disabled by clearing its interrupt enable bit in the ACSR register. Otherwise an interrupt can
occur when the bits are changed.
Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write
a “1” back into ACI if it is read as set, thus clearing the flag.
67
1041H–11/01
Analog-to-Digital
Converter
Feature list
•
•
•
•
•
•
•
•
•
•
10-bit Resolution
0.5 LSB Integral Non-linearity
±2 LSB Absolute Accuracy
65 - 260 µs Conversion Time
Up to 15 kSPS at Maximum Resolution
8 Multiplexed Input Channels
Rail-to-Rail Input Range
Free Running or Single Conversion Mode
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
The AT90S8535 features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multiplexer that allows each pin of Port A to be used as
an input for the ADC. The ADC contains a Sample and Hold Amplifier that ensures that
the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 45.
The ADC has two separate analog supply voltage pins, AVCC and AGND. AGND must
be connected to GND and the voltage on AVCC must not differ more than ±0.3V from
VCC. See “ADC Noise Canceling Techniques” on page 74 on how to connect these pins.
An external reference voltage must be applied to the AREF pin. This voltage must be in
the range 2V - AVCC.
Figure 45. Analog-to-Digital Converter Block Schematic
ADC CONVERSION
COMPLETE IRQ
15
0
ADC DATA REGISTER
(ADCH/ADCL)
PRESCALER
ADC9..0
ADPS0
ADPS1
ADPS2
ADIF
ADIE
ADFR
ADSC
ADC CTRL & STATUS
REGISTER (ADCSR)
ADEN
MUX0
AREF
MUX1
MUX2
ADC MULTIPLEXER
SELECT (ADMUX)
ADIE
ADIF
8-BIT DATA BUS
ADC7
ADC6
10-BIT DAC
CONVERSION LOGIC
ADC5
ADC4
ADC3
ADC2
8CHANNEL
MUX
+
SAMPLE & HOLD
COMPARATOR
ADC1
ADC0
68
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive
approximation. The minimum value represents AGND and the maximum value represents the voltage on the AREF pin minus one LSB. The analog input channel is selected
by writing to the MUX bits in ADMUX. Any of the eight ADC input pins ADC7..0 can be
selected as single-ended inputs to the ADC.
The ADC can operate in two modes – Single Conversion and Free Running. In Single
Conversion Mode, each conversion will have to be initiated by the user. In Free Running
Mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR
bit in ADCSR selects between the two available modes.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Input channel
selections will not go into effect until ADEN is set. The ADC does not consume power
when ADEN is cleared, so it is recommended to switch off the ADC before entering
power-saving sleep modes.
A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be set to zero by
hardware when the conversion is completed. If a different data channel is selected while
a conversion is in progress, the ADC will finish the current conversion before performing
the channel change.
The ADC generates a 10-bit result, which is presented in the ADC data register, ADCH
and ADCL. When reading data, ADCL must be read first, then ADCH, to ensure that the
content of the data register belongs to the same conversion. Once ADCL is read, ADC
access to data register is blocked. This means that if ADCL has been read and a conversion completes before ADCH is read, neither register is updated and the result from
the conversion is lost. Then ADCH is read, ADC access to the ADCH and ADCL register
is re-enabled.
The ADC has its own interrupt that can be triggered when a conversion completes.
When ADC access to the data registers is prohibited between reading of ADCH and
ADCL, the interrupt will trigger even if the result is lost.
Prescaling
Figure 46. ADC Prescaler
ADEN
Reset
7-BIT ADC PRESCALER
CK/64
CK/128
CK/32
CK/8
CK/16
CK/4
CK/2
CK
ADPS0
ADPS1
ADPS2
ADC CLOCK SOURCE
The successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to achieve maximum resolution. If a resolution of lower than 10 bits is
required, the input clock frequency to the ADC can be higher than 200 kHz to achieve a
69
1041H–11/01
higher sampling rate. See “ADC Characteristics” on page 75 for more details. The ADC
module contains a prescaler, which divides the system clock to an acceptable ADC
clock frequency.
The ADPS2..0 bits in ADCSR are used to generate a proper ADC clock input frequency
from any CPU frequency above 100 kHz. The prescaler starts counting from the
moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler
keeps running for as long as the ADEN bit is set and is continuously reset when ADEN
is low.
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at
the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. In certain situations, the ADC needs
more clock cycles for initialization and to minimize offset errors. Extended conversions
take 25 ADC clock cycles and occur as the first conversion after the ADC is switched on
(ADEN in ADCSR is set).
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal
conversion and 13.5 ADC clock cycles after the start of an extended conversion. When
a conversion is complete, the result is written to the ADC data registers and ADIF is set.
In Single Conversion Mode, ADSC is cleared simultaneously. The software may then
set ADSC again and a new conversion will be initiated on the first rising ADC clock
edge. In Free Running Mode, a new conversion will be started immediately after the
conversion completes, while ADSC remains high. Using Free Running Mode and an
ADC clock frequency of 200 kHz gives the lowest conversion time with a maximum resolution, 65 µs, equivalent to 15 kSPS. For a summary of conversion times, see Table
26.
Figure 47. ADC Timing Diagram, Extended Conversion (Single Conversion Mode)
Next
Conversion
Extended Conversion
Cycle number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
ADC clock
ADEN
ADSC
ADIF
Sign and MSB of result
ADCH
LSB of result
ADCL
MUX and REFS
update
70
Sample & hold
Conversion
complete
MUX and REFS
update
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Figure 48. ADC Timing Diagram, Single Conversion
One Conversion
Cycle number
2
1
3
4
5
6
7
8
Next Conversion
10
9
11
12
13
1
2
3
ADC clock
ADSC
ADIF
ADCH
Sign and MSB of result
ADCL
LSB of result
Sample & hold
Conversion
complete
MUX and REFS
update
MUX and REFS
update
Figure 49. ADC Timing Diagram, Free Running Conversion
One Conversion
Cycle number
11
12
Next Conversion
13
1
3
2
4
ADC clock
ADSC
ADIF
ADCH
Sign and MSB of result
ADCL
LSB of result
Sample & hold
Conversion
complete
MUX and REFS
update
Table 26. ADC Conversion Time
Condition
ADC Noise Canceler
Function
Sample and Hold (Cycles
from Start of Conversion)
Conversion
Time (Cycles)
Conversion
Time (µs)
Extended Conversion
14
25
125 - 500
Normal Conversion
14
26
130 - 520
The ADC features a noise canceler that enables conversion during Idle Mode to reduce
noise induced from the CPU core. To make use of this feature, the following procedure
should be used:
1. Make sure that the ADC is enabled and is not busy converting. Single Conversion Mode must be selected and the ADC conversion complete interrupt must be
enabled.
ADEN = 1
ADSC = 0
ADFR = 0
ADIE = 1
71
1041H–11/01
2. Enter Idle Mode. The ADC will start a conversion once the CPU has been halted.
3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the MCU and execute the ADC Conversion Complete Interrupt
routine.
ADC Multiplexer Select
Register – ADMUX
Bit
7
6
5
4
3
2
1
0
$07 ($27)
–
–
–
–
–
MUX2
MUX1
MUX0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADMUX
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read as zero.
• Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2-0
The value of these three bits selects which analog input ADC7..0 is connected to the
ADC. See Table 27 for details.
If these bits are changed during a conversion, the change will not go into effect until this
conversion is complete (ADIF in ADCSR is set).
Table 27. Input Channel Selections
ADC Control and Status
Register – ADCSR
MUX2.0
Single-ended Input
000
ADC0
001
ADC1
010
ADC2
011
ADC3
100
ADC4
101
ADC5
110
ADC6
111
ADC7
Bit
7
6
5
4
3
2
1
0
ADEN
ADSC
ADFR
ADIF
ADIE
ADPS2
ADPS1
ADPS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
$06 ($26)
ADCSR
• Bit 7 – ADEN: ADC Enable
Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is
turned off. Turning the ADC off while a conversion is in progress will terminate this
conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion Mode, a logical “1” must be written to this bit to start each conversion. In Free Running Mode, a logical “1” must be written to this bit to start the first
conversion. The first time ADSC has been written after the ADC has been enabled or if
ADSC is written at the same time as the ADC is enabled, an extended conversion will
precede the initiated conversion. This extended conversion performs initialization of the
ADC.
72
AT90S/LS8535
1041H–11/01
AT90S/LS8535
ADSC will read as one as long as a conversion is in progress. When the conversion is
complete, it returns to zero. When a extended conversion precedes a real conversion,
ADSC will stay high until the real conversion completes. Writing a “0” to this bit has no
effect.
• Bit 5 – ADFR: ADC Free Running Select
When this bit is set (one), the ADC operates in Free Running Mode. In this mode, the
ADC samples and updates the data registers continuously. Clearing this bit (zero) will
terminate Free Running Mode.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion completes and the data registers are
updated. The ADC Conversion Complete interrupt is executed if the ADIE bit and the Ibit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical “1” to the
flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete interrupt is activated.
• Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input
clock to the ADC.
Table 28. ADC Prescaler Selections
ADC Data Register – ADCL
AND ADCH
ADPS2
ADPS1
ADPS0
Division Factor
0
0
0
2
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Bit
15
14
13
12
11
10
9
8
$05 ($25)
–
–
–
–
–
–
ADC9
ADC8
ADCH
$04 ($24)
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
7
6
5
4
3
2
1
0
Read/Write
Initial Value
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, it is essential that both registers are read and that ADCL is read before ADCH.
73
1041H–11/01
• ADC9..0: ADC Conversion result
These bits represent the result from the conversion. $000 represents analog ground and
$3FF represents the selected reference voltage minus one LSB.
Scanning Multiple
Channels
Since change of analog channel always is delayed until a conversion is finished, the
Free Running Mode can be used to scan multiple channels without interrupting the converter. Typically, the ADC Conversion Complete interrupt will be used to perform the
channel shift. However, the user should take the following fact into consideration: The
interrupt triggers once the result is ready to be read. In Free Running Mode, the next
conversion will start immediately when the interrupt triggers. If ADMUX is changed after
the interrupt triggers, the next conversion has already started and the old setting is
used.
ADC Noise Canceling
Techniques
Digital circuitry inside and outside the AT90S8535 generates EMI that might affect the
accuracy of analog measurements. If conversion accuracy is critical, the noise level can
be reduced by applying the following techniques:
1. The analog part of the AT90S8535 and all analog components in the application
should have a separate analog ground plane on the PCB. This ground plane is
connected to the digital ground plane via a single point on the PCB.
2. Keep analog signal paths as short as possible. Make sure analog tracks run over
the analog ground plane and keep them well away from high-speed switching
digital tracks.
3. The AVCC pin on the AT90S8535 should be connected to the digital VCC supply
voltage via an LC network as shown in Figure 50.
4. Use the ADC noise canceler function to reduce induced noise from the CPU.
5. If some Port A pins are used as digital outputs, it is essential that these do not
switch while a conversion is in progress.
PA3 (ADC3)
41
40
Analog Ground Plane
PA2 (ADC2)
42
39
PA4 (ADC4)
38
PA5 (ADC5)
37
PA6 (ADC6)
36
PA7 (ADC7)
35
AREF
34
33
32
74
10µΗ
PA1 (ADC1)
43
AGND
AVCC
100nF
PA0 (ADC0)
44
AT90S8535
1
VCC
GND
Figure 50. ADC Power Connections
PC0
AT90S/LS8535
1041H–11/01
AT90S/LS8535
ADC Characteristics
TA = -40°C to 85°C
Symbol
Parameter
Condition
Min
Typ
Resolution
Units
10
Bits
Absolute accuracy
VREF = 4V
ADC clock = 200 kHz
1
Absolute accuracy
VREF = 4V
ADC clock = 1 MHz
4
LSB
Absolute accuracy
VREF = 4V
ADC clock = 2 MHz
16
LSB
Integral Non-linearity
VREF > 2V
0.5
LSB
Differential Non-linearity
VREF > 2V
0.5
LSB
1
LSB
Zero Error (Offset)
Conversion Time
65
Clock Frequency
50
AVCC
Analog Supply Voltage
VREF
Reference Voltage
2
RREF
Reference Input Resistance
6
VIN
Max
Input Voltage
RAIN
Analog Input Resistance
Notes: 1. Minimum for AVCC is 2.7V.
2. Maximum for AVCC is 6.0V.
VCC - 0.3
2
LSB
µs
260
200
kHz
(2)
(1)
VCC + 0.3
10
AGND
100
V
AVCC
V
13
kΩ
AREF
V
MΩ
75
1041H–11/01
I/O Ports
All AVR ports have true read-modify-write functionality when used as general digital I/O
ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same
applies for changing drive value (if configured as output) or enabling/disabling of pull-up
resistors (if configured as input).
Port A
Port A is an 8-bit bi-directional I/O port.
Three I/O memory address locations are allocated for Port A, one each for the Data
Register – PORTA, $1B($3B), Data Direction Register – DDRA, $1A($3A) and the Port
A Input Pins – PINA, $19($39). The Port A Input Pins address is read-only, while the
Data Register and the Data Direction Register are read/write.
All port pins have individually selectable pull-up resistors. The Port A output buffers can
sink 20 mA and thus drive LED displays directly. When pins PA0 to PA7 are used as
inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
Port A has an alternate function as analog inputs for the ADC. If some Port A pins are
configured as outputs, it is essential that these do not switch when a conversion is in
progress. This might corrupt the result of the conversion.
During Power-down mode, the Schmitt trigger of the digital input is disconnected. This
allows analog signals that are close to VCC/2 to be present during power-down without
causing excessive power consumption.
Port A Data Register – PORTA
Bit
Port A Data Direction Register
– DDRA
Port A Input Pins Address –
PINA
7
6
5
4
3
2
1
0
$1B ($3B)
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$1A ($3A)
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
$19 ($39)
PORTA
DDRA
PINA
The Port A Input Pins address (PINA) is not a register; this address enables access to
the physical value on each Port A pin. When reading PORTA, the Port A Data Latch is
read and when reading PINA, the logical values present on the pins are read.
76
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Port A as General Digital I/O
All eight pins in Port A have equal functionality when used as digital I/O pins.
PAn, general I/O pin: The DDAn bit in the DDRA register selects the direction of this pin.
If DDAn is set (one), PAn is configured as an output pin. If DDAn is cleared (zero), PAn
is configured as an input pin. If PORTAn is set (one) when the pin is configured as an
input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the
PORTAn has to be cleared (zero) or the pin has to be configured as an output pin.The
port pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Table 29. DDAn Effects on Port A Pins
DDAn
PORTAn
I/O
Pull-up
0
0
Input
No
Tri-state (high-Z)
0
1
Input
Yes
PAn will source current if ext. pulled low
1
0
Output
No
Push-pull Zero Output
1
1
Output
No
Push-pull One Output
Note:
Port A Schematics
Comment
n: 7,6…0, pin number.
Note that all port pins are synchronized. The synchronization latch is, however, not
shown in the figure.
Figure 51. Port A Schematic Diagrams (Pins PA0 - PA7)
RD
MOS
PULLUP
RESET
Q
D
DDAn
WD
RESET
Q
D
PORTAn
C
PAn
RL
PWRDN
WP
RP
TO ADC MUX
WP:
WD:
RL:
RP:
RD:
n:
DATA BUS
C
ADCn
WRITE PORTA
WRITE DDRA
READ PORTA LATCH
READ PORTA PIN
READ DDRA
0-7
77
1041H–11/01
Port B
Port B is an 8-bit bi-directional I/O port.
Three I/O memory address locations are allocated for the Port B, one each for the Data
Register – PORTB, $18($38), Data Direction Register – DDRB, $17($37) and the Port B
Input Pins – PINB, $16($36). The Port B Input Pins address is read-only, while the Data
Register and the Data Direction Register are read/write.
All port pins have individually selectable pull-up resistors. The Port B output buffers can
sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7 are used as
inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
The Port B pins with alternate functions are shown in Table 30.
Table 30. Port B Pin Alternate Functions
Port Pin
Alternate Functions
PB0
T0 (Timer/Counter0 External Counter Input)
PB1
T1 (Timer/Counter1 External Counter Input)
PB2
AIN0 (Analog Comparator Positive Input)
PB3
AIN1 (Analog Comparator Negative Input)
PB4
SS (SPI Slave Select Input)
PB5
MOSI (SPI Bus Master Output/Slave Input)
PB6
MISO (SPI Bus Master Input/Slave Output)
PB7
SCK (SPI Bus Serial Clock)
When the pins are used for the alternate function, the DDRB and PORTB registers have
to be set according to the alternate function description.
Port B Data Register – PORTB
Bit
7
6
5
4
3
2
1
0
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
$18 ($38)
Port B Data Direction Register
– DDRB
Bit
7
6
5
4
3
2
1
0
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
$17 ($37)
Port B Input Pins Address –
PINB
Bit
7
6
5
4
3
2
1
0
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
$16 ($36)
PORTB
DDRB
PINB
The Port B Input Pins address (PINB) is not a register and this address enables access
to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch
is read and when reading PINB, the logical values present on the pins are read.
78
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Port B As General Digital I/O
All eight pins in Port B have equal functionality when used as digital I/O pins.
PBn, general I/O pin: The DDBn bit in the DDRB register selects the direction of this pin.
If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn
is configured as an input pin. If PORTBn is set (one) when the pin is configured as an
input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the
PORTBn has to be cleared (zero) or the pin has to be configured as an output pin. The
port pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Table 31. DDBn Effects on Port B Pins
DDBn
PORTBn
I/O
Pull-up
0
0
Input
No
Tri-state (high-Z)
0
1
Input
Yes
PBn will source current if ext. pulled low
1
0
Output
No
Push-pull Zero Output
1
1
Output
No
Push-pull One Output
Note:
Alternate Functions of Port B
Comment
n: 7,6…0, pin number.
The alternate pin configuration is as follows:
• SCK – Port B, Bit 7
SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB7.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB7 bit. See the description of the SPI port for further details.
• MISO – Port B, Bit 6
MISO: Master data input, slave data output pin for SPI channel. When the SPI is
enabled as a master, this pin is configured as an input regardless of the setting of
DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by
DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB6 bit. See the description of the SPI port for further details.
• MOSI – Port B, Bit 5
MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB5.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB5 bit. See the description of the SPI port for further details.
• SS – Port B, Bit 4
SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as
an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin
is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled
by the PORTB4 bit. See the description of the SPI port for further details.
• AIN1 – Port B, Bit 3
AIN1, Analog Comparator Negative Input. When configured as an input (DDB3 is
cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared
[zero]), this pin also serves as the negative input of the on-chip Analog Comparator.
During Power-down mode, the Schmitt trigger of the digital input is disconnected. This
79
1041H–11/01
allows analog signals that are close to VCC/2 to be present during power-down without
causing excessive power consumption.
• AIN0 – Port B, Bit 2
AIN0, Analog Comparator Positive Input. When configured as an input (DDB2 is cleared
[zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]),
this pin also serves as the positive input of the on-chip Analog Comparator. During
Power-down mode, the Schmitt trigger of the digital input is disconnected. This allows
analog signals that are close to VCC/2 to be present during power-down without causing
excessive power consumption.
• T1 – Port B, Bit 1
T1, Timer/Counter1 counter source. See the timer description for further details.
• T0 – Port B, Bit 0
T0: Timer/Counter0 counter source. See the timer description for further details.
Port B Schematics
Note that all port pins are synchronized. The synchronization latches are, however, not
shown in the figures.
Figure 52. Port B Schematic Diagram (Pins PB0 and PB1)
2
80
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1041H–11/01
AT90S/LS8535
Figure 53. Port B Schematic Diagram (Pins PB2 and PB3)
RD
MOS
PULLUP
RESET
Q
D
DDBn
WD
RESET
Q
D
PORTBn
C
PBn
RL
PWRDN
WP
RP
TO COMPARATOR
WP:
WD:
RL:
RP:
RD:
n:
m:
DATA BUS
C
AINm
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
2, 3
0, 1
Figure 54. Port B Schematic Diagram (Pin PB4)
RD
MOS
PULLUP
RESET
Q
D
DDB4
WD
RESET
Q
D
PORTB4
C
PB4
RL
DATA BUS
C
WP
RP
WP:
WD:
RL:
RP:
RD:
MSTR:
SPE:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI MASTER ENABLE
SPI ENABLE
MSTR
SPE
SPI SS
81
1041H–11/01
Figure 55. Port B Schematic Diagram (Pin PB5)
RD
MOS
PULLUP
RESET
Q
R
D
DDB5
WD
RESET
R
Q
D
PORTB5
PB5
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
MSTR
SPE
SPI MASTER
OUT
SPI SLAVE
IN
Figure 56. Port B Schematic Diagram (Pin PB6)
RD
MOS
PULLUP
RESET
Q
R
D
DDB6
WD
RESET
R
Q
D
PORTB6
PB6
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
MSTR
SPE
SPI SLAVE
OUT
SPI MASTER
IN
82
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AT90S/LS8535
Figure 57. Port B Schematic Diagram (Pin PB7)
RD
MOS
PULLUP
RESET
Q
R
D
DDB7
WD
RESET
R
Q
D
PORTB7
PB7
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
MSTR
SPE
SPI CLOCK
OUT
SPI CLOCK
IN
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Port C
Port C is an 8-bit bi-directional I/O port.
Three I/O memory address locations are allocated for the Port C, one each for the Data
Register – PORTC, $15($35), Data Direction Register – DDRC, $14($34) and the Port C
Input Pins – PINC, $13($33). The Port C Input Pins address is read-only, while the Data
Register and the Data Direction Register are read/write.
All port pins have individually selectable pull-up resistors. The Port C output buffers can
sink 20 mA and thus drive LED displays directly. When pins PC0 to PC7 are used as
inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
Port C Data Register – PORTC
Bit
7
6
5
4
3
2
1
0
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
$15 ($35)
Port C Data Direction Register
– DDRC
Bit
7
6
5
4
3
2
1
0
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
$14 ($34)
Port C Input Pins Address –
PINC
Bit
7
6
5
4
3
2
1
0
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
$13 ($33)
PORTC
DDRC
PINC
The Port C Input Pins address (PINC) is not a register; this address enables access to
the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is
read and when reading PINC, the logical values present on the pins are read.
Port C As General Digital I/O
All eight pins in Port C have equal functionality when used as digital I/O pins.
PCn, general I/O pin: The DDCn bit in the DDRC register selects the direction of this pin.
If DDCn is set (one), PCn is configured as an output pin. If DDCn is cleared (zero), PCn
is configured as an input pin. If PORTCn is set (one) when the pin is configured as an
input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off,
PORTCn has to be cleared (zero) or the pin has to be configured as an output pin.The
port pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
Table 32. DDCn Effects on Port C Pins
DDCn
PORTCn
I/O
Pull-up
0
0
Input
No
Tri-state (high-Z)
0
1
Input
Yes
PCn will source current if ext. pulled low
1
0
Output
No
Push-pull Zero Output
1
Output
No
Push-pull One Output
1
Note:
84
Comment
n: 7…0, pin number
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Alternate Functions of Port C
When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of
Timer/Counter2, pins PC6 and PC7 are disconnected from the port. In this mode, a
crystal oscillator is connected to the pins and the pins cannot be used as I/O pins.
Port C Schematics
Note that all port pins are synchronized. The synchronization latch is, however, not
shown in the figure.
Figure 58. Port C Schematic Diagram (Pins PC0 - PC5)
RD
MOS
PULLUP
RESET
R
Q
D
DDCn
C
DATA BUS
WD
RESET
R
Q
D
PORTCn
PCn
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
n:
WRITE PORTC
WRITE DDRC
READ PORTC LATCH
READ PORTC PIN
READ DDRC
0-5
Figure 59. Port C Schematic Diagram (Pins PC6)
RD
MOS
PULLUP
RESET
Q
R
D
DDC6
WD
RESET
R
Q
D
PORTC6
PC6
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
AS2:
WRITE PORTC
WRITE DDRC
READ PORTC LATCH
READ PORTC PIN
READ DDRC
ASYNCH SELECT T/C2
AS2
T/C2 OSC
AMP INPUT
85
1041H–11/01
Figure 60. Port C Schematic Diagram (Pins PC7)
Port D
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors.
Three I/O memory address locations are allocated for Port D, one each for the Data
Register – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D
Input Pins – PIND, $10($30). The Port D Input Pins address is read-only, while the Data
Register and the Data Direction Register are read/write.
The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally
pulled low will source current if the pull-up resistors are activated. Some Port D pins
have alternate functions as shown in Table 33.
Table 33. Port D Pin Alternate Functions
Port Pin
86
Alternate Function
PD0
RXD (UART Input line)
PD1
TXD (UART Output line)
PD2
INT0 (External interrupt 0 input)
PD3
INT1 (External interrupt 1 input)
PD4
OC1B (Timer/Counter1 output compareB match output)
PD5
OC1A (Timer/Counter1 output compareA match output)
PD6
ICP (Timer/Counter1 input capture pin)
PD7
OC2 (Timer/Counter2 output compare match output)
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Port D Data Register – PORTD
Bit
7
6
5
4
3
2
1
0
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
$12 ($32)
Port D Data Direction Register
– DDRD
Bit
7
6
5
4
3
2
1
0
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
$11 ($31)
Port D Input Pins Address –
PIND
Bit
7
6
5
4
3
2
1
0
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
$10 ($30)
PORTD
DDRD
PIND
The Port D Input Pins address (PIND) is not a register; this address enables access to
the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is
read and when reading PIND, the logical values present on the pins are read.
Port D As General Digital I/O
PDn, general I/O pin: The DDDn bit in the DDRD register selects the direction of this pin.
If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn
is configured as an input pin. If PDn is set (one) when configured as an input pin, the
MOS pull-up resistor is activated. To switch the pull-up resistor off, the PDn has to be
cleared (zero) or the pin has to be configured as an output pin.The port pins are tristated when a reset condition becomes active, even if the clock is not running.
Table 34. DDDn Bits on Port D Pins
DDDn
PORTDn
I/O
Pull-up
0
0
Input
No
Tri-state (high-Z)
0
1
Input
Yes
PDn will source current if ext. pulled low
1
0
Output
No
Push-pull Zero Output
1
1
Output
No
Push-pull One Output
Note:
Alternate Functions of Port D
Comment
n: 7,6…0, pin number.
• OC2 – Port D, Bit 7
OC2, Timer/Counter2 output compare match output: The PD7 pin can serve as an
external output for the Timer/Counter2 output compare. The pin has to be configured as
an output (DDD7 set [one]) to serve this function. See the timer description on how to
enable this function. The OC2 pin is also the output pin for the PWM mode timer
function.
• ICP – Port D, Bit 6
ICP – Input Capture Pin: The PD6 pin can act as an input capture pin for
Timer/Counter1. The pin has to be configured as an input (DDD6 cleared [zero]) to
serve this function. See the timer description on how to enable this function.
87
1041H–11/01
• OC1A – Port D, Bit 5
OC1A, Output compare matchA output: The PD5 pin can serve as an external output for
the Timer/Counter1 output compareA. The pin has to be configured as an output (DDD5
set [one]) to serve this function. See the timer description on how to enable this function.
The OC1A pin is also the output pin for the PWM mode timer function.
• OC1B – Port D, Bit 4
OC1B, Output compare matchB output: The PD4 pin can serve as an external output for
the Timer/Counter1 output compareB. The pin has to be configured as an output (DDD4
set [one]) to serve this function. See the timer description on how to enable this function.
The OC1B pin is also the output pin for the PWM mode timer function.
• INT1 – Port D, Bit 3
INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source
to the MCU. See the interrupt description for further details and how to enable the
source.
• INT0 – Port D, Bit 2
INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source
to the MCU. See the interrupt description for further details and how to enable the
source.
• TXD – Port D, Bit 1
Transmit Data (data output pin for the UART). When the UART Transmitter is enabled,
this pin is configured as an output, regardless of the value of DDD1.
• RXD – Port D, Bit 0
Receive Data (data input pin for the UART). When the UART Receiver is enabled, this
pin is configured as an input, regardless of the value of DDD0. When the UART forces
this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.
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Port D Schematics
Note that all port pins are synchronized. The synchronization latches are, however, not
shown in the figures.
Figure 61. Port D Schematic Diagram (Pin PD0)
RD
MOS
PULLUP
RESET
Q
D
DDD0
C
DATA BUS
WD
RESET
Q
D
PORTD0
C
PD0
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
RXD:
RXEN:
RXEN
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART RECEIVE DATA
UART RECEIVE ENABLE
RXD
Figure 62. Port D Schematic Diagram (Pin PD1)
RD
MOS
PULLUP
RESET
Q
R
D
DDD1
C
DATA BUS
WD
RESET
R
Q
D
PORTD1
PD1
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
TXD:
TXEN:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART TRANSMIT DATA
UART TRANSMIT ENABLE
TXEN
TXD
89
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Figure 63. Port D Schematic Diagram (Pins PD2 and PD3)
Figure 64. Port D Schematic Diagram (Pins PD4 and PD5)
90
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Figure 65. Port D Schematic Diagram (Pin PD6)
RD
MOS
PULLUP
RESET
Q
R
D
DDD6
WD
RESET
R
Q
D
PORTD6
PD6
DATA BUS
C
C
RL
WP
RP
WP:
WD:
RL:
RP:
RD:
ACIC:
ACO:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
COMPARATOR IC ENABLE
COMPARATOR OUTPUT
0
NOISE CANCELER
EDGE SELECT
ICNC1
ICES1
ICF1
1
ACIC
ACO
Figure 66. Port D Schematic Diagram (Pin PD7)
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1041H–11/01
Memory
Programming
Program and Data
Memory Lock Bits
The AT90S8535 MCU provides two Lock bits that can be left unprogrammed (“1”) or can
be programmed (“0”) to obtain the additional features listed in Table 35. The Lock bits
can only be erased with the Chip Erase command.
Table 35. Lock Bit Protection Modes
Memory Lock Bits
Mode
LB1
LB2
1
1
1
No memory lock features enabled.
2
0
1
Further programming of the Flash and EEPROM is disabled.(1)
3
0
0
Same as mode 2 and verify is also disabled.
Note:
Fuse Bits
Protection Type
1. In Parallel Mode, further programming of the Fuse bits is also disabled. Program the
Fuse bits before programming the Lock bits.
The AT90S8535 has two Fuse bits, SPIEN and FSTRT.
•
When the SPIEN Fuse is programmed (“0”), Serial Program and Data Downloading
is enabled. Default value is programmed (“0”). The SPIEN Fuse is not accessible in
Serial Programming Mode.
•
When the FSTRT Fuse is programmed (“0”), the short start-up time is selected.
Default value is unprogrammed (“1”).
The status of the Fuse bits is not affected by Chip Erase.
Signature Bytes
All Atmel microcontrollers have a three-byte signature code that identifies the device.
This code can be read in both Serial and Parallel modes. The three bytes reside in a
separate address space.
1. $000: $1E (indicates manufactured by Atmel)
2. $001: $93 (indicates 8K bytes Flash memory)
3. $002: $03 (indicates AT90S8535 device when signature byte $001 is $93)
Note:
Programming the Flash
and EEPROM
1. When both Lock bits are programmed (lock mode 3), the signature bytes cannot be
read in Serial Mode. Reading the signature bytes will return: $00, $01 and $02.
Atmel’s AT90S8535 offers 8K bytes of in-system reprogrammable Flash program memory and 512 bytes of EEPROM data memory.
The AT90S8535 is shipped with the On-chip Flash program and EEPROM data memory
arrays in the erased state (i.e., contents = $FF) and ready to be programmed. This
device supports a high-voltage (12V) Parallel Programming Mode and a low-voltage
Serial Programming Mode. The +12V is used for programming enable only and no current of significance is drawn by this pin. The Serial Programming Mode provides a
convenient way to download program and data into the AT90S8535 inside the user’s
system.
The program and data memory arrays on the AT90S8535 are programmed byte-by-byte
in either programming mode. For the EEPROM, an auto-erase cycle is provided within
the self-timed write instruction in the Serial Programming Mode.
During programming, the supply voltage must be in accordance with Table 36.
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Table 36. Supply Voltage during Programming
Part
Serial Programming
Parallel Programming
AT90S8535
4.0 - 6.0V
4.5 - 5.5V
AT90LS8535
2.7 - 6.0V
4.5 - 5.5V
Parallel Programming
This section describes how to parallel program and verify Flash program memory,
EEPROM data memory, Lock bits and Fuse bits in the AT90S8535.
Signal Names
In this section, some pins of the AT90S8535 are referenced by signal names describing
their function during parallel programming. See Figure 67 and Table 37. Pins not
described in Table 37 are referenced by pin name.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding are shown in Table 38.
When pulsing WR or OE, the command loaded determines the action executed. The
command is a byte where the different bits are assigned functions as shown in Table 39.
Figure 67. Parallel Programming
AT90S8535
+5V
RDY/BSY
PD1
VCC
OE
PD2
PB7 - PB0
WR
PD3
BS
PD4
XA0
PD5
XA1
PD6
+12 V
DATA
RESET
XTAL1
GND
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Table 37. Pin Name Mapping
Signal Name in
Programming Mode
Pin Name
I/O
Function
RDY/BSY
PD1
O
0: Device is busy programming, 1: Device is ready
for new command
OE
PD2
I
Output Enable (Active low)
WR
PD3
I
Write Pulse (Active low)
BS
PD4
I
Byte Select (“0” selects low byte, “1” selects high
byte)
XA0
PD5
I
XTAL Action Bit 0
XA1
PD6
I
XTAL Action Bit 1
DATA
PB7 - 0
I/O
Bi-directional Data Bus (Output when OE is low)
Table 38. XA1 and XA0 Coding
XA1
XA0
Action when XTAL1 is Pulsed
0
0
Load Flash or EEPROM Address (high or low address byte determined by BS)
0
1
Load Data (High or low data byte for Flash determined by BS)
1
0
Load Command
1
1
No Action, Idle
Table 39. Command Byte Bit Coding
Command Byte
Enter Programming Mode
Command Executed
1000 0000
Chip Erase
0100 0000
Write Fuse Bits
0010 0000
Write Lock Bits
0001 0000
Write Flash
0001 0001
Write EEPROM
0000 1000
Read Signature Bytes
0000 0100
Read Lock and Fuse Bits
0000 0010
Read Flash
0000 0011
Read EEPROM
The following algorithm puts the device in Parallel Programming Mode:
1. Apply supply voltage according to Table 36, between VCC and GND.
2. Set the RESET and BS pin to “0” and wait at least 100 ns.
3. Apply 11.5 - 12.5V to RESET. Any activity on BS within 100 ns after +12V has
been applied to RESET, will cause the device to fail entering programming mode.
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AT90S/LS8535
Chip Erase
The Chip Erase command will erase the Flash and EEPROM memories and the Lock
bits. The Lock bits are not reset until the Flash and EEPROM have been completely
erased. The Fuse bits are not changed. Chip Erase must be performed before the Flash
or EEPROM is reprogrammed.
Load Command “Chip Erase”:
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS to “0”.
3. Set DATA to “1000 0000”. This is the command for Chip Erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR a tWLWH_CE-wide negative pulse to execute Chip Erase. See Table 40
for tWLWH_CE value. Chip Erase does not generate any activity on the RDY/BSY
pin.
Programming the Flash
A: Load Command “Write Flash”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS to “0”.
3. Set DATA to “0001 0000”. This is the command for Write Flash.
4. Give XTAL1 a positive pulse. This loads the command.
B: Load Address High Byte
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS to “1”. This selects high byte.
3. Set DATA = Address high byte ($00 - $0F).
4. Give XTAL1 a positive pulse. This loads the address high byte.
C: Load Address Low Byte
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS to “0”. This selects low byte.
3. Set DATA = Address low byte ($00 - $FF).
4. Give XTAL1 a positive pulse. This loads the address low byte.
D: Load Data Low Byte
1. Set XA1, XA0 to “01”. This enables data loading.
2. Set DATA = Data low byte ($00 - $FF).
3. Give XTAL1 a positive pulse. This loads the data low byte.
E: Write Data Low Byte
1. Set BS to “0”. This selects low data.
2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY
goes low.
3. Wait until RDY/BSY goes high to program the next byte.
(See Figure 68 for signal waveforms.)
F: Load Data High Byte
1. Set XA1, XA0 to “01”. This enables data loading.
2. Set DATA = Data high byte ($00 - $FF).
3. Give XTAL1 a positive pulse. This loads the data high byte.
G: Write Data High Byte
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1041H–11/01
1. Set BS to “1”. This selects high data.
2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY
goes low.
3. Wait until RDY/BSY goes high to program the next byte.
(See Figure 69 for signal waveforms.)
The loaded command and address are retained in the device during programming. For
efficient programming, the following should be considered:
• The command needs only be loaded once when writing or reading multiple memory
locations.
• Address high byte needs only be loaded before programming a new 256-word page
in the Flash.
• Skip writing the data value $FF, that is, the contents of the entire Flash and EEPROM
after a Chip Erase.
These considerations also apply to EEPROM programming and Flash, EEPROM and
signature byte reading.
Figure 68. Programming the Flash Waveforms
DATA
$10
ADDR. HIGH
ADDR. LOW
DATA LOW
XA1
XA0
BS
XTAL1
WR
RDY/BSY
RESET
12V
OE
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AT90S/LS8535
Figure 69. Programming the Flash Waveforms (Continued)
DATA
DATA HIGH
XA1
XA0
BS
XTAL1
WR
RDY/BSY
RESET
+12V
OE
Reading the Flash
The algorithm for reading the Flash memory is as follows (refer to “Programming the
Flash” for details on command and address loading):
1. A: Load Command “0000 0010”.
2. B: Load Address High Byte ($00 - $0F).
3. C: Load Address Low Byte ($00 - $FF).
4. Set OE to “0” and BS to “0”. The Flash word low byte can now be read at DATA.
5. Set BS to “1”. The Flash word high byte can now be read from DATA.
6. Set OE to “1”.
Programming the EEPROM
The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” for details on command, address and data loading):
1. A: Load Command “0001 0001”.
2. B: Load Address High Byte ($00 - $01).
3. C: Load Address Low Byte ($00 - $FF).
4. D: Load Data Low Byte ($00 - $FF).
5. E: Write Data Low Byte.
Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to “Programming the
Flash” for details on command and address loading):
1. A: Load Command “0000 0011”.
2. B: Load Address High Byte ($00 - $01).
3. C: Load Address Low Byte ($00 - $FF).
4. Set OE to “0” and BS to “0”. The EEPROM data byte can now be read at DATA.
5. Set OE to “1”.
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Programming the Fuse Bits
The algorithm for programming the Fuse bits is as follows (refer to “Programming the
Flash” for details on command and data loading):
1. A: Load Command “0100 0000”.
2. D: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
Bit 5 = SPIEN Fuse bit.
Bit 0 = FSTRT Fuse bit.
Bit 7-6,4-1 = “1”. These bits are reserved and should be left unprogrammed (“1”).
3. Give WR a tWLWH_PFB-wide negative pulse to execute the programming, tWLWH_PFB
is found in Table 40. Programming the Fuse bits does not generate any activity
on the RDY/BSY pin.
Programming the Lock Bits
The algorithm for programming the Lock bits is as follows (refer to “Programming the
Flash” on page 95 for details on command and data loading):
1. A: Load Command “0010 0000”.
2. D: Load Data Low Byte. Bit n = “0” programs the Lock bit.
Bit 2 = Lock Bit2
Bit 1 = Lock Bit1
Bit 7-3,0 = “1”. These bits are reserved and should be left unprogrammed (“1”).
3. E: Write Data Low Byte.
The Lock bits can only be cleared by executing Chip Erase.
Reading the Fuse and Lock
Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming
the Flash” on page 95 for details on command loading):
1. A: Load Command “0000 0100”.
2. Set OE to “0” and BS to “1”. The status of the Fuse and Lock bits can now be
read at DATA (“0” means programmed).
Bit 7 = Lock Bit1
Bit 6 = Lock Bit2
Bit 5 = SPIEN Fuse bit
Bit 0 = FSTRT Fuse bit
3. Set OE to “1”.
Observe that BS needs to be set to “1”.
Reading the Signature Bytes
The algorithm for reading the signature bytes is as follows (refer to “Programming the
Flash” on page 95 for details on command and address loading):
1. A: Load Command “0000 1000”.
2. C: Load Address Low Byte ($00 - $02).
Set OE to “0” and BS to “0”. The selected signature byte can now be read at DATA.
3. Set OE to “1”.
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Parallel Programming
Characteristics
Figure 70. Parallel Programming Timing
tXLWL
tXHXL
XTAL1
tDVXH
tXLDX tBVWL
tWLWH
WR
tRHBX
tWHRL
Write
Data & Contol
(DATA, XA0/1, BS)
RDY/BSY
tXLOL
tOHDZ
tOLDV
DATA
Read
tWLRH
OE
Table 40. Parallel Programming Characteristics, TA = 25°C ± 10%, VCC = 5V ± 10%
Symbol
Parameter
Min
Typ
Max
Units
VPP
Programming Enable Voltage
11.5
12.5
V
IPP
Programming Enable Current
250.0
µA
tDVXH
Data and Control Setup before XTAL1 High
67.0
ns
tXHXL
XTAL1 Pulse Width High
67.0
ns
tXLDX
Data and Control Hold after XTAL1 Low
67.0
ns
tXLWL
XTAL1 Low to WR Low
67.0
ns
tBVWL
BS Valid to WR Low
67.0
ns
tRHBX
BS Hold after RDY/BSY High
67.0
ns
tWLWH
WR Pulse Width Low(1)
67.0
ns
tWHRL
WR High to RDY/BSY Low(2)
tWLRH
WR Low to RDY/BSY High
(2)
tXLOL
XTAL1 Low to OE Low
tOLDV
OE Low to DATA Valid
tOHDZ
OE High to DATA Tri-stated
tWLWH_CE
WR Pulse Width Low for Chip Erase
20.0
0.5
0.7
ns
0.9
67.0
ns
20.0
5.0
10.0
ns
20.0
ns
15.0
ms
WR Pulse Width Low for Programming the
tWLWH_PFB
Fuse Bits
1.0
1.5
1.8
Notes: 1. Use tWLWH_CE for Chip Erase and tWLWH_PFB for programming the Fuse bits.
2. If tWLWH is held longer than tWLRH, no RDY/BSY pulse will be seen.
Serial Downloading
ms
ms
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output), see Figure 71. After RESET is set low, the Programming
Enable instruction needs to be executed first before program/erase operations can be
executed.
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1041H–11/01
Figure 71. Serial Programming and Verify
2.7 - 6.0V
AT90S8535
GND
RESET
VCC
PB7
PB6
PB5
CLOCK INPUT
SCK
MISO
MOSI
XTAL1
GND
For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction
and there is no need to first execute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the program and EEPROM
arrays into $FF.
The program and EEPROM memory arrays have separate address spaces: $0000 to
$0FFF for program memory and $0000 to $01FF for EEPROM memory.
Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected
across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock
(SCK) input are defined as follows:
Low: > 2 XTAL1 clock cycles
High: > 2 XTAL1 clock cycles
Serial Programming
Algorithm
When writing serial data to the AT90S8535, data is clocked on the rising edge of SCK.
When reading data from the AT90S8535, data is clocked on the falling edge of SCK.
See Figure 72, Figure 73 and Table 43 for timing details.
To program and verify the AT90SS8535 in the Serial Programming Mode, the following
sequence is recommended (see 4-byte instruction formats in Table 42):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. If a crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the
XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held
low during power-up. In this case, RESET must be given a positive pulse of at least
two XTAL1 cycles duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to the MOSI (PB5) pin.
3. The serial programming instructions will not work if the communication is out of
synchronization. When in sync, the second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is
correct or not, all four bytes of the instruction must be transmitted. If the $53 did
not echo back, give SCK a positive pulse and issue a new Programming Enable
instruction. If the $53 is not seen within 32 attempts, there is no functional device
connected.
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AT90S/LS8535
4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE
after the instruction, give RESET a positive pulse and start over from step 2. See
Table 44 for tWD_ERASE value.
5. The Flash or EEPROM array is programmed one byte at a time by supplying the
address and data together with the appropriate Write instruction. An EEPROM
memory location is first automatically erased before new data is written. Use
Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait tWD_PROG before transmitting the next instruction.
See Table 45 for tWD_PROG value. In an erased device, no $FFs in the data file(s)
needs to be programmed.
6. Any memory location can be verified by using the Read instruction that returns
the content at the selected address at the serial output MISO (PB6) pin.
7. At the end of the programming session, RESET can be set high to commence
normal operation.
8. Power-off sequence (if needed):
Set XTAL1 to “0” (if a crystal is not used).
Set RESET to “1”.
Turn VCC power off.
Data Polling EEPROM
When a byte is being programmed into the EEPROM, reading the address location
being programmed will give the value P1 until the auto-erase is finished and then the
value P2. See Table 41 for P1 and P2 values.
At the time the device is ready for a new EEPROM byte, the programmed value will read
correctly. This is used to determine when the next byte can be written. This will not work
for the values P1 and P2, so when programming these values, the user will have to wait
for at least the prescribed time tWD_PROG before programming the next byte. See Table
45 for tWD_PROG value. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. This does not apply if
the EEPROM is reprogrammed without first chip-erasing the device.
Table 41. Read Back Value during EEPROM Polling
Data Polling Flash
Part
P1
P2
AT90S/LS8535
$00
$FF
When a byte is being programmed into the Flash, reading the address location being
programmed will give the value $FF. At the time the device is ready for a new byte, the
programmed value will read correctly. This is used to determine when the next byte can
be written. This will not work for the value $FF, so when programming this value, the
user will have to wait for at least tWD_PROG before programming the next byte. As a chiperased device contains $FF in all locations, programming of addresses that are meant
to contain $FF can be skipped.
Figure 72. Serial Programming Waveforms
SERIAL DATA INPUT
PB5(MOSI)
MSB
LSB
SERIAL DATA OUTPUT
PB6(MISO)
MSB
LSB
SERIAL CLOCK INPUT
PB7(SCK)
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1041H–11/01
f
Table 42. Serial Programming Instruction Set
Instruction Format
Instruction
Programming Enable
Chip Erase
Byte 1
Byte 2
Byte 3
Byte4
1010 1100
0101 0011
xxxx xxxx
xxxx xxxx
Enable serial programming
while RESET is low.
1010 1100
100x xxxx
xxxx xxxx
xxxx xxxx
Chip Erase Flash and
EEPROM memory arrays.
0010 H000
xxxx aaaa
bbbb bbbb
oooo oooo
Read H (high or low) data o
from program memory at word
address a:b.
0100 H000
xxxx aaaa
bbbb bbbb
iiii iiii
Write H (high or low) data i to
program memory at word
address a:b.
1010 0000
xxxx xxxa
bbbb bbbb
oooo oooo
Read data o from EEPROM
memory at address a:b.
1100 0000
xxxx xxxa
bbbb bbbb
iiii iiii
Write data i to EEPROM
memory at address a:b.
0101 1000
xxxx xxxx
xxxx xxxx
12Sx xxxF
Read Lock and Fuse bits.
“0” = programmed
“1” = unprogrammed
1010 1100
1111 1211
xxxx xxxx
xxxx xxxx
Write Lock bits. Set bits 1,2 =
“0” to program Lock bits.
0011 0000
xxxx xxxx
xxxx xxbb
oooo oooo
Read signature byte o at
address b.(2)
1010 1100
1011 111F
xxxx xxxx
xxxx xxxx
Write FSTRT fuse. Set bit
F = “0” to program,
“1” to unprogram.
Read Program Memory
Write Program Memory
Read EEPROM Memory
Write EEPROM Memory
Read Lock and Fuse Bits
Write Lock Bits
Read Signature Byte
Write FSTRT Fuse
Notes:
102
Operation
1. a = address high bits
b = address low bits
H = 0 – Low byte, 1 – High Byte
o = data out
i = data in
x = don’t care
1 = Lock Bit 1
2 = Lock Bit 2
F = FSTRT Fuse
S = SPIEN Fuse
2. The signature bytes are not readable in lock mode 3, i.e., both Lock bits programmed.
AT90S/LS8535
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AT90S/LS8535
Serial Programming
Characteristics
Figure 73. Serial Programming Timing
MOSI
tOVSH
SCK
tSHOX
tSLSH
tSHSL
MISO
tSLIV
Table 43. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7 - 6.0V
(unless otherwise noted)
Symbol
1/tCLCL
tCLCL
1/tCLCL
Parameter
Min
Oscillator Frequency (VCC = 2.7 - 6.0V)
Oscillator Period (VCC = 2.7 - 4.0V)
Oscillator Period (VCC = 4.0 - 6.0V)
tSHSL
0
Max
Units
4.0
MHz
250.0
Oscillator Frequency (VCC = 4.0 - 6.0V)
tCLCL
Typ
ns
0
8.0
MHz
125.0
ns
SCK Pulse Width High
2.0 tCLCL
ns
tSLSH
SCK Pulse Width Low
2.0 tCLCL
ns
tOVSH
MOSI Setup to SCK High
tCLCL
ns
tSHOX
MOSI Hold after SCK High
2.0 tCLCL
ns
tSLIV
SCK Low to MISO Valid
10.0
16.0
32.0
ns
Table 44. Minimum Wait Delay after the Chip Erase instruction
Symbol
3.2V
3.6V
4.0V
5.0V
tWD_ERASE
18 ms
14 ms
12 ms
8 ms
Table 45. Minimum Wait Delay after Writing a Flash or EEPROM Location
Symbol
3.2V
3.6V
4.0V
5.0V
tWD_PROG
9 ms
7 ms
6 ms
4 ms
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Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature ................................ -40°C to +105°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature .................................... -65°C to +150°C
Voltage on Any Pin except RESET
with Respect to Ground .............................-1.0V to VCC + 0.5V
Voltage on RESET with Respect to Ground ....-1.0V to +13.0V
Maximum Operating Voltage ............................................ 6.6V
I/O Pin Maximum Current ........................................... 40.0 mA
Maximum Current VCC
and GND (PDIP package) ....................................... 200.0 mA
Maximum Current VCC
and GND (TQFP, PLCC package) ............................ 400.0 mA
DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol
VIL
VIL1
VIH
VIH1
VIH2
Parameter
Condition
Input Low Voltage
Input Low Voltage
XTAL
Input High Voltage
Except (XTAL, RESET)
Input High Voltage
XTAL
Input High Voltage
RESET
(3)
Typ
Max
Units
-0.5
0.3VCC(1)
V
-0.5
(1)
V
0.6 VCC
(2)
VCC + 0.5
V
0.8 VCC
(2)
VCC + 0.5
V
0.9 VCC
(2)
VCC + 0.5
V
0.6
0.5
V
V
0.2 VCC
VOL
Output Low Voltage
(Ports A, B, C, D)
IOL = 20 mA, VCC = 5V
IOL = 10 mA, VCC = 3V
VOH
Output High Voltage(4)
(Ports A, B, C, D)
IOH = -3 mA, VCC = 5V
IOH = -1.5 mA, VCC = 3V
IIL
Input Leakage
Current I/O Pin
VCC = 6V, Vin = 0.45V
(absolute value)
8.0
µA
IIH
Input Leakage
Current I/O Pin
VCC = 6V, Vin = 6.0V
(absolute value)
8.0
µA
RRST
RI/O
ICC
104
Min
4.2
2.3
V
V
Reset Pull-up
100.0
500.0
kΩ
I/O Pin Pull-up Resistor
35.0
120.0
kΩ
Active 4 MHz, VCC = 3V
5.0
mA
Idle 4 MHz, VCC = 3V
3.0
mA
Power-down, VCC = 3V
WDT enabled(5)
15.0
µA
Power-down, VCC = 3V
WDT disabled(5)
5.0
µA
Power Save, VCC = 3V
WDT disabled(5)
15.0
µA
Power Supply Current
AT90S/LS8535
1041H–11/01
AT90S/LS8535
DC Characteristics (Continued)
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol
Parameter
Condition
VACIO
Analog Comparator Input
Offset Voltage
VCC = 5V
Vin = VCC/2
IACLK
Analog Comparator Input
Leakage A
VCC = 5V
Vin = VCC/2
tACPD
Analog Comparator
Propagation Delay
VCC = 2.7V
VCC = 4.0V
Notes:
Min
Typ
-50.0
750.0
500.0
Max
Units
40.0
mV
50.0
nA
ns
1. “Max” means the highest value where the pin is guaranteed to be read as low (logical “0”).
2. “Min” means the lowest value where the pin is guaranteed to be read as high (logical “1”).
3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOL, for all ports, should not exceed 200 mA.
2] The sum of all IOL, for port A0 - A7, should not exceed 100 mA.
3] The sum of all IOL, for ports B0 - B7, C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA.
PLCC and TQFP Packages:
1] The sum of all IOL, for all ports, should not exceed 400 mA.
2] The sum of all IOL, for ports A0 - A7, should not exceed 100 mA.
3] The sum of all IOL, for ports B0 - B3, should not exceed 100 mA.
4] The sum of all IOL, for ports B4 - B7, should not exceed 100 mA.
5] The sum of all IOL, for ports C0 - C3, should not exceed 100 mA.
6] The sum of all IOL, for ports C4 - C7, should not exceed 100 mA.
7] The sum of all IOL, for ports D0 - D3 and XTAL2, should not exceed 100 mA.
8] The sum of all IOL, for ports D4 - D7, should not exceed 100 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
4. Although each I/O port can source more than the test conditions (3 mA at VCC = 5V, 1.5 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOH, for all ports, should not exceed 200 mA.
2] The sum of all IOH, for port A0 - A7, should not exceed 100 mA.
3] The sum of all IOH, for ports B0 - B7, C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA.
PLCC and TQFP Packages:
1] The sum of all IOH, for all ports, should not exceed 400 mA.
2] The sum of all IOH, for ports A0 - A7, should not exceed 100 mA.
3] The sum of all IOH, for ports B0 - B3, should not exceed 100 mA.
4] The sum of all IOH, for ports B4 - B7, should not exceed 100 mA.
5] The sum of all IOH, for ports C0 - C3, should not exceed 100 mA.
6] The sum of all IOH, for ports C4 - C7, should not exceed 100 mA.
7] The sum of all IOH, for ports D0 - D3 and XTAL2, should not exceed 100 mA.
8] The sum of all IOH, for ports D4 - D7, should not exceed 100 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. Minimum VCC for power-down is 2V.
105
1041H–11/01
External Clock Drive
Waveforms
Figure 74. External Clock
VIH1
VIL1
Table 46. External Clock Drive
VCC = 2.7V to 6.0V
Symbol
1/tCLCL
106
Parameter
Oscillator Frequency
VCC = 4.0V to 6.0V
Min
Max
Min
Max
Units
0
4
0
8.0
MHz
tCLCL
Clock Period
250.0
125.0
ns
tCHCX
High Time
100.0
50.0
ns
tCLCX
Low Time
100.0
50.0
ns
tCLCH
Rise Time
1.6
0.5
µs
tCHCL
Fall Time
1.6
0.5
µs
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Typical
Characteristics
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins
configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage,
operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and
ambient temperature. The dominating factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as
CL•VCC•f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in with Watchdog Timer enabled and
Power-down mode with Watchdog Timer disabled represents the differential current
drawn by the Watchdog Timer.
Figure 75. Active Supply Current vs. Frequency
ACTIVE SUPPLY CURRENT vs. FREQUENCY
TA= 25˚C
40
Vcc= 6V
35
Vcc= 5.5V
I cc(mA)
30
Vcc= 5V
25
Vcc= 4.5V
20
Vcc= 4V
Vcc= 3.6V
15
Vcc= 3.3V
Vcc= 3.0V
Vcc= 2.7V
10
5
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Frequency (MHz)
107
1041H–11/01
Figure 76. Active Supply Current vs. VCC
ACTIVE SUPPLY CURRENT vs. Vcc
FREQUENCY = 4 MHz
16
14
TA = 25˚C
TA = 85˚C
I cc(mA)
12
10
8
6
4
2
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
Figure 77. Idle Supply Current vs. Frequency
IDLE SUPPLY CURRENT vs. FREQUENCY
TA= 25˚C
20
Vcc= 6V
18
Vcc= 5.5V
I cc(mA)
16
14
Vcc= 5V
12
Vcc= 4.5V
10
Vcc= 4V
Vcc= 3.6V
8
Vcc= 3.3V
6
Vcc= 3.0V
4
Vcc= 2.7V
2
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Frequency (MHz)
108
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Figure 78. Idle Supply Current vs. VCC
IDLE SUPPLY CURRENT vs. Vcc
FREQUENCY = 4 MHz
7
6
TA = 85˚C
TA = 25˚C
I cc(mA)
5
4
3
2
1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
Figure 79. Power-down Supply Current vs. VCC
POWER DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER DISABLED
90
TA = 85˚C
80
I cc(µΑ)
70
60
50
TA = 70˚C
40
30
TA = 45˚C
20
TA = 25˚C
10
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
109
1041H–11/01
Figure 80. Power-down Supply Current vs. VCC
POWER DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER ENABLED
140
120
I cc(µΑ)
100
TA = 85˚C
80
60
40
TA = 25˚C
20
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
Figure 81. Power Save Supply Current vs. VCC
POWER SAVE SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER DISABLED
90
TA = 85˚C
80
70
I cc(µΑ)
60
50
40
30
TA = 25˚C
20
10
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
110
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Figure 82. Analog Comparator Current vs. VCC
ANALOG COMPARATOR CURRENT vs. Vcc
1
0.9
0.8
TA = 25˚C
0.7
TA = 85˚C
I cc(mA)
0.6
0.5
0.4
0.3
0.2
0.1
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc(V)
Note:
Analog comparator offset voltage is measured as absolute offset.
Figure 83. Analog Comparator Offset Voltage vs. Common Mode Voltage
ANALOG COMPARATOR OFFSET VOLTAGE vs.
COMMON MODE VOLTAGE
Vcc = 5V
18
16
TA = 25˚C
Offset Voltage (mV)
14
12
TA = 85˚C
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Common Mode Voltage (V)
111
1041H–11/01
Figure 84. Analog Comparator Offset Voltage vs. Common Mode Voltage
ANALOG COMPARATOR OFFSET VOLTAGE vs.
COMMON MODE VOLTAGE
Vcc = 2.7V
10
TA = 25˚C
Offset Voltage (mV)
8
6
TA = 85˚C
4
2
0
0
0.5
1
1.5
2
2.5
3
Common Mode Voltage (V)
Figure 85. Analog Comparator Input Leakage Current
ANALOG COMPARATOR INPUT LEAKAGE CURRENT
VCC = 6V
TA = 25˚C
60
50
30
I
ACLK
(nA)
40
20
10
0
-10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
VIN (V)
112
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Figure 86. Watchdog Oscillator Frequency vs. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. Vcc
1600
TA = 25˚C
1400
TA = 85˚C
F RC (KHz)
1200
1000
800
600
400
200
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Vcc (V)
Note:
Sink and source capabilities of I/O ports are measured on one pin at a time.
Figure 87. Pull-up Resistor Current vs. Input Voltage
PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5V
120
TA = 25˚C
100
TA = 85˚C
I
OP (µA)
80
60
40
20
0
0
0.5
1
1.5
2
2.5
VOP (V)
3
3.5
4
4.5
5
113
1041H–11/01
Figure 88. Pull-up Resistor Current vs. Input Voltage
PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V
30
TA = 25˚C
25
TA = 85˚C
15
I
OP (µA)
20
10
5
0
0
0.5
1
1.5
2
2.5
3
VOP (V)
Figure 89. I/O Pin Sink Current vs. Output Voltage
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
70
TA = 25˚C
60
TA = 85˚C
50
30
I
OL (mA)
40
20
10
0
0
0.5
1
1.5
2
2.5
3
VOL (V)
114
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Figure 90. I/O Pin Source Current vs. Output Voltage
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
20
TA = 25˚C
18
16
TA = 85˚C
14
I
OH (mA)
12
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VOH (V)
Figure 91. I/O Pin Sink Current vs. Output Voltage
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
6
TA = 25˚C
5
TA = 85˚C
3
I
OH (mA)
4
2
1
0
0
0.5
1
1.5
2
2.5
3
VOH (V)
115
1041H–11/01
Figure 92. I/O Pin Source Current vs. Output Voltage
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
25
TA = 25˚C
20
TA = 85˚C
10
I
OL (mA)
15
5
0
0
0.5
1
1.5
2
VOL (V)
Figure 93. I/O Pin Input Threshold Voltage vs. VCC
I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
TA = 25˚C
2.5
Threshold Voltage (V)
2
1.5
1
0.5
0
2.7
4.0
5.0
Vcc
116
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Figure 94. I/O Pin Input Hysteresis vs. VCC
I/O PIN INPUT HYSTERESIS vs. Vcc
TA = 25˚C
0.18
0.16
Input hysteresis (V)
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
2.7
4.0
5.0
Vcc
117
1041H–11/01
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
$3F ($5F)
SREG
I
T
H
S
V
N
Z
C
page 19
$3E ($5E)
SPH
-
-
-
-
-
-
SP9
SP8
page 20
$3D ($5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
page 20
$3C ($5C)
Reserved
$3B ($5B)
GIMSK
INT1
INT0
-
-
-
-
-
-
$3A ($5A)
GIFR
INTF1
INTF0
$39 ($59)
TIMSK
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
-
TOIE0
page 26
$38 ($58)
TIFR
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
-
TOV0
page 27
$37 ($57)
Reserved
$36 ($56)
Reserved
page 25
page 26
$35 ($55)
MCUCR
-
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
page 29
$34 ($54)
MCUSR
-
-
-
-
-
-
EXTRF
PORF
page 24
$33 ($53)
TCCR0
-
-
-
-
-
CS02
CS01
CS00
$32 ($52)
TCNT0
$31 ($51)
Reserved
$30 ($50)
Reserved
Timer/Counter0 (8 Bits)
page 34
page 34
$2F ($4F)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
-
-
PWM11
PWM10
page 36
$2E ($4E)
TCCR1B
ICNC1
ICES1
-
-
CTC1
CS12
CS11
CS10
page 37
$2D ($4D)
TCNT1H
Timer/Counter1 – Counter Register High Byte
$2C ($4C)
TCNT1L
Timer/Counter1 – Counter Register Low Byte
page 38
$2B ($4B)
OCR1AH
Timer/Counter1 – Output Compare Register A High Byte
page 39
$2A ($4A)
OCR1AL
Timer/Counter1 – Output Compare Register A Low Byte
page 39
$29 ($49)
OCR1BH
Timer/Counter1 – Output Compare Register B High Byte
page 39
$28 ($48)
OCR1BL
Timer/Counter1 – Output Compare Register B Low Byte
page 39
$27 ($47)
ICR1H
Timer/Counter1 – Input Capture Register High Byte
page 40
$26 ($46)
ICR1L
Timer/Counter1 – Input Capture Register Low Byte
$25 ($45)
TCCR2
$24 ($44)
TCNT2
Timer/Counter2 (8 Bits)
$23 ($43)
OCR2
Timer/Counter2 Output Compare Register
$22 ($42)
ASSR
-
-
-
-
AS2
TCN2UB
OCR2UB
TCR2UB
page 46
$21 ($41)
WDTCR
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
page 49
$20 ($40)
Reserved
EEAR8
page 51
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
page 51
-
PWM2
COM21
page 38
page 40
COM20
CTC2
CS22
CS21
CS20
page 43
page 44
page 44
$1F ($3F)
EEARH
$1E ($3E)
EEARL
$1D ($3D)
EEDR
$1C ($3C)
EECR
-
-
-
-
EERIE
EEMWE
EEWE
EERE
page 51
$1B ($3B)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
page 76
$1A ($3A)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
page 76
$19 ($39)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
page 76
$18 ($38)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
page 78
$17 ($37)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
page 78
$16 ($36)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 78
$15 ($35)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
page 84
$14 ($34)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
page 84
$13 ($33)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
page 84
$12 ($32)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
page 87
$11 ($31)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
page 87
$10 ($30)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
page 87
EEPROM Data Register
page 51
$0F ($2F)
SPDR
$0E ($2E)
SPSR
SPIF
WCOL
-
-
-
-
-
-
page 58
$0D ($2D)
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
page 57
$0C ($2C)
UDR
$0B ($2B)
USR
page 62
$0A ($2A)
UCR
$09 ($29)
UBRR
SPI Data Register
page 58
UART I/O Data Register
page 62
RXC
TXC
UDRE
FE
OR
-
-
-
RXCIE
TXCIE
UDRIE
RXEN
TXEN
CHR9
RXB8
TXB8
UART Baud Rate Register
page 63
page 65
$08 ($28)
ACSR
ACD
-
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
page 66
$07 ($27)
ADMUX
-
-
-
-
-
MUX2
MUX1
MUX0
page 72
$06 ($26)
ADCSR
ADEN
ADSC
ADFR
ADIF
ADIE
ADPS2
ADPS1
ADPS0
page 72
$05 ($25)
ADCH
-
-
-
-
-
-
ADC9
ADC8
page 73
$04 ($24)
ADCL
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
page 73
$03 ($20)
Reserved
$02 ($22)
Reserved
$01 ($21)
Reserved
$00 ($20)
Reserved
118
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all
bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work
with registers $00 to $1F only.
119
1041H–11/01
Instruction Set Summary
Mnemonic
Operands
Description
Operation
Flags
# Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add Two Registers
Rd ← Rd + Rr
Z,C,N,V,H
1
ADC
Rd, Rr
Add with Carry Two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl, K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract Two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry Two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl, K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ←=Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd •=K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ←=Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd ← $FF − Rd
Z,C,N,V
1
1
NEG
Rd
Two’s Complement
Rd ← $00 − Rd
Z,C,N,V,H
SBR
Rd, K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd, K
Clear Bit(s) in Register
Rd ← Rd • ($FF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← $FF
None
1
BRANCH INSTRUCTIONS
RJMP
k
IJMP
Relative Jump
PC=← PC + k + 1
None
2
Indirect Jump to (Z)
PC ← Z
None
2
Relative Subroutine Call
PC ← PC + k + 1
None
3
ICALL
Indirect Call to (Z)
PC ← Z
None
3
RET
Subroutine Return
PC ← STACK
None
4
RETI
Interrupt Return
PC ← STACK
I
4
RCALL
k
CPSE
Rd, Rr
Compare, Skip if Equal
if (Rd = Rr) PC=← PC + 2 or 3
None
CP
Rd, Rr
Compare
Rd − Rr
Z,N,V,C,H
1/2/3
1
CPC
Rd, Rr
Compare with Carry
Rd − Rr − C
Z,N,V,C,H
1
CPI
Rd, K
Compare Register with Immediate
Rd − K
Z,N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b) = 0) PC ← PC + 2 or 3
None
1/2/3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b) = 1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b) = 0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b) = 1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC ←=PC + k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC ←=PC + k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
1
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half-carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half-carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T-flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T-flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if (I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if (I = 0) then PC ← PC + k + 1
None
1/2
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move between Registers
Rd ← Rr
None
1
LDI
Rd, K
Load Immediate
Rd ← K
None
1
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-inc.
Rd ← (X), X ← X + 1
None
2
LD
Rd, -X
Load Indirect and Pre-dec.
X ← X - 1, Rd ← (X)
None
2
120
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Instruction Set Summary (Continued)
Mnemonic
Operands
Description
Operation
Flags
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
# Clocks
2
LD
Rd, Y+
Load Indirect and Post-inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, -Y
Load Indirect and Pre-dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd, Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-inc.
Rd ← (Z), Z ← Z + 1
None
2
LD
Rd, -Z
Load Indirect and Pre-dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X)=← Rr
None
2
ST
X+, Rr
Store Indirect and Post-inc.
(X)=← Rr, X ← X + 1
None
2
ST
-X, Rr
Store Indirect and Pre-dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-inc.
(Y) ← Rr, Y ← Y + 1
None
2
ST
-Y, Rr
Store Indirect and Pre-dec.
Y ← Y - 1, (Y) ← Rr
None
2
STD
Y+q, Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-inc.
(Z) ← Rr, Z ← Z + 1
None
2
2
ST
-Z, Rr
Store Indirect and Pre-dec.
Z ← Z - 1, (Z) ← Rr
None
STD
Z+q, Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
In Port
Rd ← P
None
1
1
LPM
IN
Rd, P
OUT
P, Rr
Out Port
P ← Rr
None
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P, b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P, b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left through Carry
Rd(0) ←=C, Rd(n+1) ← Rd(n), C ←=Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right through Carry
Rd(7) ←=C, Rd(n) ← Rd(n+1), C ←=Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n = 0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit Load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C←1
C
1
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I=← 0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Two’s Complement Overflow
V←1
V
1
CLV
Clear Two’s Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
Set Half-carry Flag in SREG
H←1
H
1
CLH
Clear Half-carry Flag in SREG
H←0
H
1
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
Watchdog Reset
(see specific descr. for WDR/timer)
None
1
121
1041H–11/01
Ordering Information
Power Supply
Speed (MHz)
2.7 - 6.0V
4
4.0 - 6.0V
8
Ordering Code
Package
Operation Range
AT90LS8535-4AC
AT90LS8535-4JC
AT90LS8535-4PC
AT90LS8535-4MC
44A
44J
40P6
44M1
Commercial
(0°C to 70°C)
AT90LS8535-4AI
AT90LS8535-4JI
AT90LS8535-4PI
AT90LS8535-4MI
44A
44J
40P6
44M1
Industrial
(-40°C to 85°C)
AT90S8535-8AC
AT90S8535-8JC
AT90S8535-8PC
AT90LS8535-8MC
44A
44J
40P6
44M1
Commercial
(0°C to 70°C)
AT90S8535-8AI
AT90S8535-8JI
AT90S8535-8PI
AT90LS8535-8MI
44A
44J
40P6
44M1
Industrial
(-40°C to 85°C)
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6
40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (MLF)
122
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Packaging Information
44A
44-lead, Thin (1.0mm) Plastic Quad Flat Package
(TQFP), 10x10mm body, 2.0mm footprint, 0.8mm pitch.
Dimension in Millimeters and (Inches)*
JEDEC STANDARD MS-026 ACB
12.25(0.482)
SQ
11.75(0.462)
PIN 1 ID
PIN 1
0.45(0.018)
0.30(0.012)
0.80(0.0315) BSC
10.10(0.394)
SQ
9.90(0.386)
1.20(0.047) MAX
0.20(0.008)
0.09(0.004)
0˚~7˚
0.75(0.030)
0.45(0.018)
0.15(0.006)
0.05(0.002)
*Controlling dimension: millimetter
REV. A
04/11/2001
123
1041H–11/01
44J
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Milimeters and (Inches)*
JEDEC STANDARD MS-018 AC
1.14(0.045) X 45˚
0.813(0.032)
0.660(0.026)
PIN NO. 1
IDENTIFY
1.14(0.045) X 45˚
16.70(0.656)
SQ
16.50(0.650)
17.70(0.695)
SQ
17.40(0.685)
1.27(0.050) TYP
12.70(0.500) REF SQ
0.318(0.0125)
0.191(0.0075)
16.00(0.630)
SQ
15.00(0.590)
0.533(0.021)
0.330(0.013)
0.50(0.020)MIN
2.11(0.083)
1.57(0.062)
3.05(0.120)
2.29(0.090)
4.57(0.180)
4.19(0.165)
0.51(0.020)MAX 45˚ MAX (3X)
*Controlling dimensions: Inches
REV. A
124
04/11/2001
AT90S/LS8535
1041H–11/01
AT90S/LS8535
40P6
40-lead, Plastic Dual Inline
Parkage (PDIP), 0.600" wide
Demension in Millimeters and (Inches)*
JEDEC STANDARD MS-011 AC
52.71(2.075)
51.94(2.045)
PIN
1
13.97(0.550)
13.46(0.530)
48.26(1.900) REF
4.83(0.190)MAX
SEATING
PLANE
0.38(0.015)MIN
3.56(0.140)
3.05(0.120)
2.54(0.100)BSC
1.65(0.065)
1.27(0.050)
0.56(0.022)
0.38(0.015)
15.88(0.625)
15.24(0.600)
0º ~ 15º REF
0.38(0.015)
0.20(0.008)
17.78(0.700)MAX
*Controlling dimension: Inches
REV. A
04/11/2001
125
1041H–11/01
44M1
D
SEATING PLANE
Marked pin#1 identifier
E
A1
TOP VIEW
A3
A
L
SIDE VIEW
PIN #1 CORNER
D2
COMMON DIMENSIONS
(*Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
0.25 REF
A3
E2
b
0.18
D
D2
2.25
e
L
0.30
4.70
5.25
7.00 BSC
2.25
e
b
0.23
7.00 BSC
E
E2
NOTE
4.70
5.25
0.50 BSC
0.35
0.55
0.75
BOTTOM VIEW
NOTE 1. JEDEC STANDARD MO-220, Fig 1 (Saw Singulation), VKKD-1
07/23/01
R
126
DRAWING NO. REV
2325 Orchard Parkway TITLE
44M1, 44-pad ,7 x 7 x 1.0 mm body, lead pitch 0.50mm
44M1
A
San Jose, CA 95131
Micro lead frame package (MLF)
AT90S/LS8535
1041H–11/01
Atmel Headquarters
Atmel Product Operations
Corporate Headquarters
Atmel Colorado Springs
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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1041H–11/01/0M