LINER LT1175CST-5 500ma negative low dropout micropower regulator Datasheet

LT1175
500mA Negative
Low Dropout Micropower
Regulator
DESCRIPTION
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FEATURES
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Stable with Wide Range of Output Capacitors
Operating Current: 45µA
Shutdown Current: 10µA
Adjustable Current Limit
Positive or Negative Shutdown Logic
Low Voltage Linear Dropout Characteristics
Fixed 5V and Adjustable Versions
Tolerates Reverse Output Voltage
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APPLICATIONS
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The LT ®1175 is a negative micropower low dropout regulator. It features 45µA quiescent current, dropping to
10µA in shutdown. A new reference amplifier topology
gives precision DC characteristics along with the ability to
maintain good loop stability with an extremely wide range
of output capacitors. Very low dropout voltage and high
efficiency are obtained with a unique power transistor antisaturation design. Adjustable and fixed 5V versions are
available.
Several new features make the LT1175 very user-friendly.
The SHDN pin can interface directly to either positive or
negative logic levels. Current limit is user-selectable at
200mA, 400mA, 600mA and 800mA. The output can be
forced to reverse voltage without damage or latchup.
Unlike some earlier designs, the increase in quiescent
current during a dropout condition is actively limited.
Analog Systems
Modems
Instrumentation
A/D and D/A Converters
Interface Drivers
Battery-Powered Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
The LT1175 has complete blowout protection with current
limiting, power limiting and thermal shutdown. Special
attention was given to the problem of high temperature
operation with micropower operating currents, preventing
output voltage rise under no-load conditions. The LT1175
is available in 8-pin PDIP and SO packages, 3-lead SOT223 as well as 5-pin surface mount DD and through-hole
TO-220 packages. The 8-pin SO package is specially
constructed for low thermal resistance.
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TYPICAL APPLICATION
Minimum Input-to-Output Voltage
+
+
CIN*
SHDN
–VIN
GND
INPUT
ILIM2 LT1175-5
SENSE
COUT
≥ 0.1µF
–5V
UP TO 500mA
OUT
ILIM4
*CIN IS NEEDED ONLY IF REGULATOR IS MORE THAN 6" FROM
INPUT SUPPLY CAPACITOR. SEE APPLICATIONS INFORMATION
1175 TA01
SECTION FOR DETAILS
INPUT-TO-OUTPUT VOLTAGE (V)
1.0
Typical LT1175 Connection
TJ = 25°C
ILIM2, ILIM4 TIED TO VIN
0.8
0.6
0.4
0.2
0
0
0.1
0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)
0.6
0.7
1175 TA02
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LT1175
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Voltage (Transient 1 sec, Note 11) ................ 25V
Input Voltage (Continuous) .................................... 20V
Input-to-Output Differential Voltage (Note 12) ........ 20V
5V SENSE Pin (with Respect to GND Pin) ...... 2V, – 10V
ADJ SENSE Pin
(with Respect to OUTPUT Pin) ................ 20V, – 0.5V
5V SENSE Pin
(with Respect to OUTPUT Pin) .................. 20V, – 7V
Output Reverse Voltage ............................................ 2V
SHDN Pin to GND Pin Voltage (Note 2) ..... 13.5V, – 20V
SHDN Pin to VIN Pin Voltage .......................... 30V, – 5V
Operating Junction Temperature Range
LT1175C .............................................. 0°C to 125°C
LT1175I .......................................... – 40°C to 125°C
Ambient Operating Temperature Range
LT1175C ................................................ 0°C to 70°C
LT1175I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER
PART NUMBER
TOP VIEW
VIN 1
8
VIN
ILIM2 2
7
ILIM4
OUTPUT 3
6
SHDN
SENSE 4
5
GND
LT1175CN8
LT1175CN8-5
LT1175IN8
LT1175IN8-5
N8 PACKAGE
8-LEAD PDIP
θJA = 80°C/ W TO 120°C/W DEPENDING
ON PC BOARD LAYOUT
TOP VIEW
VIN 1
8
ILIM2 2
VIN
7
ILIM4
OUTPUT 3
6
SHDN
SENSE 4
5
GND
S8 PACKAGE
8-LEAD PLASTIC SO
θJA = 60°C/ W TO 100°C/W DEPENDING
ON PC BOARD LAYOUT
PINS 1, 8 ARE INTERNALLY
CONNECTED TO DIE
ATTACH PADDLE FOR HEAT
SINKING. ELECTRICAL
CONTACT CAN BE MADE TO
EITHER PIN. FOR BEST
THERMAL RESISTANCE,
PINS 1, 8 SHOULD BE
CONNECTED TO AN
EXPANDED LAND THAT IS
OVER AN INTERNAL OR
BACKSIDE PLANE.
SEE APPLICATIONS
INFORMATION
FRONT VIEW
5
4
3
2
1
TAB
IS
INPUT
SHDN
GND
INPUT
SENSE
OUTPUT
Q PACKAGE
5-LEAD PLASTIC DD
θJA = 27°C/ W TO 60°C/W DEPENDING
ON PC MOUNTING. SEE DATA SHEET
FOR DETAILS
LT1175CQ
LT1175CQ-5
LT1175IQ
LT1175IQ-5
S8 PART MARKING
1175
11755
TAB IS
INPUT
3
GND
2
VIN
1
OUTPUT
ORDER
PART NUMBER
LT1175CST-5
LT1175IST-5
ST PACKAGE
3-LEAD PLASTIC SOT-223
θJA = 50°C/ W WITH BACKPLANE
AND 10cm2 TOPSIDE LAND
SOLDERED TO TAB
ORDER
PART NUMBER
LT1175CS8
LT1175CS8-5
LT1175IS8
LT1175IS8-5
FRONT VIEW
ORDER
PART NUMBER
ORDER
PART NUMBER
FRONT VIEW
5
4
3
2
1
TAB IS
INPUT
SHDN
GND
INPUT
SENSE
OUTPUT
LT1175CT
LT1175CT-5
LT1175IT
LT1175IT-5
T PACKAGE
5-LEAD PLASTIC TO-220
θJA = 50°C/ W, θJC = 5°C/ W
1175I
1175I5
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VOUT = 5V, VIN = 7V, IOUT = 0, VSHDN = 3V, ILIM2 and ILIM4 tied to VIN, TJ = 25°C,
unless otherwise noted. To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as
absolute values except where polarity is not obvious.
PARAMETER
Feedback Sense Voltage
Output Voltage Initial Accuracy
Output Voltage Accuracy (All Conditions)
Quiescent Input Supply Current
CONDITIONS
Adjustable Part
Fixed 5V Part
Adjustable, Measured at 3.8V Sense
Fixed 5V
VIN – VOUT = 1V to VIN = 20V, IOUT = 0A to 500mA
P = 0 to PMAX, TJ = TMIN to TMAX (Note 3)
VIN – VOUT ≤ 12V
MIN
3.743
4.93
●
●
TYP
3.8
5.0
0.5
0.5
1.5
MAX
3.857
5.075
1.5
1.5
2.5
45
65
80
UNITS
V
V
%
%
%
µA
µA
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LT1175
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VOUT = 5V, VIN = 7V, IOUT = 0, VSHDN = 3V, ILIM2 and ILIM4 tied to VIN, TJ = 25°C,
unless otherwise noted. To avoid confusion with “min” and “max” as applied to negative voltages, all voltages are shown as
absolute values except where polarity is not obvious.
PARAMETER
CONDITIONS
GND Pin Current Increase with Load (Note 4)
Input Supply Current in Shutdown
VSHDN = 0V
MIN
●
TYP
MAX
UNITS
10
10
20
20
25
2.5
8
4
1
5
150
20
0.2
0.26
0.7
0.5
0.45
0.45
1300
975
650
325
0.015
0.35
0.1
0.2
1.25
µA/mA
µA
µA
V
µA
µA
µA
µA
nA
µA
V
V
V
V
V
V
mA
mA
mA
mA
%/V
%
%/W
%/W
%
●
Shutdown Thresholds (Note 9)
SHDN Pin Current (Note 2)
Output Bleed Current in Shutdown (Note 6)
Either Polarity On SHDN Pin
VSHDN = 0V to 10V (Flows Into Pin)
VSHDN = – 15V to 0V (Flows Into Pin)
VOUT = 0V, VIN = 15V
●
0.8
●
●
SENSE Pin Input Current
Dropout Voltage (Note 7)
Current Limit (Note 11)
Line Regulation (Note 10)
Load Regulation (Note 5, 10)
Thermal Regulation
Output Voltage Temperature Drift
(Adjustable Part Only, Current Flows Out of Pin)
(Fixed Voltage Only, Current Flows Out of Pin)
IOUT = 25mA
IOUT = 100mA
IOUT = 500mA
ILIM2 Open, IOUT = 300mA
ILIM4 Open, IOUT = 200mA
ILIM2, ILIM4 Open, IOUT = 100mA
VIN – VOUT = 1V to 12V
ILIM2 Open
ILIM4 Open
ILIM2, ILIM4 Open
VIN – VOUT = 1V to VIN = 20V
IOUT = 0mA to 500mA
P = 0 to PMAX (Notes 3, 8)
5-Pin Packages
8-Pin Packages
TJ = 25°C to TJMIN, or 25°C to TJMAX
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: SHDN pin maximum positive voltage is 30V with respect to
– VIN and 13.5V with respect to GND. Maximum negative voltage is – 20V
with respect to GND and – 5V with respect to – VIN.
Note 3: PMAX = 1.5W for 8-pin packages, and 6W for 5-pin packages. This
power level holds only for input-to-output voltages up to 12V, beyond
which internal power limiting may reduce power. See Guaranteed Current
Limit curve in Typical Performance Characteristics section. Note that all
conditions must be met.
Note 4: GND pin current increases because of power transistor base drive.
At low input-to-output voltages (< 1V) where the power transistor is in
saturation, GND pin current will be slightly higher. See Typical
Performance Characteristics.
Note 5: With ILOAD = 0, at TJ > 125°C, power transistor leakage could
increase higher than the 10µA to 25µA drawn by the output divider or fixed
voltage SENSE pin, causing the output to rise above the regulated value.
To prevent this condition, an internal active pull-up will automatically turn
on, but supply current will increase.
Note 6: This is the current required to pull the output voltage to within 1V
of ground during shutdown.
Note 7: Dropout voltage is measured by setting the input voltage equal to
the normal regulated output voltage and measuring the difference between
●
●
●
●
●
●
●
●
●
●
●
●
●
●
520
390
260
130
4
1
0.1
1
75
12
0.1
0.18
0.5
0.33
0.3
0.26
800
600
400
200
0.003
0.1
0.04
0.1
0.25
VIN and VOUT. For currents between 100mA and 500mA, with both ILIM
pins tied to VIN, maximum dropout can be calculated from
VDO = 0.15 + 1.1Ω (IOUT).
Note 8: Thermal regulation is a change in the output voltage caused by die
temperature gradients, so it is proportional to chip power dissipation.
Temperature gradients reach final value in less than 100ms. Output
voltage changes after 100ms are due to absolute die temperature changes
and reference voltage temperature coefficient.
Note 9: The lower limit of 0.8V is guaranteed to keep the regulator in
shutdown. The upper limit of 2.5V is guaranteed to keep the regulator
active. Either polarity may be used, referenced to GND pin.
Note 10: Load and line regulation are measured on a pulse basis with
pulse width of 20ms or less to keep chip temperature constant. DC
regulation will be affected by thermal regulation (Note 8) and chip
temperature changes. Load regulation specification also holds for currents
up to the specified current limit when ILIM2 or ILIM4 are left open.
Note 11: Current limit is reduced for input-to-output voltage above 12V.
See the graph in Typical Performance Characteristics for guaranteed limits
above 12V.
Note 12: Operating at very large input-to-output differential voltages
(>15V) with load currents less than 5mA requires an output capacitor with
an ESR greater than 1Ω to prevent low level output oscillations.
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TYPICAL PERFORMANCE CHARACTERISTICS
Typical Current Limit
Characteristics
CURRENT LIMIT CHANGES ONLY SLIGHTLY
WITH TEMPERATURE SO CURVES ARE
REPRESENTATIVE OF ALL TEMPERATURES
0.8
5.05
ILIM2, ILIM TIED TO VIN
0.5
CURRENT (A)
ILIM2, ILIM TIED TO VIN
CURRENT (A)
Output Voltage Temperature Drift
Guaranteed Current Limit
0.6
0.6
ILIM4 TIED TO VIN
0.4
ILIM2 TIED TO VIN
0.4
ILIM4 TIED TO VIN
0.3
ILIM2 TIED TO VIN
CURVES REPRESENT MINIMUM
GUARANTEED
LIMITS AT ALL
TEMPERATURES
OUTPUT
FIXED 5V PART
5.00
VOLTAGE (V)
1.0
4.95
3.84
0.2
ILIM2, ILIM4 OPEN
0.2
3.80
0.1
ILIM2, ILIM4 OPEN
0
0
5
15
20
0
25
10
INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)
1175 G02
SENSE Bias Current
(Adjustable Part)
1.0
0.6
ILIM2 TIED
TO VIN
ILIM2, ILIM4
OPEN
0.4
ILIM4 TIED
TO VIN
0.2
ILIM2, ILIM4
TIED TO VIN
0
100
VIN REDUCED UNTIL OUTPUT
VOLTAGE DROPS 1%.
ILIM2, ILIM4 TIED TO VIN
0.8
80
CURRENT (nA)
0.8
INPUT-TO-OUTPUT VOLTAGE (V)
0.6
TJ = 125°C
0.4
0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)
0.1
0.6
0.7
0
0.1
0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)
1175 G04
0.6
0
–50 –25
0.7
15
POSITIVE THRESHOLD
THRESHOLD (V)
2.0
TJ = 25°C
TJ = 125°C
10
TJ = –55°C
5
10
1.5
NEGATIVE THRESHOLD
1.0
0.5
5
15
10
INPUT VOLTAGE (V)
20
25
1175 G07
5
0
–50 –25
25 50
0
75
TEMPERATURE (°C)
100
125
1175 G08
VIN = 25V
CHARACTERISTICS DO NOT
CHANGE SIGNIFICANTLY WITH
TEMPERATURE, SO A SINGLE
CURVE IS SHOWN. POSITIVE
CURRENT FLOWS INTO
SHDN PIN
0
–5
DEVICE IS OFF
BELOW THRESHOLD
0
125
SHDN Pin Characteristics
2.5
20
100
1175 G06
Shutdown Thresholds
Shutdown Input Current
15
50
25
0
75
TEMPERATURE (°C)
1175 G05
25
0
40
20
TJ = –55°C
0
0
60
TJ = 25°C
0.2
PIN CURRENT (µA)
INPUT-TO-OUTPUT VOLTAGE (V)
1.0
125
1175 G03
Minimum Input-to-Output Voltage
Minimum Input-to-Output Voltage
INPUT CURRENT (µA)
3.76
50
25
0
75 100
–50 –25
JUNCTION TEMPERATURE (°C)
25
0
5
10
15
20
INPUT-TO-OUTPUT DIFFERENTIAL VOLTAGE (V)
1175 G01
TJ = 25°C
VIN REDUCED
UNTIL OUTPUT
VOLTAGE
DROPS 1%
FEEDBACK VOLTAGE
ADJUSTABLE PART
IF SHDN PIN IS NEGATIVE WITH
RESPECT TO INPUT VOLTAGE AND
INPUT VOLTAGE IS LESS THAN 15V,
NEGATIVE BREAKOVER POINT WILL
BE ABOUT 8V BELOW –VIN
–10
–25 –20 –15 –10 –5 0 5 10 15 20 25
SHUTDOWN TO GROUND VOLTAGE (V)
1175 G09
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LT1175
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TYPICAL PERFORMANCE CHARACTERISTICS
Ripple Rejection
GND pin Current
100
VOUT = 12V
(ADJUSTABLE)
WITH 0.1µF ACROSS
DIVIDER RESISTOR
80
16
REJECTION (dB)
GROUND PIN CURRENT (mA)
20
12
POWER
TRANSISTOR
IN DROPOUT
TJ = –55°C
TJ = 25°C
8
4
VIN – VOUT = 2V
TJ = 25°C
0
0.1
VOUT = 5V
(FIXED)
VOUT = 12V
(ADJUSTABLE)
40
20
VIN – VOUT ≥ 3V
TJ = 25°C
0
60
0.2 0.3 0.4
0.5
OUTPUT CURRENT (A)
0.6
0.7
1175 G10
IOUT = 100mA
VIN – VOUT = 2V
COUT = 1µF TANT
0
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
RIPPLE REJECTION IS RELATIVELY INDEPENDENT OF
INPUT VOLTAGE AND LOAD FOR CURRENTS BETWEEN
25mA AND 500mA. LARGER OUTPUT CAPACITORS DO
NOT IMPROVE REJECTION FOR FREQUENCIES BELOW
50kHz. AT VERY LIGHT LOADS, REJECTION WILL
IMPROVE WITH LARGER OUTPUT CAPACITORS 1175 G11
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PIN FUNCTIONS
SENSE Pin: The SENSE pin is used in the adjustable
version to allow custom selection of output voltage, with
an external divider set to generate 3.8V at the SENSE pin.
Input bias current is typically 75nA flowing out of the pin.
Maximum forced voltage on the SENSE pin is 2V and –10V
with respect to GND pin.
The fixed 5V version utilizes the SENSE pin to give true
Kelvin connections to the load or to drive an external pass
transistor for higher output currents. Bias current out of
the 5V SENSE pin is approximately 12µA. Separating the
SENSE and OUTPUT pins also allows for a new loop
compensation technique described in the Applications
Information section.
SHDN Pin: The SHDN pin is specially configured to allow
it to be driven from either positive voltage logic or with
negative only logic. Forcing the SHDN pin 2V either above
or below the GND pin will turn the regulator on. This makes
it simple to connect directly to positive logic signals for
active low shutdown. If no positive voltages are available,
the SHDN pin can be driven below the GND pin to turn the
regulator on. When left open, the SHDN pin will default low
to a regulator “on” condition. For all voltages below
absolute maximum ratings, the SHDN pin draws only a few
microamperes of current (see Typical Performance Characteristics). Maximum voltage on the SHDN pin is 15V,
– 20V with respect to the GND pin and 35V, – 5V with
respect to the negative input pin.
ILIM Pins: The two current limit pins are emitter sections
of the power transistor. When left open, they float several
hundred millivolts above the negative input voltage. When
shorted to the input voltage, they increase current limit by
a minimum of 200mA for ILIM2 and 400mA for ILIM4. These
pins must be connected only to the input voltage, either
directly or through a resistor.
OUTPUT Pin: The OUTPUT pin is the collector of the NPN
power transistor. It can be forced to the input voltage, to
ground or up to 2V positive with respect to ground without
damage or latchup (see Output Voltage Reversal in Applications Information section). The LT1175 has foldback
current limit, so maximum current at the OUTPUT pin is a
function of input-to-output voltage. See Typical Performance Characteristics.
GND Pin: The GND pin has a quiescent current of 45µA at
zero load current, increasing by approximately 10µA per
mA of output current. At 500mA output current, GND pin
current is about 5mA. Current flows into the GND pin.
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LT1175
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APPLICATIONS INFORMATION
Note to Reader: To avoid confusion when working with
negative voltages (is – 6V more or less than – 5V?), I have
decided to treat the LT1175 as if it were a positive
regulator and express all voltages as positive values, both
in text and in formulas. If you do the same and simply add
a negative sign to the eventual answer, confusion should
be avoided. Please don’t give me a hard time about
“preciseness” or “correctness.” I have to field phone calls
from around the world and this is my way of dealing with
a multitude of conventions. Thanks for your patience.
The LT1175-5 is a fixed 5V design with the SENSE pin
acting as a Kelvin connection to the output. Normally the
SENSE pin and the OUTPUT pin are connected directly
together, either close to the regulator or at the remote load
point.
SHUTDOWN
LOGIC
+
> 2V OR < –2V TO
TURN REGULATOR ON
+
SHDN
GND
INPUT
ILIM2
Setting Output Voltage
The LT1175 adjustable version has a feedback sense
voltage of 3.8V with a bias current of approximately 75nA
flowing out of the SENSE pin. To avoid output voltage
errors caused by this current, the output divider string
(see Figure 1) should draw about 25µA. Table 1 shows
suggested resistor values for a range of output voltages.
The second part of the table shows resistor values which
draw only 10µA of current. Output voltage error caused by
bias current with the lower valued resistors is about 0.4%
maximum and with the higher values, about 1% maximum. A formula is also shown for calculating the resistors
for any output voltage.
Table 1
OUTPUT
VOLTAGE
R1
IDIV = 25µA
R2
R1
NEAREST 1% IDIV = 10µA
R2
NEAREST 1%
5V
150k
47.5k
383k
121k
6V
150k
86.6k
383k
221k
8V
150k
165k
383k
422k
10V
150k
243k
383k
619k
12V
150k
324k
383k
825k
15V
150k
442k
383k
1.13M
R1 =
ILIM4
SENSE
LT1175
OUT
R2
825k
1%
COUT
≥ 0.1µF
VOUT
–12V
1175 F01
Figure 1. Typical LT1175 Adjustable Connection
Setting Current Limit
The LT1175 uses two ILIM pins to set current limit (typical)
at 200mA, 400mA, 600mA or 800mA. The corresponding
minimum guaranteed currents are 130mA, 260mA, 390mA
and 520mA. This allows the user to select a current limit
tailored to his specific application and prevents the situation where short-circuit current is many times higher than
full-load current. Problems with input supply overload or
excessive power dissipation in a faulted load are prevented. Power limiting in the form of foldback current limit
is built in and reduces current limit as a function of inputto-output voltage differential for differentials exceeding
14V. See the graph in Typical Performance Characteristics.
The LT1175 is guaranteed to be blowout-proof regardless
of current limit setting. The power limiting combined with
thermal shutdown protects the device from destructive
junction temperatures under all load conditions.
Shutdown
3.8V
IDIV
) (Simple formula)
3.8V
R1( V − 3.8V) ⎛ Taking SENSE pin bias⎞
R2 =
⎜
⎟
3.8V + R1(I ) ⎝ current into account ⎠
R2 =
R1
383k
1%
CIN
(
R1 VOUT − 3.8V
OUT
FB
IDIV = Desired divider current
In shutdown, the LT1175 draws only about 10µA. Special
circuitry is used to minimize increases in shutdown current at high temperatures, but a slight increase is seen
above 125°C. One option not taken was to actively pull
down on the output during shutdown. This means that the
output will fall slowly after shutdown is initiated, at a rate
determined by load current plus the 12µA internal load,
and the size of the output capacitor. Active pull-down is
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APPLICATIONS INFORMATION
normally a good thing when the regulator is used by itself,
but it prevents the user from shutting down the regulator
when a second power source is connected to the LT1175
output. If active output pull-down is needed in shutdown,
it can be added externally with a depletion mode PFET as
shown in Figure 2. Note that the maximum pinch-off
voltage of the PFET must be less than the positive logic
high level to ensure that the device is completely off when
the regulator is active. The Motorola J177 device has
300Ω on resistance for zero gate source voltage.
3V TO 5V
s
Q1*
d
+
SHDN
–VIN
GND
INPUT
ILIM2
COUT
≥ 0.1µF
SENSE
LT1175-5
OUT
ILIM4
* MOTOROLA J177
PINCH-OFF VOLTAGE MUST BE LESS THAN
POSITIVE LOGIC HIGH VOLTAGE
1175 F02
Figure 2. Active Output Pull-Down During Shutdown
Minimum Dropout Voltage
Dropout voltage is the minimum voltage required between
input and output to maintain proper output regulation. For
older 3-terminal regulator designs, dropout voltage was
typically 1.5V to 3V. The LT1175 uses a saturating power
transistor design which gives much lower dropout voltage, typically 100mV at light loads and 450mV at full load.
Special precautions were taken to ensure that this technique does not cause quiescent supply current to be high
under light load conditions. When the regulator input
voltage is too low to maintain a regulated output, the pass
transistor is driven hard by the error amplifier as it tries to
maintain regulation. The current drawn by the driver
transistor could be tens of milliamperes even with little or
no load on the output. This indeed was the case for older
IC designs that did not actively limit driver current when
the power transistor saturated. The LT1175 uses a new
antisaturation technique that prevents high driver current,
yet allows the power transistor to approach its theoretical
saturation limit.
Output Capacitor
Several new regulator design techniques are used to make
the LT1175 extremely tolerant of output capacitor selection. Like most low dropout designs which use a collector
or drain of the power transistor to drive the output node,
the LT1175 uses the output capacitor as part of the overall
loop compensation. Older regulators generally required
the output capacitor to have a minimum value of 1µF to
100µF, a maximum ESR (Effective Series Resistance) of
0.1Ω to 1Ω and a minimum ESR in the range of 0.03Ω to
0.3Ω. These restrictions usually could be met only with
good quality solid tantalum capacitors. Aluminum capacitors have problems with high ESR unless much higher
values of capacitance are used (physically large). The ESR
of ceramic or film capacitors was too low, which made the
capacitance/ESR zero frequency too high to maintain
phase margin in the regulator. Even with optimum capacitors, loop phase margin was very low in previous designs
when output current was low. These problems led to a new
design technique for the LT1175 error amplifier and internal frequency compensation as shown in Figure 3.
A conventional regulator loop consists of error amplifier
A1, driver transistor Q2 and power transistor Q1. Added to
this basic loop are secondary loops generated by Q3 and
CF. A DC negative feedback current fed into the error
amplifier through Q3 and RN causes overall loop current
gain to be very low at light load currents. This is not a
problem because very little gain is needed at light loads. In
addition to low gain, the parasitic pole frequency at Q2
base is extended by the DC feedback. The combination of
these two effects dramatically improves loop phase margin at light loads and makes the loop tolerant of large ESR
in the output capacitor. With heavy loads, loop phase and
gain are not nearly as troublesome and large negative
feedback could degrade regulation. The logarithmic behavior of the base emitter voltage of Q1 reduces Q3 negative
feedback at heavy loads to prevent poor regulation.
In a conventional design, even with the nonlinear feedback, poor loop phase margin would occur at medium to
heavy loads if the ESR of the output capacitor fell below
1175fd
7
LT1175
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APPLICATIONS INFORMATION
GND
LT1175
+
3.8V
R1
–
COUT
A1
LOAD
+
ESR
R2
SENSE
Q2
AC
FEEDFORWARD
PATH
OUT
CF
20pF
OUTPUT
RC
0.5Ω
NEGATIVE DC
FEEDBACK
AT LIGHT
LOADS
Q3
PARASITIC
COLLECTOR
RESISTANCE
Q1
POWER
TRANSISTOR
RN
RLIM
CURRENT LIMIT
SENSE RESISTOR
1175 F03
–VIN
Figure 3
0.3Ω. This condition can occur with ceramic or film
capacitors which often have an ESR under 0.1Ω. With
previous designs, the user was forced to add a real resistor
in series with the capacitor to guarantee loop stability. The
LT1175 uses a unique AC feedforward technique to eliminate this problem. CF is a conventional feedforward capacitor often used in regulators to cancel the pole formed
by the output capacitor. It would normally be connected
from the regulated output node to the feedback node at the
R1/R2 junction or to an internal node on the amplifier as
shown. In this case, however, the capacitor is connected
to the internal structure of the power transistor. RC is the
unavoidable parasitic collector resistance of the power
transistor. Access to the node at the bottom of RC is
available only in monolithic structures where Kelvin connections can be made to the NPN buried collector layer.
The loop now responds as if RC were in series with the
output capacitor and good loop stability is achieved even
with extremely low ESR in the output capacitor.
The end result of all this attention to loop stability is that
the output capacitor used with the LT1175 can range in
value from 0.1µF to hundreds of microfarads, with an ESR
from 0Ω to 10Ω. This range allows the use of ceramic,
solid tantalum, aluminum and film capacitors over a wide
range of values.
The optimum output capacitor type for the LT1175 is still
solid tantalum, but there is considerable leeway in selecting the exact unit. If large load current transients are
expected, larger capacitors with lower ESR may be needed
to control worst-case output variation during transients. If
transients are not an issue, the capacitor can be chosen for
small physical size, low price, etc. Concerns about surge
currents in tantalum capacitors are not an issue for the
output capacitor because the LT1175 limits inrush current
to well below the level which can cause capacitor damage.
Surges caused by shorting the regulator output are also
not a problem because tantalum capacitors do not fail
1175fd
8
LT1175
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APPLICATIONS INFORMATION
during a “shorting out” surge, only during a “charge up”
surge.
The output capacitor should be located within several
inches of the regulator. If remote sensing is used, the
output capacitor can be located at the remote sense node,
but the GND pin of the regulator should also be connected
to the remote site. The basic rule is to keep SENSE and
GND pins close to the output capacitor, regardless of
where it is.
Operating at very large input-to-output differential voltages (> 5V) with load currents less than 5mA requires an
output capacitor with an ESR greater than 1Ω to prevent
low level output oscillations.
Input Capacitor
The LT1175 requires a separate input bypass capacitor
only if the regulator is located more than six inches from
the raw supply output capacitor. A 1µF or larger tantalum
capacitor is suggested for all applications, but if low ESR
capacitors such as ceramic or film are used for the output
and input capacitors, the input capacitor should be at least
three times the value of the output capacitor. If a solid
tantalum or aluminum electrolytic output capacitor is
used, the input capacitor is very noncritical.
High Temperature Operation
The LT1175 is a micropower design with only 45µA
quiescent current. This could make it perform poorly at
high temperatures (>125°C), where power transistor leakage might exceed the output node loading current (5µA to
15µA). To avoid a condition where the output voltage drifts
uncontrolled high during a high temperature no-load
condition, the LT1175 has an active load which turns on
when the output is pulled above the nominal regulated
voltage. This load absorbs power transistor leakage and
maintains good regulation. There is one downside to this
feature, however. If the output is pulled high deliberately,
as it might be when the LT1175 is used as a backup to a
slightly higher output from a primary regulator, the LT1175
will act as an unwanted load on the primary regulator.
Because of this, the active pull-down is deliberately “weak.”
It can be modeled as a 2k resistor in series with an internal
clamp voltage when the regulator output is being pulled
high. If a 4.8V output is pulled to 5V, for instance, the load
on the primary regulator would be (5V – 4.8V)/2kΩ =
100µA. This also means that if the internal pass transistor
leaks 50µA, the output voltage will be (50µA)(2kΩ) =
100mV high. This condition will not occur under normal
operating conditions, but could occur immediately after
an output short circuit had overheated the chip.
Thermal Considerations
The LT1175 is available in a special 8-pin surface mount
package which has Pins 1 and 8 connected to the die attach
paddle. This reduces thermal resistance when Pins 1 and
8 are connected to expanded copper lands on the PC
board. Table 2 shows thermal resistance for various
combinations of copper lands and backside or internal
planes. Table 2 also shows thermal resistance for the 5-pin
DD surface mount package and the 8-pin DIP and package.
Table 2. Package Thermal Resistance (°C/W)
LAND AREA
DIP
ST
SO
Q
Minimum
140
90
100
60
Minimum with
Backplane
110
70
80
50
1cm2 Top Plane
with Backplane
100
64
75
35
10cm2 Top Plane
with Backplane
80
50
60
27
To calculate die temperature, maximum power dissipation
or maximum input voltage, use the following formulas
with correct thermal resistance numbers from Table 2. For
through-hole TO-220 applications use θJA = 50°C/W
without a heat sink and θJA = 5°C/W + heat sink thermal
resistance when using a heat sink.
(
)( )
Die Temp = TA + θJA VIN − VOUT ILOAD
Maximum Power Dissipation =
Maximum Input Voltage
for Thermal Considerations
=
TMAX − TA
θJA
TMAX − TA
( )
θJA ILOAD
+ VOUT
1175fd
9
LT1175
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APPLICATIONS INFORMATION
TA
= Maximum ambient temperature
TMAX = Maximum LT1175 die temperature (125°C for
commercial and industrial grades)
θJA
= LT1175 thermal resistance, junction to ambient
VIN
= Maximum continuous input voltage at maximum
load current
NPN power transistor structure that has a parasitic diode
between the input and output of the regulator. Reverse
voltages between input and output above 1V will damage
the regulator if large currents are allowed to flow. Simply
disconnecting the input source with the output held up will
not cause damage even though the input-to-output voltage will become slightly reversed.
ILOAD = Maximum load current
High Frequency Ripple Rejection
Example: LT1175S8 with ILOAD = 200mA, VOUT = 5V,
VIN = 7V, TA = 60°C. Maximum die temperature for the
LT1175S8 is 125°C. Thermal resistance from Table 2 is
found to be 80°C/W.
The LT1175 will sometimes be powered from switching
regulators that generate the unregulated or quasi-regulated input voltage. This voltage will contain high frequency ripple that must be rejected by the linear regulator.
Special care was taken with the LT1175 to maximize high
frequency ripple rejection, but as with any micropower
design, rejection is strongly affected by ripple frequency.
The graph in the Typical Performance Characteristics
section shows 60dB rejection at 1kHz, but only 15dB
rejection at 100kHz for the 5V part. Photographs in Figures
4a and 4b show actual output ripple waveforms with
square wave and triwave input ripple.
Die Temperature = 60 + 80 (0.2A)(8 – 5) = 108°C
125 – 60
= 0.81W
80
Maximum Continuous
125 – 60
=
+ 5 = 9V
Input Voltage
80
0
.
2
(for Thermal Considerations)
Maximum Power Dissipation =
( )
Output Voltage Reversal
The LT1175 is designed to tolerate an output voltage
reversal of up to 2V. Reversal might occur, for instance, if
the output was shorted to a positive 5V supply. This would
almost surely destroy IC devices connected to the negative
output. Reversal could also occur during start-up if the
positive supply came up first and loads were connected
between the positive and negative supplies. For these
reasons, it is always good design practice to add a reverse
biased diode from each regulator output to ground to limit
output voltage reversal. The diode should be rated to
handle full negative load current for start-up situations, or
the short-circuit current of the positive supply if supply-tosupply shorts must be tolerated.
COUT = 4.7µF TANT
OUTPUT
20mV/DIV
COUT = 1µF TANT
INPUT
RIPPLE
100mV/DIV
f = 50kHz
5µs/DIV
1175 F04
Figure 4a.
COUT = 4.7µF TANT
OUTPUT
100mV/DIV
COUT = 1µF TANT
Input Voltage Lower Than Output
Linear Technology’s positive low dropout regulators
LT1121 and LT1129, will not draw large currents if the
input voltage is less than the output. These devices use a
lateral PNP power transistor structure that has 40V emitter
base breakdown voltage. The LT1175, however, uses an
INPUT
RIPPLE
100mV/DIV
f = 100kHz
2µs/DIV
1175 F04
Figure 4b.
1175fd
10
LT1175
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APPLICATIONS INFORMATION
To estimate regulator output ripple under different conditions, the following general comments should be helpful:
1. Output ripple at high frequency is only weakly affected
by load current or output capacitor size for medium to
heavy loads. At very light loads (<10mA), higher frequency ripple may be reduced by using larger output
capacitors.
2. A feedforward capacitor across the resistor divider
used with the adjustable part is effective in reducing
ripple only for output voltages greater than 5V and only
for frequencies less than 100kHz.
3. Input-to-output voltage differential has little effect on
ripple rejection until the regulator actually enters a
dropout condition of 0.2V to 0.6V.
If ripple rejection needs to be improved, an input filter can
be added. This filter can be a simple RC filter using a 1Ω
to 10Ω resistor. A 3.3Ω resistor for instance, combined
with a 0.3Ω ESR solid tantalum capacitor, will give an
additional 20dB ripple rejection. The size of the resistor
will be dictated by maximum load current. If the maximum
voltage drop allowable across the resistor is “VR,” and
maximum load current is ILOAD, R = VR /ILOAD. At light
loads, larger resistors and smaller capacitors can be used
to save space. At heavier loads an inductor may have to be
used in place of the resistor. The value of the inductor can
be calculated from:
LFIL =
ESR
(
2π ( f) 10 rr / 20
)
ESR = Effective series resistance of filter capacitor. This
assumes that the capacitive reactance is small
compared to ESR, a reasonable assumption for
solid tantalum capacitors above 2.2µF and 50kHz.
f
= Ripple frequency
rr
= Ripple rejection ratio of filter in dB
Example: ESR = 1.2Ω, f = 100kHz, rr = – 25dB.
L FIL =
1.2
= 34µH
6.3 ⎛⎝ 10 5⎞⎠ ⎛⎝10 −25 / 20 ⎞⎠
Solid tantalum capacitors are suggested for the filter to
keep filter Q fairly low. This prevents unwanted ringing at
the resonant frequency of the filter and oscillation problems with the filter/regulator combination.
1175fd
11
LT1175
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PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
+.035
.325 –.015
(
8.255
+0.889
–0.381
)
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.065
(1.651)
TYP
.100
(2.54)
BSC
.120
(3.048) .020
MIN (0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
N8 1002
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1175fd
12
LT1175
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PACKAGE DESCRIPTIO
Q Package
5-Lead Plastic DD Pak
(Reference LTC DWG # 05-08-1461)
.256
(6.502)
.060
(1.524)
TYP
.060
(1.524)
.390 – .415
(9.906 – 10.541)
.165 – .180
(4.191 – 4.572)
.045 – .055
(1.143 – 1.397)
15° TYP
.060
(1.524)
.183
(4.648)
+.008
.004 –.004
+0.203
0.102 –0.102
.059
(1.499)
TYP
.330 – .370
(8.382 – 9.398)
(
)
.095 – .115
(2.413 – 2.921)
.075
(1.905)
.300
(7.620)
+.012
.143 –.020
+0.305
3.632 –0.508
(
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
.067
(1.702)
.028 – .038 BSC
(0.711 – 0.965)
TYP
)
Q(DD5) 0502
.420
.276
.080
.420
.050 ± .012
(1.270 ± 0.305)
.013 – .023
(0.330 – 0.584)
.325
.350
.205
.565
.565
.320
.090
.090
.067
.042
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
1. DIMENSIONS IN INCH/(MILLIMETER)
2. DRAWING NOT TO SCALE
.067
.042
RECOMMENDED SOLDER PAD LAYOUT
FOR THICKER SOLDER PASTE APPLICATIONS
1175fd
13
LT1175
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PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
2
3
4
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
SO8 0303
1175fd
14
LT1175
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PACKAGE DESCRIPTIO
ST Package
3-Lead Plastic SOT-223
(Reference LTC DWG # 05-08-1630)
.248 – .264
(6.30 – 6.71)
.129 MAX
.114 – .124
(2.90 – 3.15)
.059 MAX
.264 – .287
(6.70 – 7.30)
.248 BSC
.130 – .146
(3.30 – 3.71)
.039 MAX
.059 MAX
.181 MAX
.033 – .041
(0.84 – 1.04)
.0905
(2.30)
BSC
.090
BSC
RECOMMENDED SOLDER PAD LAYOUT
10° – 16°
.010 – .014
(0.25 – 0.36)
10°
MAX
.071
(1.80)
MAX
10° – 16°
.024 – .033
(0.60 – 0.84)
.181
(4.60)
BSC
.012
(0.31)
MIN
.0008 – .0040
(0.0203 – 0.1016)
ST3 (SOT-233) 0502
1175fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT1175
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PACKAGE DESCRIPTIO
T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)
.165 – .180
(4.191 – 4.572)
.147 – .155
(3.734 – 3.937)
DIA
.390 – .415
(9.906 – 10.541)
.045 – .055
(1.143 – 1.397)
.230 – .270
(5.842 – 6.858)
.570 – .620
(14.478 – 15.748)
.460 – .500
(11.684 – 12.700)
.620
(15.75)
TYP
.330 – .370
(8.382 – 9.398)
.700 – .728
(17.78 – 18.491)
.095 – .115
(2.413 – 2.921)
SEATING PLANE
.152 – .202
.260 – .320 (3.861 – 5.131)
(6.60 – 8.13)
.155 – .195*
(3.937 – 4.953)
.013 – .023
(0.330 – 0.584)
BSC
.067
(1.70)
.028 – .038
(0.711 – 0.965)
.135 – .165
(3.429 – 4.191)
* MEASURED AT THE SEATING PLANE
T5 (TO-220) 0801
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1121
150mA Positive Micropower Low Dropout Regulator with Shutdown
LT1129
700mA Positive Micropower Low Dropout Regulator with Shutdown
LT1185
3A Negative Low Dropout Regulator
LT1521
300mA Positive Micropower Low Dropout Regulator with Shutdown
LT1529
3A Positive Micropower Low Dropout Regulator with Shutdown
1175fd
16
Linear Technology Corporation
LT/LT 0305 REV D • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1995