PHILIPS N74F648AD Octal transceiver/register, non-inverting 3-state Datasheet

INTEGRATED CIRCUITS
74F646, 74F646A
Octal transceiver/register, non-inverting
(3-State)
74F648, 74F648A
Octal transceiver/register, inverting
(3-State)
Product specification
IC15 Data Handbook
1990 Sep 25
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
FEATURES
DESCRIPTION
• Combines 74F245 and two 74F374 type functions in one chip
• High impedance base inputs for reduced loading (70µA in high
The 74F646/74F646A and 74F648/74F648A transceivers/registers
consist of bus transceiver circuits with 3–state outputs, D–type
flip–flops, and control circuitry arranged for multiplexed transmission
of data directly from the input bus or the internal registers. Data on
the A or B bus will be clocked into the registers as the appropriate
clock pin goes high. Output enable (OE) and DIR pins are provided
to control the transceiver function. In the transceiver mode, data
present at the high impedance port may be stored in either the A or
B register or both.
and low states)
• Independent registers for A and B buses
• Multiplexed real-time and stored data
• Choice of non-inverting and inverting data paths
• Controlled ramp outputs for 74F646A/74F648A
• 3-state outputs
• 300 mil wide 24-pin slim dip package
The select (SAB, SBA) pins determine whether data is stored or
transferred through the device in real–time. The DIR determines
which bus will receive data when the OE is active low. In the
isolation mode (OE = high), data from bus A may be stored in the B
register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
TYPE
TYPICAL fmax
TYPICAL SUPPLY CURRENT ( TOTAL)
74F646/74F648
115MHz
140mA
74F646A/74F648A
185MHz
105mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
PKG DWG #
VCC = 5V ±10%, Tamb = 0°C to +70°C
24–pin plastic slim DIP
(300mil)
N74F646N, N74F646AN, N74F648N, N74F648AN
SOT222-1
24–pin plastic SOL
N74F646D, N74F646AD, N74F648D, N74F648AD
SOT137-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
A and B inputs
3.5/0.116
70µA/70µA
PINS
A0 – A7, B0 – B7
DESCRIPTION
CPAB
A–to–B clock input
1.0/0.033
20µA/20µA
CPBA
B–to–A clock input
1.0/0.033
20µA/20µA
SAB
A–to–B select input
1.0/0.033
20µA/20µA
SBA
B–to–A select input
1.0/0.033
20µA/20µA
DIR
Data flow directional control enable input
1.0/0.033
20µA/20µA
OE
Output enable input
1.0/0.033
20µA/20µA
750/80
15mA/48mA
750/106.7
15mA/64mA
A0 – A7, B0 – B7
A, B outputs for N74F646A/N74F648A
A0 – A7, B0 – B7
A, B outputs for N74F646/N74F648
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
1990 Sep 25
2
853-1124 00515
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
PIN CONFIGURATION
IEC/IEEE SYMBOL
74F646/646A
74F646/646A
21
G3
CPAB
1
24 V
CC
SAB
2
23 CPBA
DIR
3
22 SBA
23
A0
4
21 OE
22
A1
5
20 B0
A2
6
19 B1
A3
7
18 B2
A4
8
17 B3
A5
9
16 B4
A6
10
15 B5
5
A7
11
14 B6
6
18
GND 12
13 B7
7
17
8
16
3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
1
C6
2
G7
1
4
5
1
1
SF00386
1
5
7
6D
7
20
4D
1
2
19
9
15
/
10
14
11
13
LOGIC SYMBOL
SF00388
74F646/646A
4
5
6
7
8
9
10
11
LOGIC DIAGRAM
A0 A1 A2 A3 A4 A5 A6 A7
1
2
CPAB
SAB
3
23
22
DIR
CPBA
SBA
21
OE
DIR3
23
CPBA
22
SBA
1
CPAB
2
SAB
OE
B0 B1 B2 B3 B4 B5 B6 B7
VCC = Pin 24
GND = Pin 12
20
19
18
17
16
15
14
74F646/646A
21
I of 8 channels
13
1D
C1
SF00387
A0
4
20
B0
1D
C1
VCC = Pin 24
GND = Pin 12
1990 Sep 25
3
to 7 other channels
SF00393
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
PIN CONFIGURATION
IEC/IEEE SYMBOL
74F648/648A
74F648/648A
21
24 V
CC
CPAB 1
SAB 2
23 CPBA
DIR 3
22 SBA
A0 4
21 OE
A1 5
20 B0
G3
3
3 EN1 [BA]
3 EN2 [AB]
23
C4
22
G5
1
C6
2
A2 6
19 B1
A3 7
18 B2
A4 8
17 B3
A5 9
16 B4
G7
1
4
5
1
5
7
6D
1
20
4D
1
1
7
2
A6 10
15 B5
5
A7 11
14 B6
6
18
7
17
8
16
9
15
10
14
11
13
GND 12
13 B7
SF00389
19
LOGIC SYMBOL
SF00391
74F648/648A
4
5
6
7
8
9
10
11
LOGIC DIAGRAM
1
2
CPAB
SAB
3
23
22
DIR
CPBA
SBA
21
74F648/648A
21
A0 A1 A2 A3 A4 A5 A6 A7
OE
DIR
CPBA
SBA
CPAB
SAB
OE
3
23
22
1
2
B0 B1 B2 B3 B4 B5 B6 B7
I of 8 channels
VCC = Pin 24
GND = Pin 12
20
19
18
17
16
15
14
1D
C1
13
SF00390
A0
4
20
B0
1D
C1
to 7 other channels
1990 Sep 25
4
SF00400
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
OE
DIR
CPAB
CPBA
SAB
SBA
An
Bn
74F646/74F646A
74F648/74F648A
X
X
↑
X
X
X
Input
Unspecified*
Store A, B unspecified*
Store A, B unspecified*
X
X
X
↑
X
X
Unspecified*
Input
Store B, A unspecified*
Store B, A unspecified*
H
X
↑
↑
X
X
Input
Input
Store A and B data
Store A and B data
H
X
H or L
H or L
X
X
Input
Input
Isolation, hold storage
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real time B data to A bus
Real time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real time A data to B bus
Real time A data to B bus
L
NOTES:
1. H =
2. L =
3. X =
4. ↑ =
5. * =
H
H or L
X
H
X
Input
Output
Stored A data to B bus
Stored A data to B bus
High–voltage level
Low–voltage level
Don’t care
Low–to–high clock transition
The data output function may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every low–to–high transition of the clock.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
VCC
Supply voltage
–0.5 to +7.0
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
–30 to +5
mA
VOUT
Voltage applied to output in high output state
–0.5 to VCC
V
IOUT
Current applied to output in low output state
74F646A, 74F648A
72
mA
74F646, 74F648
128
mA
0 to +70
°C
–65 to +150
°C
Tamb
Operating free air temperature range
Tstg
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
NOM
MAX
5.0
5.5
VCC
Supply voltage
4.5
VIH
High–level input voltage
2.0
VIL
Low–level input voltage
0.8
V
IIk
Input clamp current
–18
mA
IOH
High–level output current
–15
mA
IOL
Low–level output current
74F646A, 74F648A
48
mA
74F646, 74F648
64
mA
+70
°C
Tamb
1990 Sep 25
Operating free air temperature range
0
5
V
V
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
data is stored or transferred through the device in real time. The
output enable pins determine the direction of the data flow.
The following examples demonstrate the four fundamental
bus–management functions that can be performed with the
74F646/646A and 74F648/648A. The select pins determine whether
BUS MANAGEMENT FUNCTIONS
REAL TIME BUS TRANSFER
BUS B TO BUS A
BUS A
BUS B
OE DIR CPAB CPBA SAB SBA
L
L
X
X
X
L
STORAGE FROM
A, B, OR A AND B
REAL TIME BUS TRANSFER
BUS A TO BUS B
BUS A
BUS A
BUS B
OE DIR CPAB CPBA SAB SBA
L
H
X
X
L
X
BUS B
OE DIR CPAB CPBA SAB SBA
X
X
↑
X
X
X
X
X
X
↑
X
X
H
X
↑
↑
X
X
TRANSFER STORED DATA
TO A AND/OR B
BUS A
BUS B
OE DIR CPAB CPBA SAB SBA
L
L
X H or L X
H
L
H H or L X
H
X
SF00392
1990 Sep 25
6
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
CONDITIONS1
±10%VCC
2.4
±5%VCC
2.7
IOH =
–15mA
±10%VCC
2.0
VCC = MIN,
VIL = MAX,
IOL = 48mA
±10%VCC
VIH = MIN
IOL = 64mA
±5%VCC
VCC = MIN,
VOH
High-level output voltage
Low-level output voltage
VIK
II
IIH
IIL
Input clamp voltage
Input current at
maximum input voltage
High–level input current
Low–level input current
IOZH + IIH
Off–state output current,
high–level voltage applied
IOZL + IIL
Off–state output current,
low–level voltage applied
IOS
Short–circuit output current3
All
74F646/74F648 only
IO
ICC
Output
current4
IOH = –3mA
VIL = MAX,
VIH = MIN
VOL
others
A0–A7, B0–B7
OE, DIR, CPAB,
CPBA, SAB, SBA
A0 – A7, B0 –B7
74F646, 74F648
74F646A, 74F648A
UNIT
MAX
V
3.4
V
V
0.38
0.55
V
0.42
0.55
V
–0.73
-1.2
100
1
20
–20
V
µA
mA
µA
µA
VCC = MAX, VO = 2.7V
70
µA
VCC = MAX, VO = 0.5V
–70
µA
-225
mA
VCC = MIN, II = IIK
VCC = 0.0V, VI = 7.0V
VCC = MAX, VI = 5.5V
VCC = MAX, VI = 2.7V
VCC = MAX, VI = 0.5V
VCC = MAX
-100
VCC = MAX, V0 = 2.25V
-60
-150
mA
165
mA
160
210
mA
ICCZ
135
160
mA
ICCH
100
145
mA
110
155
mA
105
155
ICCH
74F648
ICCL
74F646A,
74F648A
TYP2
125
74F646,
Supply current (total)
MIN
ICCL
VCC = MAX
VCC = MAX
ICCZ
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
Unless otherwise specified, VX = VCC for all test conditions.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. IO is tested under conditions that produce current approximately one half of the true short–circuit output current (IOS).
1990 Sep 25
7
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
AC ELECTRICAL CHARACTERISTICS FOR 74F646
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MAX
MIN
UNIT
MIN
TYP
fmax
Maximum clock frequency
Waveform 1
100
115
MAX
tPLH
tPHL
Propagation delay
CPAB or CPBA to An or Bn
Waveform 1
5.5
5.5
7.5
8.0
10.0
10.0
5.0
5.0
11.5
11.0
ns
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
Waveform 2
4.0
4.0
6.0
6.5
9.0
8.0
4.0
4.0
10.0
10.0
ns
tPLH
tPHL
Propagation delay
SAB or SBA to An or Bn
Waveform 2, 3
5.0
5.0
7.0
6.5
8.5
8.5
4.5
4.5
10.5
9.5
ns
tPZH
tPZL
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
5.0
6.5
7.0
8.5
10.0
11.0
4.5
6.0
11.0
12.5
ns
tPZH
tPZL
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
4.5
6.0
6.5
8.5
9.0
11.0
4.0
5.5
10.0
12.5
ns
tPHZ
tPLZ
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
6.5
6.5
9.0
9.0
11.5
11.5
6.0
6.0
12.5
13.5
ns
tPHZ
tPLZ
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
5.5
5.5
8.5
8.5
11.0
11.0
4.5
5.0
13.0
12.5
ns
90
MHz
AC SETUP REQUIREMENTS FOR 74F646
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST CONDITION
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
tsu (H)
tsu (L)
Setup time, high or low
An or Bn to CPAB or CPBA
th (H)
th (L)
tw (H)
tw (L)
1990 Sep 25
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL= 50pF, RL = 500Ω
MIN
UNIT
MAX
Waveform 4
4.5
4.5
5.0
5.0
ns
Hold time, high or low
An or Bn to CPAB or CPBA
Waveform 4
0
0
0
0
ns
Pulse width, high or low
CPAB or CPBA
Waveform 1
4.0
6.0
4.0
6.0
ns
8
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
AC ELECTRICAL CHARACTERISTICS FOR 74F648
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MAX
MIN
UNIT
MIN
TYP
fmax
Maximum clock frequency
Waveform 1
100
115
MAX
tPLH
tPHL
Propagation delay
CPAB or CPBA to An or Bn
Waveform 1
5.0
5.0
7.0
7.5
9.5
9.5
4.5
4.5
11.0
11.0
ns
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
Waveform 3
3.0
4.0
6.0
6.0
8.5
8.5
2.5
3.5
9.5
9.5
ns
tPLH
tPHL
Propagation delay
SAB or SBA to An or Bn
Waveform 2,3
4.5
4.5
7.0
6.5
8.5
8.5
4.5
4.5
10.5
9.5
ns
tPZH
tPZL
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
4.5
6.0
7.0
8.5
10.0
11.0
4.5
5.5
11.0
12.5
ns
tPZH
tPZL
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
4.5
6.0
7.0
8.5
10.0
11.0
4.0
5.5
11.0
12.5
ns
tPHZ
tPLZ
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
6.0
6.0
9.0
8.5
11.5
12.0
6.0
6.0
12.5
13.5
ns
tPHZ
tPLZ
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
5.0
5.0
9.0
9.0
12.5
12.5
4.5
5.0
14.0
14.0
ns
90
MHz
AC SETUP REQUIREMENTS FOR 74F648
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST CONDITION
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
tsu (H)
tsu (L)
Setup time, high or low
An or Bn to CPAB or CPBA
th (H)
th (L)
tw (H)
tw (L)
1990 Sep 25
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
Waveform 4
4.0
4.0
5.0
5.0
ns
Hold time, high or low
An or Bn to CPAB or CPBA
Waveform 4
0
0
0
0
ns
Pulse width, high or low
CPAB or CPBA
Waveform 1
3.5
6.5
4.0
7.0
ns
9
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
AC ELECTRICAL CHARACTERISTICS FOR 74F646A
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MAX
MIN
UNIT
MIN
TYP
fmax
Maximum clock frequency
Waveform 1
165
185
MAX
tPLH
tPHL
Propagation delay
CPAB or CPBA to An or Bn
Waveform 1
5.5
4.5
7.0
7.0
10.5
9.5
4.5
4.0
11.0
10.0
ns
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
Waveform 2
4.0
2.0
6.0
5.0
9.0
8.0
3.5
2.0
10.0
8.0
ns
tPLH
tPHL
Propagation delay
SAB or SBA to An or Bn
Waveform 2, 3
4.5
3.5
6.5
8.0
9.5
10.0
4.0
3.0
10.0
11.5
ns
tPZH
tPZL
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
3.0
3.0
5.5
5.5
9.0
10.0
2.5
2.5
10.0
10.5
ns
tPZH
tPZL
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
3.0
3.5
5.0
6.0
8.0
8.5
3.0
3.0
8.5
9.5
ns
tPHZ
tPLZ
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
1.5
2.5
4.0
5.5
6.5
8.0
1.0
2.0
8.0
9.5
ns
tPHZ
tPLZ
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
2.0
3.0
4.5
5.0
7.5
8.0
1.5
2.0
8.5
8.5
ns
150
MHz
AC SETUP REQUIREMENTS FOR 74F646A
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST CONDITION
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
tsu (H)
tsu (L)
Setup time, high or low
An or Bn to CPAB or CPBA
th (H)
th (L)
tw (H)
tw (L)
1990 Sep 25
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
Waveform 4
3.5
4.0
4.0
4.5
ns
Hold time, high or low
An or Bn to CPAB or CPBA
Waveform 4
0
0
0
0
ns
Pulse width, high or low
CPAB or CPBA
Waveform 1
3.5
3.5
4.5
4.0
ns
10
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
AC ELECTRICAL CHARACTERISTICS FOR 74F648A
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST CONDITION
Tamb = 0°C to +70°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MAX
MIN
UNIT
MIN
TYP
fmax
Maximum clock frequency
Waveform 1
160
185
MAX
tPLH
tPHL
Propagation delay
CPAB or CPBA to An or Bn
Waveform 1
5.0
5.5
7.0
7.5
9.5
10.0
4.5
4.5
10.5
10.5
ns
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
Waveform 3
2.5
4.0
4.5
6.0
7.5
8.5
2.0
4.0
8.5
9.5
ns
tPLH
tPHL
Propagation delay
SAB or SBA to An or Bn
Waveform 2, 3
4.0
4.5
7.0
7.0
9.5
9.5
3.5
4.5
11.5
10.0
ns
tPZH
tPZL
Output enable time
OE to An or Bn
Waveform 5
Waveform 6
3.5
4.5
6.5
6.5
10.0
10.0
3.5
4.0
11.0
11.5
ns
tPZH
tPZL
Output enable time
DIR to An or Bn
Waveform 5
Waveform 6
3.5
4.0
5.5
6.5
8.5
9.5
3.0
4.0
9.0
10.0
ns
tPHZ
tPLZ
Output disable time
OE to An or Bn
Waveform 5
Waveform 6
2.5
4.0
4.0
6.5
6.5
9.0
2.0
3.5
8.0
10.0
ns
tPHZ
tPLZ
Output disable time
DIR to An or Bn
Waveform 5
Waveform 6
2.5
2.5
5.0
5.0
8.5
8.0
2.0
3.5
9.0
9.0
ns
135
ns
AC SETUP REQUIREMENTS FOR 74F648A
LIMITS
Tamb = +25°C
SYMBOL
PARAMETER
TEST CONDITION
MIN
tsu (H)
tsu (L)
Setup time, high or low
An or Bn to CPAB or CPBA
th (H)
th (L)
tw (H)
tw (L)
Tamb = 0°C to +70°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
TYP
MAX
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
Waveform 4
4.0
4.0
4.5
4.5
ns
Hold time, high or low
An or Bn to CPAB or CPBA
Waveform 4
0
0
0
0
ns
Pulse width, high or low
CPAB or CPBA
Waveform 1
3.5
3.5
4.0
3.5
ns
AC WAVEFORMS
1/fmax
CPBA
or
CPAB
VM
An or Bn
VM
tw(H)
VM
tPHL
tPHL
An or Bn
tw(L)
VM
tPLH
tPLH
VM
Bn or An
SF00394
VM
VM
An or Bn
SF00395
Waveform 2. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
Waveform 1. Propagation delay for clock input to output clock
pulse width, and maximum clock frequency
1990 Sep 25
SBA or SAB
VM
VM
11
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
AC WAVEFORMS (Continued)
OE
An or Bn
VM
tPLH
VM
SBA or SAB
VM
VM
DIR
tPZH
tPHL
An or Bn
Bn or An
VM
VM
An or Bn
VM
VOH -0.3V
tPHZ
0V
SF00398
SF00396
Waveform 5. 3-state output enable time to high level and
output disable time from high level
Waveform 3. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
OE
VM
VM
DIR
An or Bn
VM
tsu(H)
VM
VM
VM
tsu(L)
th(H)
tPZL
tPLZ
th(L)
An or Bn
CPBA
or
CPAB
VM
3.5V
VM
VM
VOL +0.3V
SF00399
SF00397
Waveform 6. 3-state output enable time to low level and output
disable time from low level
Waveform 4. Data setup time and hold times
NOTES:
1. For all waveforms, VM = 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORM
VCC
7.0V
VIN
RL
VOUT
PULSE
GENERATOR
tw
90%
NEGATIVE
PULSE
VM
CL
AMP (V)
VM
10%
D.U.T.
RT
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
RL
AMP (V)
90%
90%
Test Circuit for Open Collector Outputs
POSITIVE
PULSE
VM
VM
10%
TEST
tPLZ
tPZL
All other
SWITCH
closed
closed
open
DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
10%
tw
SWITCH POSITION
0V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00128
1990 Sep 25
12
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
DIP24: plastic dual in-line package; 24 leads (300 mil)
1990 Sep 25
13
SOT222-1
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
SO24: plastic small outline package; 24 leads; body width 7.5 mm
1990 Sep 25
14
SOT137-1
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
NOTES
1990 Sep 25
15
Philips Semiconductors
Product specification
Transceivers/registers
74F646/A/74F648/A
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
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16
Date of release: 10-98
9397-750-05151