240pin Load Reduced DDR3(L) SDRAM DIMM
DDR3(L) SDRAM Load Reduced DIMM
Based on 4Gb A-die
HMT84GL7AMR4A
HMT84GL7AMR4C
*SK hynix reserves the right to change products or specifications without notice.
Rev. 0.3 / Jul. 2013
1
Revision History
Revision No.
History
Draft Date
0.1
Initial Release
Mar.2013
0.2
IDD Specification Update &
Changed module maximum thickness
to reflect the measured maximum
Jun.2013
0.3
IDD Update
(Montage 1.5V 1866Mbps)
Jul.2013
Rev. 0.3 / Jul. 2013
Remark
2
Description
SK hynix Load Reduced DDR3(L) SDRAM DIMMs are low power, high-speed operation memory modules
that use SK hynix DDR3(L) SDRAM devices. These Load Reduced DIMMs are intended for use as main
memory when installed in systems such as servers and workstations.
Features
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240 pin Load Reduced DDR3(L) DRAM Dual In-Line Memory Module
Buffer performance by LRDIMM presenting less load to system
Compatible with RDIMM systems with appropriate BIOS changes
Backward Compatible with 1.5V DDR3 Memory Module
(1.35V could not support the upper 1.5V speed)
Built with 4Gb DDR3 SDRAM 78ball
Data transfer rates: Up to PC3L-12800 / PC3-14900
JEDEC standard Double Data Rate3 Synchronous DRAMs(DDR3 SDRAMs) with 1.5V nominal
JEDEC standard Double Data Rate3L Synchronous DRAMs(DDR3L SDRAMs) with 1.35V nominal
Functionality and operations are same with DDR3 & DDR3L about same speed bin
Host interface and MB(Memory Buffer) component industry standard compliant
MB provides “address multiplication” to generate additional chips selects
Address mirroring
ODT (On-Die Termination)
133.35 x 30.35 mm form factor
Full DIMM Heat Spreader
This product is in compliance with the RoHS directive.
Ordering Information
Part Number
Density Organization
HMT84GL7AMR4A
-H9/PB
# of
ranks
MB
FDHS
Height
O
30.35mm
Vendor version
Montage
C1
Inphi
GS02B
Montage
C1
Inphi
GS02B
DDP 2Gx4(H5TC8G43AMR)*36
32GB
HMT84GL7AMR4C
-H9/PB/RD
Component Composition
4Gx72
4
DDP 2Gx4(H5TQ8G43AMR)*36
* In order to uninstall FDHS, please contact sales administrator
Rev. 0.3 / Jul. 2013
3
Key Parameters
MT/s
Grade
tCK
(ns)
CAS
Latency
(tCK)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
CL-tRCD-tRP
DDR3-1066
-G7
1.875
7
13.125
13.125
37.5
50.625
7-7-7
DDR3-1333
-H9
1.5
9
13.5
13.5
(13.125)* (13.125)*
36
49.5
(49.125)*
9-9-9
DDR3-1600
-PB
1.25
11
13.75
13.75
(13.125)* (13.125)*
35
48.75
(48.125)*
11-11-11
DDR3-1866
-Rd
1.07
13
13.91
13.91
(13.125)* (13.125)*
34
47.91
(48.125)*
13-13-13
*SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Frequency [MHz]
Grade
Remark
CL6
CL7
CL8
CL9
CL10
-G7
800
1066
1066
-H9
800
1066
-PB
800
-RD
800
CL11
1066
1333
1333
1066
1066
1333
1333
1600
1066
1066
1333
1333
1600
CL12
CL13
1866
Address Table
32GB(4Rx4)
Refresh Method
8K/64ms
Row Address
A0-A15
Column Address
A0-A9,A11
Bank Address
BA0-BA2
Page Size
1KB
Rev. 0.3 / Jul. 2013
4
Pin Descriptions
Pin Name
Description
Num
ber
Pin Name
Description
Num
ber
CK0
Clock Input, positive line
1
Par_In
Parity bit for the Address and Control bus
1
CK0
Clock Input, negative line
1
Err_Out
Parity error found on the Address
and Control bus
1
CK1
Clock Input, positive line
1
ODT[0]
CK1
Clock Input, negative line
1
DQ[63:0]
Clock Enables
2
CB[7:0]
2
DQS[8:0]
CKE[1:0]
On Die Termination Inputs
1
Data Input/Output
64
Data check bits Input/Output
8
Clock Enables
On Die Termination
CKE[3:2],
ODT[1], TEST Memory bus tool (Not Connected and Not Useable on
DIMMs)
Data strobes
RAS
Row Address Strobe
1
DQS[8:0]
CAS
Column Address Strobe
1
DM[8:0]/
DQS[17:9],
TDQS[17:9]
WE
Write Enable
1
DQS[17:9],
TDQS[17:9]
S[1:0]
Chip Selects
2
EVENT
S[3:2], A17,
A16
Chip Selects
2
TEST
Memory bus test tool (Not Connected and Not Usable on DIMMs)
1
Address Inputs
14
RESET
Register and SDRAM control pin
1
A10/AP
Address Input/Autoprecharge
1
VDD
Power Supply
22
A12/BC
Address Input/Burst chop
1
VSS
Ground
59
BA[2:0]
SDRAM Bank Addresses
3
VREFDQ
Reference Voltage for DQ
1
Reference Voltage for CA
1
Termination Voltage
4
A[9:0],A11,
A[15:13]
Address Inputs
SCL
Serial Presence Detect (SPD)
Clock Input
1
VREFCA
SDA
SPD Data Input/Output
1
VTT
SPD Address Inputs
3
VDDSPD
SA[2:0]
Rev. 0.3 / Jul. 2013
Data strobes, negative line
9
Data Masks / Data strobes,
Termination data strobes
Data Masks / Data strobes,
Termination data strobes
Reserved for optional hardware
temperature sensing
SPD Power
9
9
9
1
1
5
Input/Output Functional Descriptions
Symbol
Type
Polarity
Function
CK0
IN
Positive
Line
Positive line of the differential pair of system clock inputs that drives input to the onDIMM Clock Driver.
CK0
IN
Negative
Line
Negative line of the differential pair of system clock inputs that drives the input to the
on-DIMM Clock Driver.
CK1
IN
Positive
Line
Terminated but not used on RDIMMs.
CK1
IN
Negative
Line
Terminated but not used on RDIMMs.
CKE[1:0]
IN
Active
High
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN
(row ACTIVE in any bank)
Enables the command decoders for the associated rank of SDRAM when low and disables decoders when high. When decoders are disabled, new commands are ignored
and previous operations continue. Other combinations of these input signals perform
unique functions, including disabling all outputs (except CKE and ODT) of the register(s)
on the DIMM or accessing internal control words in the register device(s). For modules
with two registers, S[3:2] operate similarly to S[1:0] for the second set of register outputs or register control words.
S[3:0]
IN
Active
Low
ODT[1:0]
IN
Active
High
On-Die Termination control signals
RAS, CAS, WE
IN
Active
Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
VREFDQ
Supply
Reference voltage for DQ0-DQ63 and CB0-CB7.
VREFCA
Supply
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In,
ODT0 and ODT1.
BA[2:0]
IN
—
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines mode register is to be accessed during an MRS
cycle.
A[15:13,
12/BC,11,
10/AP,[9:0]
IN
—
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL
4/8 identification for ‘’BL on the fly’’ during CAS command. The address inputs also provide the op-code during Mode Register Set commands.
DQ[63:0],
CB[7:0]
I/O
—
Data and Check Bit Input/Output pins
DM[8:0]
IN
Active
High
VDD, VSS
Supply
Power and ground for the DDR SDRAM input buffers and core logic.
VTT
Supply
Termination Voltage for Address/Command/Control/Clock nets.
Rev. 0.3 / Jul. 2013
Masks write data when high, issued concurrently with input data.
6
Symbol
Type
Polarity
Function
DQS[17:0]
I/O
Positive
Edge
Positive line of the differential data strobe for input and output data.
DQS[17:0]
I/O
Negative
Edge
Negative line of the differential data strobe for input and output data.
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is
applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will
provide the data mask function and TDQS is not used. X4 DRAMs must disable the TDQS
function via mode register A11=0 in MR1
TDQS[17:9]
TDQS[17:9]
OUT
SA[2:0]
IN
—
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
SDA
I/O
—
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to VDDSPD on the system planar to act as a
pullup.
SCL
IN
—
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
EVENT
OUT
(open
drain)
VDDSPD
Supply
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
RESET
IN
The RESET pin is connected to the RESET pin on the register and to the RESET pin on
the DRAM.
Par_In
IN
Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
Err_Out
OUT
(open
drain)
TEST
Rev. 0.3 / Jul. 2013
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
Active Low
EVENT pin on TS/SPD part.
No pull-up resister is provided on DIMM.
Parity error detected on the Address and Control bus. A resistor may be connected from
Err_Out bus line to VDD on the system planar to act as a pull up.
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
7
Pin Assignments
Pin #
Front Side
(left 1–60)
Pin #
Back Side
(right 121–180)
Pin #
Front Side
(left 61–120)
Pin #
Back Side
(right 181–240)
1
VREFDQ
121
VSS
61
A2
181
A1
2
VSS
122
DQ4
62
VDD
182
VDD
3
DQ0
123
DQ5
63
NC, CK1
183
VDD
4
DQ1
124
VSS
64
NC, CK1
184
CK0
5
VSS
125
DM0,DQS9,
TDQS9
65
VDD
185
CK0
6
DQS0
126
NC,DQS9,
TDQS9
66
VDD
186
VDD
7
DQS0
127
VSS
67
VREFCA
187
EVENT, NC
8
VSS
128
DQ6
68
Par_In, NC
188
A0
9
DQ2
129
DQ7
69
VDD
189
VDD
10
DQ3
130
VSS
70
A10 / AP
190
BA1
11
VSS
131
DQ12
71
BA0
191
VDD
12
DQ8
132
DQ13
72
VDD
192
RAS
13
DQ9
133
VSS
73
WE
193
S0
14
VSS
134
DM1,DQS10,
TDQS10
74
CAS
194
VDD
15
DQS1
135
NC,DQS10,
TDQS10
75
VDD
195
ODT0
16
DQS1
136
VSS
76
S1, NC
196
A13
17
VSS
137
DQ14
77
ODT1, NC
197
VDD
18
DQ10
138
DQ15
78
VDD
198
S3, NC
19
DQ11
139
VSS
79
S2, NC
199
VSS
20
VSS
140
DQ20
80
VSS
200
DQ36
21
DQ16
141
DQ21
81
DQ32
201
DQ37
22
DQ17
142
VSS
82
DQ33
202
VSS
83
VSS
203
DM4,DQS13,
TDQS13
23
VSS
143
DM2,DQS11,
TDQS11
24
DQS2
144
NC,DQS11,
TDQS11
84
DQS4
204
NC,DQS13,
TDQS13
25
DQS2
145
VSS
85
DQS4
205
VSS
26
VSS
146
DQ22
86
VSS
206
DQ38
27
DQ18
147
DQ23
87
DQ34
207
DQ39
28
DQ19
148
VSS
88
DQ35
208
VSS
29
VSS
149
DQ28
89
VSS
209
DQ44
30
DQ24
150
DQ29
90
DQ40
210
DQ45
31
DQ25
151
VSS
91
DQ41
211
VSS
NC = No Connect; RFU = Reserved Future Use
Rev. 0.3 / Jul. 2013
8
Pin #
Front Side
(left 1–60)
Pin #
Back Side
(right 121–180)
Pin #
Front Side
(left 61–120)
Pin #
Back Side
(right 181–240)
32
VSS
152
DM3,DQS12,
TDQS12
92
VSS
212
DM5,DQS14,
TDQS14
33
DQS3
153
NC,DQS12,
TDQS12
93
DQS5
213
NC,DQS14,
TDQS14
34
DQS3
154
VSS
94
DQS5
214
VSS
35
VSS
155
DQ30
95
VSS
215
DQ46
36
DQ26
156
DQ31
96
DQ42
216
DQ47
37
DQ27
157
VSS
97
DQ43
217
VSS
38
VSS
158
CB4, NC
98
VSS
218
DQ52
39
CB0, NC
159
CB5, NC
99
DQ48
219
DQ53
40
CB1, NC
160
VSS
100
DQ49
220
VSS
41
VSS
161
NC,DM8,DQS17,
TDQS17
101
VSS
221
DM6,DQS15,
TDQS15
42
DQS8
162
NC,DQS17,
TDQS17
102
DQS6
222
NC,DQS15,
TDQS15
43
DQS8
163
VSS
103
DQS6
223
VSS
44
VSS
164
CB6, NC
104
VSS
224
DQ54
45
CB2, NC
165
CB7, NC
105
DQ50
225
DQ55
46
CB3, NC
166
VSS
106
DQ51
226
VSS
47
VSS
167
NC(TEST)
107
VSS
227
DQ60
48
VTT, NC
168
RESET
108
DQ56
228
DQ61
109
DQ57
229
VSS
KEY
KEY
49
VTT, NC
169
CKE1, NC
110
VSS
230
DM7,DQS16,
TDQS16
50
CKE0
170
VDD
111
DQS7
231
NC,DQS16,
TDQS16
51
VDD
171
A15
112
DQS7
232
VSS
52
BA2
172
A14
113
VSS
233
DQ62
53
Err_Out, NC
173
VDD
114
DQ58
234
DQ63
54
VDD
174
A12 / BC
115
DQ59
235
VSS
55
A11
175
A9
116
VSS
236
VDDSPD
56
A7
176
VDD
117
SA0
237
SA1
57
VDD
177
A8
118
SCL
238
SDA
58
A5
178
A6
119
SA2
239
VSS
59
A4
179
VDD
120
VTT
240
VTT
60
VDD
180
A3
NC = No Connect; RFU = Reserved Future Use
Rev. 0.3 / Jul. 2013
9
Functional Block Diagram
32GB, 4Gx72 Module(4Rank of x4) - page1
QCKE0A
QODT0A
QCKE1A
QODT1A
QCS0A
QCS2A
QCS1A
QCS3A
VDD
CS0 CS1
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS3
MDQS3
MDQ [24:27]
DQS3
DQS3
DQ [24:27]
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
VSS
D0
ZQ
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
DQS
DQS
DQ [0:3]
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
DQS
DQS
DQ [0:3]
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
DQS9
DQS9
DQ [4:7]
MEMORY BUFFER
DQS11
DQS11
DQ [20:23]
DQS
DQS
DQ [0:3]
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
DQS
DQS
DQ [0:3
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
DQS
DQS
DQ [0:3]
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
MDQS0
MDQS0
MDQ [0:3]
DQS
DQS
DQ [0:3]
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
MDQS10
MDQS10
MDQ [12:15]
DQS
DQS
DQ [0:3]
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
MDQS1
MDQS1
MDQ [8:11]
DQS
DQS
DQ [0:3
D8
VSS
D34
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
DQS1
DQS1
DQ [8:11]
ODT0 ODT1 CKE0 CKE1
VSS
D7
VDD
CS0 CS1
VSS
D33
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
DQS10
DQS10
DQ [12:15]
ODT0 ODT1 CKE0 CKE1
VSS
D6
VDD
CS0 CS1
VSS
D32
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
DQS0
DQS0
DQ [0:3]
ODT0 ODT1 CKE0 CKE1
VSS
D5
VDD
CS0 CS1
VSS
D31
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS9
MDQS9
MDQ [4:7]
ODT0 ODT1 CKE0 CKE1
VSS
D4
VDD
CS0 CS1
VSS
D30
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS11
MDQS11
MDQ [20:23]
ODT0 ODT1 CKE0 CKE1
VSS
D3
VDD
CS0 CS1
VSS
D29
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS2
MDQS2
MDQ [16:19]
DQS2
DQS2
DQ [16:19]
ODT0 ODT1 CKE0 CKE1
VSS
D2
VDD
CS0 CS1
VSS
D28
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS17
MDQS17
MCB [4:7]
DQS17
DQS17
CB [4:7]
ODT0 ODT1 CKE0 CKE1
VSS
D1
VDD
CS0 CS1
VSS
D27
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS12
MDQS12
MDQ [28:31]
DQS12
DQS12
DQ [28:31]
ODT0 ODT1 CKE0 CKE1
CS0 CS1
ODT0 ODT1 CKE0 CKE1
VSS
ZQ
DQS
DQS
DQ [0:3]
VSS
D35
Notes:
1.
2.
3.
4.
5.
Unless otherwise noted, resistor values are 10 Ohms ±5%.
See the wiring diagrams for all resistors associated with the command, address and control bus.
This Design uses SDRAMz in DDP. There are four ZQ resistors per DDP. The ZQ resistors are 240 Ohms ±1%.
DM pins on SDRAMs are wired to VSS.
The DQ and MDQ labels reflect the byte lanes as defined at the edge connector not which Memory Buffer pins are used.
Rev. 0.3 / Jul. 2013
10
32GB, 4Gx72 Module(4Rank of x4) - page2
QCKE0B
QODT0B
QCKE1B
QODT1B
QCS0B
QCS2B
QCS1B
QCS3B
VDD
CS0 CS1
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS4
MDQS4
MDQ [32:35]
MDQS3
MDQS3
DQ [32:35]
ZQ
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
DQS15
DQS15
DQ [52:55]
MEMORY BUFFER
DQS14
DQS14
DQ [44:47]
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
MDQS6
MDQS6
MDQ [48:51]
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
MDQS16
MDQS16
MDQ [60:63]
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
MDQS7
MDQS7
MDQ [56:59]
CS0 CS1
ZQ
DQS
DQS
DQ [0:3]
VDDSPD
SCL
EVENT
EVENT
A0
A1
A2
SDA
SA0 SA1 SA2
Serial PD w/ stand alone Thermal sensor
Rev. 0.3 / Jul. 2013
ODT0 ODT1 CKE0 CKE1
VSS
D17
DQS
DQS
DQ [0:3
VSS
D25
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
DQS7
DQS7
DQ [56:59]
ODT0 ODT1 CKE0 CKE1
VSS
D16
DQS
DQS
DQ [0:3]
VSS
D24
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
DQS16
DQS16
DQ [60:63]
ODT0 ODT1 CKE0 CKE1
VSS
D15
DQS
DQS
DQ [0:3]
VSS
D23
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
DQS6
DQS6
DQ [48:51]
ODT0 ODT1 CKE0 CKE1
VSS
D14
DQS
DQS
DQ [0:3]
VSS
D22
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS15
MDQS15
MDQ [52:55]
ODT0 ODT1 CKE0 CKE1
VSS
D13
DQS
DQS
DQ [0:3
VSS
D21
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS14
MDQS14
MDQ [44:47]
ODT0 ODT1 CKE0 CKE1
VSS
D12
DQS
DQS
DQ [0:3]
VSS
D20
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS5
MDQS5
MDQ [40:43]
DQS5
DQS5
DQ [40:43]
ODT0 ODT1 CKE0 CKE1
VSS
D2=11
DQS
DQS
DQ [0:3]
VSS
D19
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS8
MDQS8
MCB [0:3]
MDQS8
MDQS8
MCB [0:3]
ODT0 ODT1 CKE0 CKE1
VSS
D10
DQS
DQS
DQ [0:3]
VSS
D18
VDD
ODT0 ODT1 CKE0 CKE1
ZQ
MDQS13
MDQS13
MDQ [36:39]
MDQS13
MDQS13
DQ [36:39]
ODT0 ODT1 CKE0 CKE1
VSS
D9
DQS
DQS
DQ [0:3]
VDD
CS0 CS1
VSS
D26
SPD
VDD
D0–D35
VTT
VREFCA
D0–D35
VREFDQ
D0–D35
VSS
D0–D35
11
32GB, 4Gx72 Module(4Rank of x4) - page3
CS[3:0]
BA[2:0]
A[15:0]
RAS
CAS
WE
CKE[3:0]
ODT[1:0]
M
e
m
o
r
y
B
u
f
f
e
r
CS2A → CS0: SDRAMs D[8:0] CS3A → CS0: SDRAMs D[35:27]
CS0A → CS1: SDRAMs D[8:0] CS1A → CS1: SDRAMs D[35:27]
CS2B → CS0: SDRAMs D[17:9] CS3B → CS0: SDRAMs D[26:18]
CS0B → CS1: SDRAMs D[17:9] CS1B → CS1: SDRAMs D[26:18]
BA[2:0]A → BA[2:0]: SDRAMs D[8:0], D[35:27]
BA[2:0]B → BA[2:0]: SDRAMs D[26:9]
A[15:0]A → A[15:0]: SDRAMs D[8:0], D[35:27]
A[15:0]B → A[15:0]: SDRAMs D[26:9]
RASA → RAS: SDRAMs D[8:0], D[35:27]
RASB → RAS: SDRAMs D[26:9]
CASA → CAS: SDRAMs D[8:0], D[35:27]
CASB → CAS: SDRAMs D[26:9]
WEA → WE: SDRAMs D[8:0], D[35:27]
WEB → We: SDRAMs D[26:9]
CKE2A → CKE0: D[8:0] CKE0A → CKE1: D[8:0]
CKE3A → CKE0: D[26:18] CKE1A → CKE1: D[26:18]
CKE2B → CKE0: D[17:9] CKE0B → CKE1: D[17:9]
CKE3B → CKE0: D[35:27] CKE1B → CKE1: D[35:27]
ODT0A → ODT1: SDRAMs D[8:0]
ODT1A → ODT1: SDRAMs D[35:27]
ODT0B → ODT1: SDRAMs D[17:9]
ODT1B → ODT1: SDRAMs D[26:18]
CK0
CK0 → CK: SDRAMs D[8:0]
CK1 → CK: SDRAMs D[35:27]
CK2 → CK: SDRAMs D[17:9]
CK3 → CK: SDRAMs D[26:18]
CK0
CK0 → CK: SDRAMs D[8:0]
CK1 → CK: SDRAMs D[35:27]
CK2 → CK: SDRAMs D[17:9]
CK3 → CK: SDRAMs D[26:18]
CK1
CK1
PAR_IN
Err_Out
RESET
QRESET: All SDRAMs
1. CK0 and CK0 are terminated with 120 Ohms ±5% resistor.
2. CK1 and CK1 are terminated with 120 Ohms ±5% resistor, but is not used.
3. Unless othersiwe noted resistors are 22 Ohms ±5%
Rev. 0.3 / Jul. 2013
12
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
Voltage on VDD pin relative to Vss
- 0.4 V ~ 1.80 V
V
1,3
Voltage on VDDQ pin relative to Vss
- 0.4 V ~ 1.80 V
V
1,3
V
1
VIN, VOUT Voltage on any pin relative to Vss
TSTG
- 0.4 V ~ 1.80 V
-55 to +100
Storage Temperature
o
C
1, 2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
TOPER
Parameter
Normal Operating Temperature Range
Extended Temperature Range
Rating
Units
Notes
0 to 85
oC
1,2
85 to 95
oC
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).
DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and/or the
DIMM SPD for tREFI requirements in the Extended Temperature Range
Rev. 0.3 / Jul. 2013
13
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
1.45
V
1,2,3,4
1.45
V
1,2,3,4
Min.
Typ.
Max.
Supply Voltage
1.283
1.35
Supply Voltage for Output
1.283
1.35
Notes:
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a
very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).
Recommended DC Operating Conditions - - DDR3 (1.5V) operation
Symbol
VDD
VDDQ
Parameter
Rating
Units
Notes
1.575
V
1,2,3
1.575
V
1,2,3
Min.
Typ.
Max.
Supply Voltage
1.425
1.5
Supply Voltage for Output
1.425
1.5
Notes:
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as
defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).
Rev. 0.3 / Jul. 2013
14
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK,CK#
VDD, VDDQ (DDR3)
tCKSRX
Tmin = 10ns
VDD, VDDQ (DDR3L)
Tmin = 10ns
Tmin = 200us
T = 500us
RESET#
Tmin = 10ns
CKE
VALID
tDLLK
tIS
COMMAND
READ
BA
READ
1)
tXPR
tMRD
tMRD
tMRD
tMOD
MRS
MRS
MRS
MRS
MR2
MR3
MR1
MR0
tZQinit
ZQCL
1)
VALID
VALID
tIS
ODT
READ
tIS
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID
RTT
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied
between MRS and ZQCL commands.
TIME BREAK
DON’T CARE
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
Rev. 0.3 / Jul. 2013
15
Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 21.
Speed Bin
DDR3-800E
CL - nRCD - nRP
6-6-6
Unit
Parameter
Symbol
min
max
Internal read command to first data
tAA
15
20
ns
ACT to internal read or write delay time
tRCD
15
—
ns
PRE command period
tRP
15
—
ns
ACT to ACT or REF command period
tRC
52.5
—
ns
ACT to PRE command period
tRAS
37.5
9 * tREFI
ns
tCK(AVG)
2.5
3.3
ns
CL = 6
CWL = 5
Supported CL Settings
6
nCK
Supported CWL Settings
5
nCK
Rev. 0.3 / Jul. 2013
Notes
1,2,3
16
DDR3-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 21.
Speed Bin
DDR3-1066F
CL - nRCD - nRP
Parameter
Symbol
Unit
7-7-7
min
max
Note
Internal read command to
first data
tAA
13.125
20
ns
ACT to internal read or
write delay time
tRCD
13.125
—
ns
PRE command period
tRP
13.125
—
ns
ACT to ACT or REF
command period
tRC
50.625
—
ns
ACT to PRE command
period
tRAS
37.5
9 * tREFI
ns
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,6
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
ns
1,2,3,4
CWL = 5
tCK(AVG)
ns
4
CWL = 6
tCK(AVG)
ns
1,2,3
CL = 6
CL = 7
CL = 8
1.875
< 2.5
Reserved
1.875
< 2.5
Supported CL Settings
6, 7, 8
nCK
Supported CWL Settings
5, 6
nCK
Rev. 0.3 / Jul. 2013
17
DDR3-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 21.
Speed Bin
DDR3-1333H
CL - nRCD - nRP
Parameter
Symbol
Unit
9-9-9
min
max
Note
Internal read
command to first data
tAA
13.5
(13.125)5,10
20
ns
ACT to internal read or
write delay time
tRCD
13.5
(13.125)5,10
—
ns
PRE command period
tRP
13.5
(13.125)5,10
—
ns
ACT to ACT or REF
command period
tRC
49.5
(49.125)5,10
—
ns
ACT to PRE command
period
tRAS
36
9 * tREFI
ns
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,7
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4,7
CWL = 7
tCK(AVG)
Reserved
ns
4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
ns
1,2,3,4,7
CWL = 7
tCK(AVG)
ns
1,2,3,4
CL = 6
CL = 7
CWL = 5
tCK(AVG)
CWL = 6
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 5, 6
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 5, 6
tCK(AVG)
CWL = 7
tCK(AVG)
1.875
< 2.5
(Optional)5,10
Reserved
ns
4
ns
1,2,3,7
Reserved
ns
1,2,3,4
Reserved
ns
4
ns
1,2,3,4
ns
4
(Optional)
ns
ns
1,2,3
5
Supported CL Settings
6, 7, 8, 9, 10
nCK
Supported CWL Settings
5, 6, 7
nCK
CL = 8
CL = 9
CL = 10
Rev. 0.3 / Jul. 2013
Reserved
1.875
< 2.5
1.5
<1.875
Reserved
1.5
<1.875
18
DDR3-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 21.
Speed Bin
DDR3-1600K
CL - nRCD - nRP
Parameter
Symbol
Unit
11-11-11
min
max
20
ns
Internal read
command to first data
tAA
13.75
(13.125)5,10
ACT to internal read or
write delay time
tRCD
13.75
(13.125)5,10
—
ns
PRE command period
tRP
13.75
(13.125)5,10
—
ns
ACT to ACT or REF
command period
tRC
48.75
(48.125)5,10
—
ns
ACT to PRE command
period
tRAS
35
9 * tREFI
ns
2.5
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 6
tCK(AVG)
CWL = 7
CWL = 5, 6
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 5
CL = 6
CWL = 6
CWL = 7
CL = 7
CWL = 8
CWL = 5
CL = 8
CWL = 6
CWL = 7
CWL = 8
CL = 9
tCK(AVG)
tCK(AVG)
tCK(AVG)
CL = 10 CWL = 7
tCK(AVG)
CWL = 8
CWL = 5, 6,7 tCK(AVG)
CL = 11
tCK(AVG)
CWL = 8
3.3
ns
1,2,3,8
Reserved
ns
1,2,3,4,8
Reserved
ns
4
Reserved
ns
4
1.875
< 2.5
(Optional)
Reserved
ns
1,2,3,4,8
ns
1,2,3,4,8
Reserved
ns
4
Reserved
ns
4
5,10
1.875
< 2.5
ns
1,2,3,8
ns
1,2,3,4,8
Reserved
ns
1,2,3,4
Reserved
ns
4
Reserved
1.5
<1.875
(Optional)
Reserved
ns
1,2,3,4,8
ns
1,2,3,4
Reserved
ns
4
ns
1,2,3,8
Reserved
ns
1,2,3,4
Reserved
ns
4
ns
1,2,3
5,10
CWL = 8
CWL = 5, 6
1.5
<1.875
1.25
<1.5
Supported CL Settings
5, 6, 7, 8, 9, 10, 11
Supported CWL Settings
5, 6, 7, 8
Rev. 0.3 / Jul. 2013
Note
nCK
nCK
19
DDR3-1866 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 21.
Speed Bin
DDR3-1866M
CL - nRCD - nRP
Parameter
Symbol
Internal read command
to first data
tAA
ACT to internal read or
write delay time
tRCD
PRE command period
tRP
ACT to PRE command
period
tRAS
ACT to ACT or PRE
command period
tRC
tCK(AVG)
tCK(AVG)
CWL = 7,8,9 tCK(AVG)
tCK(AVG)
CWL = 5
tCK(AVG)
CWL = 6
CWL = 7,8,9 tCK(AVG)
tCK(AVG)
CWL = 5
tCK(AVG)
CWL = 6
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 8,9
tCK(AVG)
CWL = 5, 6
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 8
tCK(AVG)
CWL = 9
tCK(AVG)
CWL = 5, 6
tCK(AVG)
CWL = 7
tCK(AVG)
CWL = 8
CWL = 5,6,7 tCK(AVG)
tCK(AVG)
CWL = 8
tCK(AVG)
CWL = 9
CWL = 5,6,7,8 tCK(AVG)
tCK(AVG)
CWL = 9
CWL = 5,6,7,8 tCK(AVG)
tCK(AVG)
CWL = 9
CWL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
CL = 12
CL = 13
Unit
13-13-13
min
13.91
max
20
ns
—
ns
—
ns
9 * tREFI
ns
-
ns
(13.125)5,11
13.91
(13.125)5,11
13.91
(13.125)5,11
34
47.91
(47.125)5,11
2.5
CWL = 6
ns
1,2,3,9
Reserved
3.3
ns
1,2,3,4,9
Reserved
ns
4
Reserved
ns
4
ns
1,2,3,4,9
ns
4
1.875
< 2.5
Reserved
Reserved
ns
4
ns
1,2,3,9
Reserved
ns
1,2,3,4,9
Reserved
ns
4
1.875
< 2.5
Reserved
ns
4
ns
1,2,3,4,9
Reserved
ns
1,2,3,4,9
Reserved
ns
4
1.5
<1.875
Reserved
ns
4
ns
1,2,3,9
Reserved
ns
1,2,3,4,9
Reserved
ns
4
1.5
<1.875
1.25
ns
1,2,3,4,9
Reserved
<1.5
ns
1,2,3,4
Reserved
ns
4
Reserved
ns
1,2,3,4
Reserved
ns
4
ns
1, 2, 3
1.07
<1.25
Supported CL Settings
6, 7, 8, 9, 10, 11, 13
Supported CWL Settings
5, 6, 7, 8, 9
Rev. 0.3 / Jul. 2013
Note
nCK
nCK
20
Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.35V +1.000/- 0.067 V);
(TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is
supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
10. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must
be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)
also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
11. DDR3 SDRAM devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin
must be 13.125ns. SPD setting must be programed to match. For example, DDR3-1866 devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for
tAAmin(byte 16), tRCDmin(byte 18) and tRPmin(byte 20) is programmed to 13.125ns, tRCmin(byte
21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin = 34ns +
13.125ns)
Rev. 0.3 / Jul. 2013
21
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls
of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
•
”0” and “LOW” is defined as VIN <= VILAC(max).
•
”1” and “HIGH” is defined as VIN >= VIHAC(max).
•
“MID_LEVEL” is defined as inputs are VREF = VDD/2.
•
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
•
Basic IDD and IDDQ Measurement Conditions are described in Table 2.
•
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
•
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 0.3 / Jul. 2013
22
IDDQ (optional)
IDD
VDD
VDDQ
RESET
CK/CK
DDR3(L)
SDRAM
CKE
CS
RAS, CAS, WE
DQS, DQS
DQ, DM,
TDQS, TDQS
A, BA
ODT
ZQ
VSS
RTT = 25 Ohm
VDDQ/2
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Application specific
memory channel
environment
IDDQ
Test Load
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
Rev. 0.3 / Jul. 2013
23
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol
tCK
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
7-7-7
9-9-9
11-11-11
13-13-13
1.875
1.5
1.25
1.25
Unit
ns
CL
7
9
11
11
nCK
nRCD
7
9
11
11
nCK
nRC
27
33
39
39
nCK
nRAS
20
24
28
28
nCK
nRP
7
9
11
11
nCK
1KB page size
20
20
24
24
nCK
2KB page size
27
30
32
32
nCK
1KB page size
4
4
5
5
nCK
nFAW
nRRD
2KB page size
nRFC -512Mb
6
5
6
6
nCK
48
60
72
72
nCK
nRFC-1 Gb
59
74
88
88
nCK
nRFC- 2 Gb
86
107
128
128
nCK
nRFC- 4 Gb
139
174
208
208
nCK
nRFC- 8 Gb
187
234
280
280
nCK
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
IDD0
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
IDD1
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 0.3 / Jul. 2013
24
Symbol
Description
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2N
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2NT Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
IDD2P0
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
IDD2P1
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)
Precharge Quiet Standby Current
IDD2Q
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD3N
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 5.
Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Rev. 0.3 / Jul. 2013
25
Symbol
Description
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
IDD4R
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
IDD4W
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
IDD5B
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
IDD6
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
IDD6ET
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Rev. 0.3 / Jul. 2013
26
Symbol
Description
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
IDD7
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 0.3 / Jul. 2013
27
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
0
-
0
F
0
-
Cycle
Number
Datab)
Sub-Loop
CKE
CK, CK
Table 3 - IDD0 Measurement-Loop Patterna)
0
3,4
...
nRAS
...
Static High
toggling
1*nRC+0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT
0
0
1
1
0
0
00
0
1*nRC+1, 2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
1*nRC+3, 4
D, D
1
1
1
1
0
0
00
0
0
F
0
-
0
-
...
1*nRC+nRAS
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
...
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
F
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 0.3 / Jul. 2013
28
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
00000000
0
0
0
-
Cycle
Number
Datab)
Sub-Loop
CKE
CK, CK
Table 4 - IDD1 Measurement-Loop Patterna)
0
3,4
...
nRCD
...
nRAS
Static High
toggling
...
repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
00
0
0
F
0
-
1*nRC+1,2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
1*nRC+3,4
...
1*nRC+nRCD
...
1*nRC+nRAS
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
0
F
0
00110011
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
F
...
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
0
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
Rev. 0.3 / Jul. 2013
29
Static High
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
3
D
1
1
1
1
0
0
0
0
0
F
0
-
Cycle
Number
Command
0
toggling
Datab)
Sub-Loop
CKE
CK, CK
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
1
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
8-11
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
12-15
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
16-19
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
20-23
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
24-17
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
28-31
repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Static High
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
3
D
1
1
1
1
0
0
0
0
0
F
0
-
Cycle
Number
Command
0
toggling
Datab)
Sub-Loop
CKE
CK, CK
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
1
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2
8-11
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3
12-15
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4
16-19
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5
20-23
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6
24-17
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7
28-31
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 0.3 / Jul. 2013
30
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
RD
0
1
0
1
0
0
00
0
0
0
0
00000000
1
D
1
0
0
0
0
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
0
0
00
0
0
0
0
-
4
RD
0
1
0
1
0
0
00
0
0
F
0
00110011
D
1
0
0
0
0
0
00
0
0
F
0
-
D,D
1
1
1
1
0
0
00
0
0
F
0
-
Cycle
Number
Datab)
Sub-Loop
CKE
CK, CK
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
0
Static High
toggling
5
6,7
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
0,
0,
0,
0,
0,
0,
0,
1
1
1
1
1
1
=
=
=
=
=
=
=
A[2:0]
ODT
0
0
1
0
0
1
BA[2:0]
BA[2:0]
BA[2:0]
BA[2:0]
BA[2:0]
BA[2:0]
BA[2:0]
A[6:3]
0
0
1
0
0
1
but
but
but
but
but
but
but
WE
CAS
RAS
CS
0
1
1
0
1
1
0
1
1
0
1
1
Sub-Loop
Sub-Loop
Sub-Loop
Sub-Loop
Sub-Loop
Sub-Loop
Sub-Loop
A[9:7]
WR
D
D,D
WR
D
D,D
repeat
repeat
repeat
repeat
repeat
repeat
repeat
A[10]
1
2
3
4
5
6
7
1
2,3
4
5
6,7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
A[15:11]
0
BA[2:0]
0
Command
Cycle
Number
Sub-Loop
CKE
Static High
toggling
CK, CK
Table 8 - IDD4W Measurement-Loop Patterna)
Datab)
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
00110011
-
1
2
3
4
5
6
7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 0.3 / Jul. 2013
31
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
0
REF
0
0
0
1
0
0
0
0
0
0
0
-
1
1.2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
Cycle
Number
Datab)
Sub-Loop
CKE
CK, CK
Table 9 - IDD5B Measurement-Loop Patterna)
3,4
Static High
toggling
5...8
2
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
33...nRFC-1
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 0.3 / Jul. 2013
32
Table 10 - IDD7 Measurement-Loop Patterna)
2
3
4
Static High
5
6
7
8
9
10
4*nRRD
nFAW
nFAW+nRRD
nFAW+2*nRRD
nFAW+3*nRRD
nFAW+4*nRRD
2*nFAW+0
2*nFAW+1
2&nFAW+2
11
2*nFAW+nRRD
2*nFAW+nRRD+1
2&nFAW+nRRD+2
12
13
2*nFAW+2*nRRD
2*nFAW+3*nRRD
14
2*nFAW+4*nRRD
15
16
17
18
3*nFAW
3*nFAW+nRRD
3*nFAW+2*nRRD
3*nFAW+3*nRRD
19
3*nFAW+4*nRRD
00110011
-
0
-
0
-
0
0
0
00110011
-
0
0
0
00000000
-
0
-
0
-
A[10]
0
0
0
ODT
00000000
-
WE
0
0
0
CAS
ACT
0
0
1
1
0
0
00
0
0
0
RDA
0
1
0
1
0
0
00
1
0
0
D
1
0
0
0
0
0
00
0
0
0
repeat above D Command until nRRD - 1
ACT
0
0
1
1
0
1
00
0
0
F
RDA
0
1
0
1
0
1
00
1
0
F
D
1
0
0
0
0
1
00
0
0
F
repeat above D Command until 2* nRRD - 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
D
1
0
0
0
0
3
00
0
0
F
Assert and repeat above D Command until nFAW - 1, if necessary
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 1, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 1, but BA[2:0] = 7
0
0
7
00
0
0
F
D
1
0
0
Assert and repeat above D Command until 2* nFAW - 1, if necessary
ACT
0
0
1
1
0
0
00
0
0
F
RDA
0
1
0
1
0
0
00
1
0
F
D
1
0
0
0
0
0
00
0
0
F
Repeat above D Command until 2* nFAW + nRRD - 1
ACT
0
0
1
1
0
1
00
0
0
0
RDA
0
1
0
1
0
1
00
1
0
0
D
1
0
0
0
0
1
00
0
0
0
Repeat above D Command until 2* nFAW + 2* nRRD - 1
repeat Sub-Loop 10, but BA[2:0] = 2
repeat Sub-Loop 11, but BA[2:0] = 3
D
1
0
0
0
0
3
00
0
0
0
Assert and repeat above D Command until 3* nFAW - 1, if necessary
repeat Sub-Loop 10, but BA[2:0] = 4
repeat Sub-Loop 11, but BA[2:0] = 5
repeat Sub-Loop 10, but BA[2:0] = 6
repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
0
Assert and repeat above D Command until 4* nFAW - 1, if necessary
RAS
Datab)
CS
A[9:7]
A[15:11]
BA[2:0]
Command
A[2:0]
1
0
1
2
...
nRRD
nRRD+1
nRRD+2
...
2*nRRD
3*nRRD
A[6:3]
0
toggling
Cycle
Number
Sub-Loop
CKE
CK, CK
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 0.3 / Jul. 2013
33
IDD Specifications (Tcase: 0 to 95oC)
*Module IDD values in the datasheet are only a calculation based on the component IDD spec and register
power. The actual measurements may vary according to DQ loading cap.
32GB, 4G x 72 LR-DIMM: HMT84GL7AMR4A
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
Montage(C1)
DDR3L 1333
DDR3L 1600
3662
3808
3788
3934
3374
3520
3662
3808
946
1020
1090
1164
3446
3520
4022
4168
1594
1740
4436
4744
4526
4834
6686
6814
1234
1308
1522
1596
5426
5644
Inphi(GS02B)
DDR3L 1333
DDR3L 1600
4169
4349
4295
4475
3881
4061
4169
4349
1527
1633
1671
1777
3953
4061
4529
4709
2175
2353
4943
5285
5033
5375
7193
7355
1815
1921
2103
2209
5933
6185
Unit note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
32GB, 4G x 72 LR-DIMM: HMT84GL7AMR4C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
Montage(C1)
Inphi(GS02B)
Unit note
DDR3 1333 DDR3 1600 DDR3 1866 DDR3 1333 DDR3 1600 DDR3 1866
4213
4351
4490
4855
5045
4949
mA
4339
4495
4652
4981
5189
5111
mA
3907
4045
4184
4549
4739
4643
mA
4195
4405
4544
4837
5099
5003
mA
1192
1259
1292
1873
1997
2198
mA
1336
1403
1508
2017
2141
2414
mA
3979
4117
4112
4624
4811
4571
mA
4555
4765
4904
5197
5459
5363
mA
1840
1979
2012
2521
2717
2918
mA
5077
5377
5768
5719
6071
6227
mA
5167
5467
5858
5809
6161
6317
mA
7147
7267
7388
7789
7961
7847
mA
1480
1547
1580
2161
2285
2486
mA
1768
1835
1868
2249
2573
2774
mA
6157
6367
6668
6799
7061
7127
mA
Rev. 0.3 / Jul. 2013
34
Module Dimensions
4Gx72 - HMT84GL7AMR4A(C)
Front
133.35
128.95
Detail B
Detail A
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
1
9.50
17.30
23.30
Memory
Buffer
4X3.00±0.10
120
1
2X3.00±0.10
47.00
Detail C
5.175
71.00
5.0 Detail D
Back
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
121
240
1
Side
Detail of Contacts A
Detail of Contacts D
Detail of Contacts C
Detail of Contacts B
1.20± 0.15
4.53mm max
0.80± 0.05
2.50
14.90
2.50±0.20
0.3 ±0.15
0.20
2.50±0.20
13.60
3± 0.1
3.80
0.4
0.3~0.1
1.00
1.50 ±0.10
5.00
1.27±010mm
max
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 0.3 / Jul. 2013
35
30.00
2.10±0.15
4Gx72 - HMT84GL7AMR4A(C) - Heat Spreader
Front
133.4
126.4
42.3
7.2
25.00
14
30.20
7.4
3.1
11
17.0
Registering
Clock Driver
7.9
11.4
2.786
26.1
5.1
16
120
1
34
76.6
69.25
119.64
Registering
Clock Driver
Back
1
120
Side
7.65mm max
Note:
1. 0.13 tolerance on all dimensions unless otherwise stated.
2.In order to uninstall FDHS, please contact sales administrator.
Rev. 0.3 / Jul. 2013
1.27±010mm
max
Units: millimeters
36