Datasheet
Serial EEPROM Series Automotive EEPROM
105℃ Operation I2C BUS EEPROM (2-Wire)
BR24Axxx-WM
(1K 2K 4K 8K 16K 32K 64K)
●General Description
BR24Axxx-WM is a serial EEPROM of I2C BUS interface method.
●Packages W(Typ.) x D(Typ.) x H(Max.)
●Features
2
Completely conforming to the world standard I C BUS.
All controls available by 2 ports of serial clock
(SCL) and serial data (SDA)
Wide temperature range -40℃ to +105℃
Other devices than EEPROM can be connected to
the same port, saving microcontroller port
2.5V to 5.5V single power source operation most
suitable for battery use
Page write mode useful for initial value write at
factory shipment
Auto erase and auto end function at data rewrite
Low current consumption
*1
¾
At write operation (5V)
: 1.2mA (Typ.)
¾
At read operation (5V)
: 0.2mA (Typ.)
¾
At standby condition (5V) : 0.1μA (Typ.)
Write mistake prevention function
¾ Write (write protect) function added
¾ Write mistake prevention function at low voltage
Data rewrite up to 1,000,000 times(Ta≦25℃）
Data kept for 40 years(Ta≦25℃）
Noise filter built in SCL / SDA terminal
Shipment data all address FFh
SOP8
5.00mm x 6.20mm x 1.71mm
SOP- J8
4.90mm x 6.00mm x 1.65mm
MSOP8
2.90mm x 4.00mm x 0.90mm
*1 BR24A32-WM, BR24A64-WM : 1.5mA
AEC-Q100 Qualified
●Page write
Number of Pages
8Byte
16Byte
32Byte
Product
number
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
●BR24Axxx-WM
Capacity
Bit format
1Kbit
128×8
2Kbit
256×8
4Kbit
512×8
8Kbit
1K×8
16Kbit
2K×8
32Kbit
4K×8
64Kbit
8K×8
Type
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
○Product structure: Silicon monolithic integrated circuit
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©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･14･001
Power source voltage
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
SOP8
●
●
●
●
●
●
●
SOP-J8
●
●
●
●
●
MSOP8
●
○This product is not designed protection against radioactive rays
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TSZ02201-0R1R0G100140-1-2
6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Absolute Maximum Ratings (Ta=25℃)
Parameter
Symbol
Ratings
Unit
Supply Voltage
VCC
-0.3 to +6.5
V
Power Dissipation
Pd
0.45 (SOP-J8)
0.45 (SOP8)
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
W
0.31 (MSOP8)
When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
Storage Temperature
Tstg
-65 to +125
℃
Operating Temperature
Topr
-40 to +105
℃
‐
-0.3 to VCC+1.0
V
Terminal Voltage
Remarks
●Memory cell characteristics (VCC=2.5V to 5.5V)
Parameter
Number of data rewrite times *1
Data hold years *1
Min.
1,000,000
100,000
40
10
Limits
Typ.
-
Max
-
Unit
Times
Years
Conditions
Ta≦25℃
Ta≦105℃
Ta≦25℃
Ta≦105℃
○Shipment data all address FFh
*1Not 100% TESTED
●Recommended Operating Ratings
Parameter
Symbol
Power source voltage
VCC
Input voltage
VIN
●Electrical characteristics
Parameter
“HIGH” input voltage
“LOW” input voltage
“LOW” output voltage 1
Input leak current
Output leak current
Current consumption
Standby current
Ratings
2.5 to 5.5
0 to VCC
Unit
V
(Unless otherwise specified, Ta=-40℃ to +105℃, VCC=2.5V to 5.5V)
Limits
Symbol
Unit
Conditions
Min.
Typ.
Max.
VIH
0.7 VCC
V
VIL
0.3 VCC
V
VOL
0.4
V
IOL=3.0mA (SDA)
ILI
-1
1
μA
VIN=0V to VCC
ILO
-1
1
μA
VOUT=0V to VCC, (SDA)
2.0 *1
VCC =5.5V,fSCL=400kHz, tWR=5ms,
ICC1
mA
Byte write, Page write
3.0 *2
VCC =5.5V,fSCL=400kHz
ICC2
0.5
mA
Random read, current read, sequential read
VCC =5.5V, SDA・SCL= VCC
ISB
2.0
μA
A0, A1, A2=GND, WP=GND
*1 BR24A01A/02/04/08/16-WM, *2 BR24A32/64-WM
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TSZ22111・15・001
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TSZ02201-0R1R0G100140-1-2
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Operating timing characteristics
(Unless otherwise specified, Ta=-40℃ to +105℃, VCC=2.5V to 5.5V)
STANDARD-MODE
FAST-MODE
2.5V≦VCC≦5.5V
2.5V≦VCC≦5.5V
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
SCL frequency
fSCL
400
100
Data clock “HIGH“ time
tHIGH
0.6
4.0
Data clock “LOW“ time
tLOW
1.2
4.7
SDA, SCL rise time *1
tR
0.3
1.0
SDA, SCL fall time *1
tF
0.3
0.3
Start condition hold time
tHD:STA
0.6
4.0
Start condition setup time
tSU:STA
0.6
4.7
Input data hold time
tHD:DAT
0
0
Input data setup time
tSU:DAT
100
250
Output data delay time
tPD
0.1
0.9
0.2
3.5
Output data hold time
tDH
0.1
0.2
Stop condition setup time
tSU:STO
0.6
4.7
Bus release time before transfer start
tBUF
1.2
4.7
Internal write cycle time
tWR
5
5
Noise removal valid period (SDA, SCL terminal)
tI
0.1
0.1
WP hold time
tHD:WP
0
0
WP setup time
tSU:WP
0.1
0.1
WP valid time
tHIGH:WP
1.0
1.0
-
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
*1 Not 100% tested
●FAST-MODE and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same operations, and mode is changed. They are distinguished by operating
speeds. 100kHz operation is called STANDARD-MODE, and 400kHz operation is called FAST-MODE. This operating
frequency is the maximum operating frequency, so 100kHz clock may be used in FAST-MODE. At VCC =2.5V to 5.5V,
400kHz, namely, operation is made in FASTMODE. (Operation is made also in STANDARD-MODE.)
●Sync Data Input / Output Timing
tR
tF
tHIGH
SCL
SCL
tSU:DAT
tHD:STA
tLOW
tHD:DAT
tSU:STA
SDA
(入力)
(input)
tPD
tBUF
tHD:STA
tSU:STO
SDA
tDH
SDA
(出力)
(output)
START BIT
STOP BIT
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Figure 1-(a) Sync data input / output timing
Figure 1-(b) Start-stop bit timing
SCL
DATA(1)
SCL
SDA
D1
D0
DATA(n)
ACK
ACK
ｔWR
SDA
D0
ACK
ｔWR
Write data
(n-th address)
Stop condition
Stop condition
ストップコンディション
WP
Start condition
ｔHD：WP
tSU：WP
Figure 1-(c) Write cycle timing
Figure 1-(d) WP timing at write execution
SCL
DATA(n)
DATA(1)
SDA
D1
D0
ACK
ACK
tHIGH:WP
tWR
WP
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
Figure 1-(e) WP timing at write cancel
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TSZ22111・15・001
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TSZ02201-0R1R0G100140-1-2
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Block Diagram
*2
A0
1Kbit to 64Kbit EEPROM array
1
8
Vcc
7
WP
6
SCL
5
SDA
*1
7bit 11bit
8bit 12bit
9bit 13bit
10bit
*2
A1
2
A2
3
Address
decoder
8bit
*1
7bit 11bit
8bit 12bit
9bit 13bit
10bit
START
*2
Data
register
Slave - word
address register
STOP
Control circuit
ACK
GND
High voltage
generating circuit
4
*1
7bit : BR24A01A-WM
8bit : BR24A02-WM
9bit : BR24A04-WM
Power source
voltage detection
*
10bit : BR24A08-WM
11bit : BR24A16-WM
12bit : BR24A32-WM
13bit : BR24A64-WM
2
A0=N.C.
A0, A1=N.C.
A0, A1= N.C. A2=Don’t Use
: BR24A04-WM
: BR24A08-WM
: BR24A16-WM
●Pin Configuration
(TOP VIEW)
A0
1
A1
2
A2
3
GND
4
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
8
Vcc
7
WP
6
SCL
5
SDA
●Pin Descriptions
Function
Terminal
name
Input /
output
A0
Input
A1
Input
A2
Input
GND
-
Reference voltage of all input / output, 0V
SDA
Input /
output
Slave and word address, Serial data input serial data output
SCL
Input
Serial clock input
WP
Input
Write protect terminal
Vcc
-
Connect the power source.
BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM
Slave address setting
Not connected
Slave address setting
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TSZ22111・15・001
Slave address setting
Not connected
Slave address setting
Slave address setting
Not used
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Slave address setting
TSZ02201-0R1R0G100140-1-2
6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
6
6
5
5
4
4
SPEC
3
VIL[V]
VIH[V]
●Typical Performance Curves
(The following values are Typ. ones.)
2
3
2
Ta=105℃
Ta=-40℃
Ta=25℃
1
Ta=105℃
Ta=-40℃
Ta=25℃
1
SPEC
0
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Figure 3. L input voltageVIL1,2
(SCL,SDA,WP)
Figure 2. H input voltage VIH1,2
(SCL,SDA,WP)
1
1.2
0.8
1.0
ILI[μA]
SPEC
VOL1[V]
0.6
SPEC Ta=105℃
0.4
Ta=25℃
0.8
0.6
0.4
0.2
Ta=105℃
Ta=25℃
Ta=-40℃
0.2
Ta=-40℃
0
0
0
1
2
3
4
5
6
0
IOL1[mA]
Figure 4. L output voltage VOL1-IOL1
(VCC =2.5V)
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
1
2
3
Vcc[V]
4
5
6
Figure 5. Input leak current ILI (SCL,WP)
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TSZ02201-0R1R0G100140-1-2
6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Typical Performance Curves‐Continued
1.2
2.5
[BR24A01A/02/04/08/16-WM]
SPEC
1
2.0
fSCL=400kHz SPEC
DATA=AAh
ICC1[mA]
ILO[μA]
0.8
0.6
0.4
Ta=105℃
Ta=25℃
Ta=-40℃
0.2
1.5
1.0
Ta=25℃
Ta=105℃
Ta=-40℃
0.5
0
0
0
1
2
3
Vcc[V]
4
5
0
6
1
2
4
5
6
Vcc[V]
Figure 7. Current consumption at WRITE operation
ICC1 (fSCL=400kHz)
Figure 6. Output leak current ILO(SDA)
3.5
0.6
[BR24A32/64-WM]
SPEC
3.0
fSCL=400kHz
DATA=AAh
2.5
0.5
SPEC
fSCL=400kHz
DATA=AAh
0.4
ICC2[mA]
ICC1[mA]
3
2.0
1.5
Ta=105℃
0.3
Ta=25℃
0.2
1.0
Ta=25℃
Ta=105℃
Ta=-40℃
0.5
Ta=-40℃
0.1
0
0
0
1
2
3
Vcc[V]
4
5
6
1
2
3
4
5
6
Vcc[V]
Figure 8. Current consumption at WRITE operation
ICC1 (fSCL=400kHz)
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TSZ22111・15・001
0
6/28
Figure 9. Current consumption at READ operation
ICC2 (fSCL=400kHz)
TSZ02201-0R1R0G100140-1-2
6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Typical Performance Curves‐Continued
3.5
2.5
[BR24A32/64-WM]
[BR24A01A/02/04/08/16-WM]
3.0
fSCL=100kHz
DATA=AAh
2.0
SPEC
2.5
ICC1[mA]
ICC1[mA]
fSCL=100kHz
DATA=AAh
1.5
1.0
2.0
1.5
1.0
Ta=25℃
Ta=105℃
Ta=-40℃
0.5
Ta=25℃
Ta=105℃
Ta=-40℃
0.5
0
0
0
1
2
3
4
5
0
6
1
2
3
4
5
6
Vcc[V]
Vcc[V]
Figure 10. Current consumption at WRITE operation
ICC1 (fSCL=100kHz)
Figure 11. Current consumption at WRITE operation
ICC1 (fSCL=100kHz)
0.6
2.5
SPEC
SPEC
0.5
2.0
fSCL=100kHz
DATA=AAh
0.4
ISB[μA]
ICC2[mA]
SPEC
0.3
1.0
Ta=105℃
0.2
1.5
Ta=25℃
Ta=105℃
0.5
0.1
Ta=-40℃
Ta=-40℃
Ta=25℃
0
0
0
1
2
3
4
5
0
6
2
3
4
5
6
Vcc[V]
Vcc[V]
Figure 12. Current consumption at READ operation
ICC2 (fSCL=100kHz)
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TSZ22111・15・001
1
Figure 13. Standby current
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ISB
TSZ02201-0R1R0G100140-1-2
6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Typical Performance Curves‐Continued
10000
5
SPEC2
fSCL[kHz]
1000
Ta=105℃
Ta=25℃
Ta=-40℃
tHIGH [μs]
4
SPEC1
100
SPEC2
3
2
10
Ta=-40℃
Ta=25℃
Ta=105℃ SPEC1
1
0
1
0
Vcc[V]
3
Vcc[V]
Figure 14. SCL frequency fSCL
Figure 15. Data clock "H" time tHIGH
1
2
3
4
5
0
6
5
1
4
5
6
5
SPEC2
SPEC2
4
4
tHD:STA[μs]
tLOW[μs]
2
3
2
3
2
Ta=105℃
Ta=25℃
Ta=-40℃
1
SPEC1
Ta=105℃
Ta=25℃
Ta=-40℃
1
0
SPEC1
0
0
1
2
3
4
5
6
Vcc[V]
3
Vcc[V]
Figure 16. Data clock "L" time tLOW
Figure 17. Start condition hold time tHD:STA
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1
2
4
5
6
TSZ02201-0R1R0G100140-1-2
6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Typical Performance Curves‐Continued
50
6
tHD:DAT(HIGH)[ns]
tSU:STA[μs]
SPEC1, 2
SPEC2
5
4
3
2
Ta=-40℃
Ta=25℃
Ta=105℃
1
0
Ta=-40℃
Ta=25℃
Ta=105℃
-50
-100
-150
SPEC1
-200
0
0
1
2
3
Vcc[V]
4
5
0
6
Figure 18. Start condition setup time tSU:STA
1
3
Vcc[V]
4
5
6
Figure 19. Input data hold time tHD:DAT(HIGH)
50
300
tSU:DAT(HIGH)[ns]
SPEC1, 2
0
tHD:DAT(LOW)[ns]
2
-50
Ta=105℃
Ta=25℃
-100
SPEC2
200
SPEC1
100
0
Ta=105℃
Ta=25℃
Ta=-40℃
-100
-150
Ta=-40℃
-200
-200
0
1
2
3
Vcc[V]
Figure 20. Input data hold time
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TSZ22111・15・001
4
5
0
6
tHD:DAT(LOW)
1
2
3
Vcc[V]
4
5
6
Figure 21. Input data setup time tSU:DAT(HIGH)
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TSZ02201-0R1R0G100140-1-2
6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Typical Performance Curves‐Continued
4
SPEC2
200
SPEC
2
3
tPD0[μs]
tSU:DAT(LOW)[ns]
300
SPEC1
100
2
Ta=105℃
0
-100
1
Ta=-40℃
Ta=25℃
Ta=105
Ta=25
℃
Ta=-40
℃
℃
SPEC
2
SPEC
1
-200
0
0
1
2
3
Vcc[V]
4
5
6
0
Figure 22. Input data setup time tSU:DAT(LOW)
1
2
SPEC
1
3
Vcc[V
]
4
5
6
Figure 23. Output data delay time tPD0
5
4
SPEC2
tBUF[μs]
3
tPD1[μs]
4
SPEC2
2
Ta=-40℃
Ta=25℃
Ta=105℃
1
3
2
SPEC1
1
SPEC2
Ta=-40℃
Ta=25℃
Ta=105℃
SPEC1
1
3
Vcc[V]
SPEC1
0
0
0
1
2
3
Vcc[V]
4
Figure 24. Output data delay time
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TSZ22111・15・001
5
6
0
2
4
5
6
Figure 25. Bus release time before transfer start tBUF
tPD1
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TSZ02201-0R1R0G100140-1-2
6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Typical Performance Curves‐Continued
0.6
6
SPEC1, 2
0.5
5
tWR[ms]
tI(SCL H)[μs]
Ta=25℃
4
Ta=-40℃
3
Ta=105℃
0.4
Ta=-40℃
Ta=25℃
0.3
2
0.2
1
0.1
0
0
Ta=105℃
SPEC1, 2
0
1
2
3
Vcc[V]
4
0
6
0.6
0.6
0.5
0.5
0.4
0.4
0.3
Ta=-40℃
0.2
1
Ta=25℃
3
Vcc[V]
4
5
6
Ta=105℃
0.2
SPEC1, 2
0.1
SPEC1
0
Ta=-40℃
Ta=25℃
0.3
Ta=105℃
0.1
2
Figure 27. Noise removal valid time tI(SCL H)
tWR
tI(SDA H)[μs]
tI(SCL L)[μs]
Figure 26. Internal write cycle time
5
0
0
1
2
3
Vcc[V]
4
5
6
0
2
3
Vcc[V]
4
5
6
Figure 29. Noise removal valid time tI(SDA H)
Figure 28. Noise removal valid time tI(SCL L)
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1
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TSZ02201-0R1R0G100140-1-2
6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Typical Performance Curves‐Continued
0.6
tSU:WP[μs]
tI(SDA L)[μs]
0.5
0.4
Ta=-40℃
0.3
Ta=25℃
SPEC1, 2
0
-0.2
Ta=105℃
0.2
Ta=105℃
Ta=25℃
-0.4
SPEC1
0.1
Ta=-40℃
0
-0.6
0
1
2
3
4
5
6
0
Vcc[V]
1
2
3
Vcc[V]
4
Figure 31. WP setup time
Figure 30. Noise removal valid time tI(SDA L)
5
6
tSU:WP
1.2
tHIGH:WP[μs]
1
SPEC1, 2
0.8
0.6
0.4
Ta=-40℃
Ta=25℃
Ta=105℃
0.2
0
0
1
2
3
Vcc[V]
4
5
6
Figure 32. WP valid time tHIGH:WP
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●I2C BUS Communication
2
○I C BUS data communication
2
I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and
2
acknowledge is always required after each byte. I C BUS carries out data transmission with plural devices connected by
2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
1-7
SCL
S
START ADDRESS
condition
8
9
R/W
ACK
1-7
8
DATA
9
ACK
1-7
8
DATA
9
ACK
P
STOP
condition
Figure 33. Data transfer timing
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL
is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition
is satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data
output of readcommand) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write operation outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write
data).
・Each read operation outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this
IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop condition (stop bit), and ends read operation. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read operation, and is
as shown below.
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
Type
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
Slave address
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
A2
A2
A2
A2
P2
A2
A2
A1
A1
A1
P1
P1
A1
A1
A0
A0
PS
P0
P0
A0
A0
―
R/W
―
R/W
―
R/W
―
R/W
―
R/W
―
R/W
―
R/W
Maximum number of
connected buses
8
8
4
2
1
8
8
A0
1
A1
2
A2
3
GND
4
1
1
1
1
8 Vcc
1
BR24A01A-WM
BR24A02-WM
7 WP
BR24A04-WM
1
BR24A08-WM
6 SCL
BR24A16-WM
1
BR24A32-WM
BR24A64-WM
5 SDA
1
PS, P0 to P2 are page select bits.
Note) Up to 4 units BR24A04-WM, up to 2 units of BR24A08-WM, and one unit of BR24A16-WM can be connected.
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24A32 / A64-WM)
S
T
A
R
T
SLAVE
ADDRESS
SDA
LINE
W
R
I
T
E
WORD
ADDRESS
WA
7
1 0 1 0 A2 A1 A0
Note)
S
T
O
P
DATA
WA
0
D7
D0
A
C
K
R A *1
/ C
W K
*1 As for WA7, BR24A01A-WM becomes Don’t care.
A
C
K
Figure 34. Byte write cycle (BR24A01A/02/04/08/16-WM)
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1 0 A2 A1 A0
*
*
*
R A
/ C
W K
Note)
2nd WORD
ADDRESS
1st WORD
ADDRESS
WAWA
12 11
DATA
WA
0
D0
D7
A
C
K
A
C
K
*1
S
T
O
P
*1 As for WA12, BR24A32-WM becomes Don’t care.
A
C
K
Figure 35. Byte write cycle (BR24A32/64-WM)
S
T
A
R
T
SDA
L IN E
W
R
I
T
E
SLAVE
ADDRESS
1 st W O R D
A D D R E S S (n )
WA WA
1 0 1 0 A 2A 1A 0
*
*
R A
/ C
W K
N ote )
2nd W ORD
A D D R E S S (n )
*
WA
0
1 2 11
A
C
K
*1
Figure 36. Page write cycle
S
T
A
R
T
SDA
L IN E
SLAVE
ADDRESS
1 0 1 0 A 2A 1A 0
N o te )
W
R
I
T
E
D A T A (n )
R A
/ C *1
W K
Figure 37. Page write cycle
D0
D0
A
C
K
A
C
K
*1 As for WA7, BR24A01A-WM becomes Don’t care.
*2 As for BR24A01A/02-WM become (n+7).
(BR24A01A/02/04/08/16-WM)
W ORD
A D D R E S S (n )
WA
7
D7
A
C
K
S
T
O
P
D A TA (n + 3 1 )
D A TA (n )
WA
0
D7
A
C
K
D A TA (n +1 5 )
D0
S
T
O
P
*2
*1 As for WA12, BR24A32-WM becomes Don’t care.
D0
A
C
K
A
C
K
(BR24A32/64-WM)
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24A01A-WM, BR24A02-WM）
: Up to 16bytes (BR24A04-WM, BR24A08-WM,BR24A16-WM）
: Up to 32bytes (BR24A32-WM, BR24A64-WM
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" in Page 15.)
・As for page write cycle of BR24A01A-WM and BR24A02-WM, after the significant 5 bits (4 significant bits in
BR24A01A-WM) of word address are designated arbitrarily, and as for page write command of BR24A04-WM,
BR24A08-WM, and BR24A16-WM, after page select bit (PS) of slave address is designated arbitrarily, by continuing data
input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in BR24A01A-WM, and BR24A02-WM) is
incremented internally, and data up to 16 bytes (up to 8 bytes in BR24A01A-WM and BR24A02-WM) can be written.
・As for page write cycle of BR24A32-WM and BR24A64-WM, after the significant 7 bits (in the case of BR24A32-WM) of
word address, or the significant 8 bits (in the case of BR24A64-WM) of word address are designated arbitrarily, by continuing data
input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
Note)
*1 *2 *3
1 0 1 0 A 2A 1A 0
*1
*2
*3
In BR24A16-WM, A2 becomes P2.
In BR24A08-WM, BR24A16-WM, A1 become P1.
In BR24A04-WM, A0 becomes PS, and in
BR24A08-WM and
Figure 38. Difference of slave address of each
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
○Notes on write cycle continuous input
At STOP (stop bit),
write starts.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
*1
WA
7
1 0 1 0 A2A1A0
Note)
WORD
ADDRESS（ｎ）
R A
/ C
W K
*2
DATA(n)
WA
0
S
T
O
P
DATA(n+7)*3
D7
D0
A
C
K
S
T
A
R
T
D0
A
C
K
1 0 1 0
A
C
K
tWR(maximum : 5ms)
Command is not accepted for this period.
Figure 39. Page write cycle
*1
*2
*3
BR24A01A-WM becomes Don’t care.
BR24A04-WM, BR24A08-W, and BR24A16-WM become (n+15).
BR24A32-WM and BR24A64-WM become (n+31).
*1
*2
*3
In BR24A16-WM, A2 becomes P2.
In BR24A08-WM, BR24A16-WM, A1 become P1.
In BR24A04-WM, A0 becomes PS, and in
BR24A08-WM and in BR24A16-WM, A0 becomes P0.
Note)
*1 *2 *3
1 0 1 0 A 2A 1A 0
Next command
Figure 40. Difference of each type of slave address
○Notes on page write cycle
List of numbers of page write
Number of Pages
8Byte
Product
number
16Byte
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A01A-WM
BR24A02-WM
32Byte
BR24A32-WM
BR24A64-WM
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
In the case BR24A02-WM, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write.
It does not stand 5ms at maximum × 8byte=40ms(Max.).
○Internal address increment
Page write mode (in the case of BR24A02-WM)
WA7 ----0
----0
----0
-----
WA4
0
0
0
-------------
0
0
0
WA1
0
0
1
WA0
0
1
0
Increment
---------
0
0
0
WA2
0
0
0
---------
---------
06h
WA3
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
Significant bit is fixed.
No digit up
For example, when it is started from address 06h, therefore, increment is made as below,
06h → 07h → 00h → 01h ---, which please note.
*06h･･･06 in hexadecimal, therefore, 00000110 becomes a binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set VCC (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of
all address is enabled. Be sure to connect this terminal to VCC or GND, or control it to H level or L level. Do not use it open.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be
read in succession.
S
T
A
R
T
W
R
I
T
E
SLAVE
ADDRESS
SDA
L IN E
S
T
A
R
T
W ORD
A D D R E S S (n )
WA
7
1 0 1 0 A 2 A 1A 0
WA
0
R A *1
/ C
W K
N o te )
R
E
A
D
SLAVE
ADDRESS
D A TA (n )
1 0 1 0 A 2 A 1A 0
A
C
K
It is necessary to input 'H' to
the last ACK.
S
T
O
P
D0
D7
A
C
K
R A
/ C
W K
*1 As for WA7, BR24A01A-WM become Don’t care.
Figure 41. Random read cycle (BR24A01A/02/04/08/16-WM)
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
W
R
I
T
E
* * *
WA
0
WAWA
12 11
R A
/ C
W K
Note)
2nd WORD
ADDRESS（ｎ）
1st WORD
ADDRESS（ｎ）
1 0 1 0 A2A1A0
S
T
A
R
T
A
C
K
*1
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2 A1A0
A
C
K
S
T
O
P
DATA(n)
D7
D0
R A
/ C
W K
A
C
K
*1 As for WA12, BR24A32-WM become Don’t care.
Figure 42. Random read cycle (BR24A32/64 -WM)
S
T
A
R
T
SDA
L IN E
R
E
A
D
S LA V E
ADDRESS
S
T
O
P
D A TA (n )
1 0 1 0 A 2 A 1A 0
D7
D0
A
C
K
R A
/ C
W K
N o te)
It is necessary to input 'H' to
the last ACK.
Figure 43. Current read cycle
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2 A1A0
Note）
D7
S
T
O
P
DATA(n+x)
DATA(n)
D0
R A
/ C
W K
D7
A
C
K
D0
A
C
K
A
C
K
Figure 44. Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
*1 *2 *3
1 0 1 0 A 2A 1A 0
*1
In BR24A16-WM, A2 becomes P2.
*2
In BR24A08-WM, BR24A16-WM, A1 become P1.
*3
In BR24A04-WM, A0 becomes PS, and in BR24A08-WM
Figure 45. Difference of slave address of each type
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and BR24A16-WM, A0 becomes P0.
TSZ02201-0R1R0G100140-1-2
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Figure 46(a), Figure 46(b), and Figure 46(c).)
In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'
level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.
Start×2
Dummy clock×14
SCL
2
1
13
Normal command
14
SDA
Normal command
Figure 46-(a) The case of dummy clock +START+START+ command input
SCL
Start
Dummy clock×9
Start
1
2
8
Normal command
9
SDA
Normal command
Figure 46-(b) The case of START +9 dummy clocks +START+ command input
Start×9
SCL
2
1
7
3
8
Normal command
9
SDA
Normal command
Figure 46-(c) START×9+ command input
※
タ
ト
Start command from START input.
●Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write operation, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next
command can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is sent back.
First write command
S
T
A
R
T
Write command
S
T
O
P
S
T Slave
A
R address
T
S
T Slave
A
R address
T
A
C
K
H
A
C
K
H
tWR
Second write command
…
S
T Slave
A
R address
T
A
C
K
H
S
T Slave
A
R address
T
A
C Word
K address
L
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
After completion of internal write,
ACK=LOW is sent back, so input next
word address and data in succession.
Figure 47. Case to continuously write by acknowledge polling
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise
of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Figure 48.)
After execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
・Rise of D0 taken clock
SCL
・Rise of SDA
SCL
SDA
D1
D0
SDA
ACK
SDA
S
T Slave
A address
R
T
A
C Word
K address
L
ACK
D0
Enlarged view
Enlarged view
A
C D7 D6 D5 D4 D3 D2 D1 D0
K
L
WP cancels invalid area
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
WP cancels valid area
Write forced end
Data is not written.
Data not guaranteed
WP
Figure 48. WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Figure 49.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Figure 49. Case of cancel by start, stop condition during slave address input
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, operating frequency is
limited. The smaller the RPU, the larger the consumption current at operation.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by input leak total (IL) of device connected to bus at output of 'H' to SDA
(2)The bus electric potential○
bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended
noise margin 0.2 VCC.
Vcc - ILRPU - 0.2Vcc ≧ VIH
∴
0.8Vcc - VIH
IL
RPU =
BR24AXX
Microcontroller
RPU
Ex. ) When VCC =3V, IL=10μA, VIH=0.7 VCC,
from (2)
RPU ≦
0.8×3- 0.7×3
10×10-6
IL
○Minimum value of RPU
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
≦ IOL
∴
IL
Bus line
バスライン容量
capacity
CBUS
CBUS
≦ 300 [kΩ]
VCC-VOL
RPU
SDA terminal
A
RPU ≦
Figure 50. I/O circuit diagram
VC-VOL
IOL
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise
margin 0.1 VCC.
VOLMAX ≦ VIL-0.1 VCC
Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3 VCC
from (1)
3－0.4
RPU ≧
3×10 -3
≧ 867 [Ω]
And
VOL = 0.4 [V]
VIL = 0.3×3
= 0.9 [V]
Therefore, the condition (2) is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ to several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
●A0, A1, A2, WP process
○Process of device address terminals (A0,A1,A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or VCC or GND. And,
pins (N, C, PIN) not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
Types with N.C.PIN
BR24A16/F/FJ -WM
A0, A1, A2
BR24A08/F/FJ-WM
A0, A1
BR24A04/F/FJ -WM
A0
○Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or VCC. In the case to use both READ and WRITE, control WP terminal or connect it
to pull down or GND.
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Cautions on microcontroller connection
○Rs
2
In I C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open
drain input/output, Rs can be used.
ACK
RPU
SCL
RS
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
Figure 51. I/O circuit diagram
Figure 52. Input / output collision timing
○Maximum value of Rs
The maximum value of Rs is determined by the following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
(2)The bus electric potential ○
should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1 VCC.
VCC
(VCC－VOL)×RS
RPU+RS
RPU A
RS
VOL
∴ RS ≦
IOL
Bus line
capacity CBUS
VIL
VIL－VOL－0.1VCC
1.1VCC－VIL
×
RPU
Example）When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ,
EEPROM
Microcontroller
+ VOL+0.1VCC≦VIL
from(2),
Figure 53. I/O circuit diagram
RS ≦
0.3×3－0.4－0.1×3
1.1×3－0.3×3
×
3
20×10
≦ 1.67［kΩ］
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following
relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so
forth. Set the over current to EEPROM 10mA or below.
VCC
≦
RS
RPU
I
'L' output
RS
∴ RS ≧
VCC
I
Over currentⅠ
Example）When VCC=3V, I=10mA
'H' output
RS
Microcontroller
EEPROM
3
10×10-3
≧ 300［Ω］
Figure 54. I/O circuit diagram
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
≧
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●I2C BUS input / output circuit
○Input (A0,A2,SCL)
Figure 55. Input pin circuit diagram
○Input / output (SDA)
Figure 56. Input / output pin circuit diagram
○Input (A1, WP)
Figure 57. Input pin circuit diagram
●Notes on power ON
At power on, in IC internal circuit and set, VCC rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the operation,
observe the following conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
Recommended conditions of tR, tOFF,Vbot
tR
tOFF
tOFF
Vbot
Vbot
10ms or below
10ms or longer
0.3V or below
100ms or below
10ms or longer
0.2V or below
0
Figure 58. Rise waveform diagram
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on.
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
Figure 59. When SCL= 'H' and SDA= 'L'
tSU:DAT
Figure 60. When SCL='L' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(Page 17).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite operation at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below,
it prevent data rewrite.
●VCC noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1μF) between IC VCC and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board VCC and GND.
●Note of use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and operation temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of
fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4)GND electric potential
Set the voltage of GND terminal lowest at any operating condition. Make sure that each terminal voltage is lower than
that of GND terminal.
(5)Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6)Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Ordering Information
Product Code Description
B
R
2 4
A
x
x
x
x
x
- WM
x x
BUS type
24: I2C
Operating temperature
-40℃ to +105℃
Capacity
01A=1K
02=2K
04=4K
Package
F
08=8K
16=16K
32=32K
64=64K
: SOP8
FJ
: SOP-J8
FVM
: MSOP8
W
: Double Cell
M
: For Automotive Application
Packaging and forming specification
E2
: Embossed tape and reel
(SOP8,SOP-J8)
TR
: Embossed tape and reel
(MSOP8)
●Lineup
Package
Capacity
Type
1K
2K
4K
8K
16K
Quantity
SOP8
Reel of 2500
SOP-J8
Reel of 2500
SOP8
Reel of 2500
SOP-J8
Reel of 2500
MSOP8
Reel of 3000
SOP8
Reel of 2500
SOP-J8
Reel of 2500
SOP8
Reel of 2500
SOP-J8
Reel of 2500
SOP8
Reel of 2500
SOP-J8
Reel of 2500
32K
SOP8
Reel of 2500
64K
SOP8
Reel of 2500
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6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Physical Dimension Tape and Reel Information
SOP8
6
5
1 2
3
4
0.3MIN
7
4.4±0.2
6.2±0.3
8
+6°
4° −4°
0.9±0.15
5.0±0.2
(MAX 5.35 include BURR)
0.595
1.5±0.1
+0.1
0.17 -0.05
S
S
0.11
0.1
1.27
0.42±0.1
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
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© 2012 ROHM Co., Ltd. All rights reserved.
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)
∗ Order quantity needs to be multiple of the minimum quantity.
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TSZ02201-0R1R0G100140-1-2
6.Nov.2013 Rev.002
Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Physical Dimension Tape and Reel Information‐Continued
SOP-J8
4.9±0.2
(MAX 5.25 include BURR)
7
6
5
1
2
3
4
0.45MIN
8
3.9±0.2
6.0±0.3
+6°
4° −4°
0.545
0.2±0.1
1.375±0.1
S
0.175
1.27
0.42±0.1
0.1 S
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
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)
∗ Order quantity needs to be multiple of the minimum quantity.
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Physical Dimension Tape and Reel Information‐Continued
MSOP8
4.0±0.2
2.8±0.1
8 7 6 5
0.6±0.2
+6°
4° −4°
0.29±0.15
2.9±0.1
(MAX 3.25 include BURR)
1 2 3 4
1PIN MARK
+0.05
0.145 –0.03
0.475
0.08±0.05
0.75±0.05
0.9MAX
S
+0.05
0.22 –0.04
0.08 S
0.65
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
3000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
)
1pin
Direction of feed
Reel
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∗ Order quantity needs to be multiple of the minimum quantity.
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TSZ02201-0R1R0G100140-1-2
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Marking Diagrams
SOP8(TOP VIEW)
SOP-J8(TOP VIEW)
Part Number Marking
Part Number Marking
LOT Number
LOT Number
1PIN MARK
1PIN MARK
MSOP8(TOP VIEW)
Part Number Marking
LOT Number
1PIN MARK
●Marking Information
Capacity
Product
Name
Marking
1K
A01A
2K
A02
Package Type
SOP8
SOP-J8
SOP8
SOP-J8
MSOP8
SOP8
4K
A04
8K
A08
16K
A16
32K
A32
SOP8
64K
A64
SOP8
SOP-J8
SOP8
SOP-J8
SOP8
SOP-J8
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Datasheet
BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Revision History
Date
Revision
Changes
31.Aug.2012
001
New Release
6.Nov.2013
002
P.1 Added AEC-Q100 Qualified
P.2 Changed Unit of Pd
P.23 Updated Product Code Description
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Datasheet
Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice - SS
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - SS
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
BR24A01AF-WM - Web Page
Buy
Distribution Inventory
Part Number
Package
Unit Quantity
Minimum Package Quantity
Packing Type
Constitution Materials List
RoHS
BR24A01AF-WM
SOP8
2500
2500
Taping
inquiry
Yes