NSC DM54LS373 Tri-statee octal d-type transparent latches and edge-triggered flip-flop Datasheet

DM54LS373/DM74LS373,
DM54LS374/DM74LS374
TRI-STATEÉ Octal D-Type Transparent
Latches and Edge-Triggered Flip-Flops
General Description
Features
These 8-bit registers feature totem-pole TRI-STATE outputs
designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
(Continued)
Y
Y
Y
Y
Y
Choice of 8 latches or 8 D-type flip-flops in a single
package
TRI-STATE bus-driving outputs
Full parallel-access for loading
Buffered control inputs
P-N-P inputs reduce D-C loading on data lines
Connection Diagrams
Dual-In-Line Packages
’LS373
Order Number
DM54LS373J,
DM54LS373W,
DM74LS373N or
DM74LS373WM
See NS Package Number
J20A, M20B, N20A or
W20A
TL/F/6431 – 1
’LS374
Order Number
DM54LS374J,
DM54LS374W,
DM74LS374WM or
DM74LS374N
See NS Package Number
J20A, M20B, N20A or
W20A
TL/F/6431 – 2
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C1995 National Semiconductor Corporation
TL/F/6431
RRD-B30M105/Printed in U. S. A.
DM54LS373/DM74LS373, DM54LS374/DM74LS374
TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
May 1992
General Description (Continued)
A buffered output control input can be used to place the
eight outputs in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance
state the outputs neither load nor drive the bus lines significantly.
The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be retained
or new data can be entered even while the outputs are off.
The eight latches of the DM54/74LS373 are transparent Dtype latches meaning that while the enable (G) is high the Q
outputs will follow the data (D) inputs. When the enable is
taken low the output will be latched at the level of the data
that was set up.
The eight flip-flops of the DM54/74LS374 are edge-triggered D-type flip flops. On the positive transition of the
clock, the Q outputs will be set to the logic states that were
set up at the D inputs.
Function Tables
DM54/74LS373
DM54/74LS374
Output
Control
Enable
G
D
Output
Output
Control
L
L
L
H
H
H
L
X
H
L
X
X
H
L
Q0
Z
L
L
L
H
Clock
D
Output
u
u
H
L
X
X
H
L
Q0
Z
L
X
H e High Level (Steady State), L e Low Level (Steady State), X e Don’t Care
e Transition from low-to-high level, Z e High Impedance State
Q0 e The level of the output before steady-state input conditions were established.
u
Logic Diagrams
DM54/74LS373
Transparent Latches
DM54/74LS374
Positive-Edge-Triggered Flip-Flops
TL/F/6431–3
TL/F/6431 – 4
2
Absolute Maximum Ratings (See Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
Input Voltage
Storage Temperature Range
7V
7V
b 65§ C to a 150§ C
Operating Free Air Temperature Range
b 55§ C to a 125§ C
DM54LS
DM74LS
0§ C to a 70§ C
Recommended Operating Conditions
Symbol
DM54LS373
Parameter
DM74LS373
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
VCC
Supply Voltage
VIH
High Level Input Votage
VIL
Low Level Input Voltage
0.7
0.8
V
IOH
High Level Output Current
b1
b 2.6
mA
IOL
Low Level Output Current
24
mA
tW
Pulse Width
(Note 2)
2
2
12
Enable High
15
15
Enable Low
15
15
tSU
Data Setup Time (Notes 1 & 2)
5v
5v
tH
Data Hold Time (Notes 1 & 2)
20v
20v
TA
Free Air Operating Temperature
Note 1: The symbol (
b 55
125
V
V
ns
ns
ns
0
70
§C
v) indicates the falling edge of the clock pulse is used for reference.
Note 2: TA e 25§ C and VCC e 5V.
’LS373 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC e Min, II e b18 mA
VOH
High Level Output Voltage
VCC e Min
IOH e Max
VIL e Max
VIH e Min
VOL
Low Level Output Voltage
Min
DM54
Typ
(Note 1)
2.4
3.4
2.4
3.1
Max
Units
b 1.5
V
V
DM74
VCC e Min
IOL e Max
VIL e Max
VIH e Min
DM54
DM74
IOL e 12 mA
VCC e Min
0.25
0.4
0.35
0.5
DM74
V
0.4
II
Input Current @ Max
Input Voltage
VCC e Max, VI e 7V
IIH
High Level Input Current
VCC e Max, VI e 2.7V
20
mA
IIL
Low Level Input Current
VCC e Max, VI e 0.4V
b 0.4
mA
IOZH
Off-State Output Current
with High Level Output
Voltage Applied
VCC e Max, VO e 2.7V
VIH e Min, VIL e Max
20
mA
Off-State Output Current
with Low Level Output
Voltage Applied
VCC e Max, VO e 0.4V
VIH e Min, VIL e Max
b 20
mA
Short Circuit
Output Current
VCC e Max
(Note 2)
Supply Current
VCC e Max, OC e 4.5V,
Dn, Enable e GND
IOZL
IOS
ICC
3
0.1
DM54
b 20
b 100
DM74
b 50
b 225
24
40
mA
mA
mA
‘LS373 Switching Characteristics at VCC e 5V and TA e 25§ C
(See Section 1 for Test Waveforms and Output Load)
Symbol
From
(Input)
To
(Output)
Parameter
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
RL e 667X
CL e 45 pF
Min
CL e 150 pF
Max
Min
Units
Max
Propagation Delay
Time Low to High
Level Output
Data
to
Q
18
26
ns
Propagation Delay
Time High to Low
Level Output
Data
to
Q
18
27
ns
Propagation Delay
Time Low to High
Level Output
Enable
to
Q
30
38
ns
Propagation Delay
Time High to Low
Level Output
Enable
to
Q
30
36
ns
Output Enable
Time to High
Level Output
Output
Control
to Any Q
28
36
ns
Output Enable
Time to Low
Level Output
Output
Control
to Any Q
36
50
ns
Output Disable
Time from High
Level Output (Note 3)
Output
Control
to Any Q
20
ns
Output Disable
Time from Low
Level Output (Note 3)
Output
Control
to Any Q
25
ns
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: CL e 5 pF.
Recommended Operating Conditions
Symbol
DM54LS374
Parameter
DM74LS374
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
V
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
0.7
0.8
V
IOH
High Level Output Current
b1
b 2.6
mA
IOL
Low Level Output Current
24
mA
tW
Pulse Width
(Note 4)
2
2
12
Clock High
15
15
Clock Low
15
15
tSU
Data Setup Time (Notes 1 & 4)
20u
20u
tH
Data Hold Time (Notes 1 & 4)
1u
1u
TA
Free Air Operating Temperature
b 55
u
Note 1: The symbol ( ) indicates the rising edge of the clock pulse is used for reference.
Note 4: TA e 25§ C and VCC e 5V.
4
125
0
V
ns
ns
ns
70
§C
’LS374 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
b 1.5
V
VI
Input Clamp Voltage
VCC e Min, II e b18 mA
VOH
High Level Output Voltage
VCC e Min
IOH e Max
VIL e Max
VIH e Min
DM54
2.4
3.4
DM74
2.4
3.1
VCC e Min
IOL e Max
VIL e Max
VIH e Min
DM54
0.25
0.4
DM74
0.35
0.5
IOL e 12 mA
VCC e Min
DM74
VOL
II
Low Level Output Voltage
V
V
0.25
0.4
Input Current @ Max
Input Voltage
VCC e Max, VI e 7V
IIH
High Level Input Current
20
mA
IIL
Low Level Input Current
VCC e Max, VI e 2.7V
VCC e Max, VI e 0.4V
b 0.4
mA
IOZH
Off-State Output
Current with High
Level Output
Voltage Applied
VCC e Max, VO e 2.7V
VIH e Min, VIL e Max
20
mA
Off-State Output
Current with Low
Level Output
Voltage Applied
VCC e Max, VO e 0.4V
VIH e Min, VIL e Max
b 20
mA
Short Circuit
Output Current
VCC e Max
(Note 2)
Supply Current
VCC e Max, Dn e GND, OC e 4.5V
IOZL
IOS
ICC
0.1
DM54
b 50
b 225
DM74
b 50
b 225
27
mA
mA
45
mA
’LS374 Switching Characteristics at VCC e 5V and TA e 25§ C
(See Section 1 for Test Waveforms and Output Load)
RL e 667X
Symbol
Parameter
CL e 45 pF
Min
Max
35
CL e 150 pF
Min
Units
Max
fMAX
Maximum Clock Frequency
tPLH
Propagation Delay Time
Low to High Level Output
20
28
32
ns
tPHL
Propagation Delay Time
High to Low Level Output
28
38
ns
tPZH
Output Enable Time
to High Level Output
28
44
ns
tPZL
Output Enable Time
to Low Level Output
28
44
ns
tPHZ
Output Disable Time
from High Level Output (Note 3)
20
ns
tPLZ
Output Disable Time
from Low Level Output (Note 3)
25
ns
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: CL e 5 pF.
5
MHz
Physical Dimensions inches (millimeters)
20-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54LS373J or DM54LS374J
NS Package Number J20A
6
Physical Dimensions inches (millimeters) (Continued)
20-Lead Wide Small Outline Molded Package (M)
Order Number DM74LS373WM or DM74LS374WM
NS Package Number M20B
20-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS373N and DM74LS374N
NS Package Number N20A
7
DM54LS373/DM74LS373, DM54LS374/DM74LS374
TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Flat Package (W)
Order Number DM54LS373W or DM54LS374W
NS Package Number W20A
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