EMIF10-COM01F2 ® IPAD™ EMI FILTER INCLUDING ESD PROTECTION MAIN PRODUCT CHARACTERISTICS EMI filtering and ESD protection for: ■ ■ ■ Computers and printers Communication systems Mobile phones DESCRIPTION The EMIF10-COM01F2 is a highly integrated device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 Flip-Chip packaging means the package size is equal to the die size. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges up to 15 kV. Flip-Chip (25 Bumps) Table 1: Order Code Part Number EMIF010-COM01F2 Marking FE Figure 1: Pin Configuration (Ball side) BENEFITS ■ EMI symmetrical (I/O) low-pass filter ■ Lead free package 2 ■ Very low PCB space consuming: < 6mm ■ Very thin package: 0.65 mm ■ High efficiency in ESD suppression on both input & output pins ■ High reliability offered by monolithic integration COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 level 4 15kV (air discharge) 8kV (contact discharge) E D C B A I5 I4 I3 I2 I1 1 I10 I9 I8 I7 I6 2 GND GND GND GND GND 3 010 09 08 07 06 4 05 04 03 02 01 5 Figure 2: Basic cell configuration Low-pass Filter Input Output RI/O = 200Ω Cline = 45 pF TM: IPAD is a trademark of STMicroelectronics. April 2005 REV. 2 1/7 EMIF10-COM01F2 Table 2: Absolute Ratings (Tamb = 25°C) Symbol VPP Tj Parameter and test conditions Value Unit ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge 15 8 kV Junction temperature 125 °C Top Operating temperature range - 40 to + 85 °C Tstg Storage temperature range - 55 to + 150 °C Table 3: Electrical Characteristics (Tamb = 25°C) Symbol VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Series resistance between Input & Output Cline Input capacitance per line Symbol VCL VBR Test conditions VBR IR = 1 mA IRM VRM = 3V per line Rd IPP = 10A, tp = 2.5µs RI/O Cline tLH 2/7 I Parameter VRM slope : 1 / R d Vinput = 2.8V Rload = 100kΩ IPP Min. Typ. Max. Unit 6 8 10 V 500 nA Ω 1 180 At 0V bias V IRM IR 200 220 Ω 45 50 pF 25 ns EMIF10-COM01F2 Figure 3: S21(db) attenuation measurement Figure 4: Analog crosstalk 0.00 EMIF10-COM01F2: Typical S21(dB) measurement on line I10/O10 dB 0.00 dB -5.00 -10.00 -20.00 -10.00 -30.00 -15.00 -40.00 -20.00 -50.00 -25.00 -30.00 -60.00 -35.00 -70.00 -40.00 -80.00 -45.00 -50.00 1.0M -90.00 3.0M 10.0M 30.0M 100.0M 300.0M f/Hz 1.0G 3.0G -100.00 100.0k 1.0M 10.0M 100.0M 1.0G f/Hz Note: Spikes at high frequencies are induced by the PCB layout Figure 5: ESD response to IEC61000-4-2 (+15kV air discharge) on one input V(in) and on one output (Vout) Figure 6: ESD response to IEC61000-4-2 (-15kV air discharge) on one input V(in) and on one output (Vout) V(in1) V(in1) V(out1) V(out1) Figure 7: Rise time measurement EMIF10-COM01F2 In Out Vout Square signal Generator Vc = 2.8V Vin 100k Vout Vin 3/7 EMIF10-COM01F2 Figure 8: Capacitance versus reverse applied voltage C(pF) 50 F=1MHz Vosc=30mV 40 30 20 10 0 1 2 3 4 5 VR(V) Figure 9: Aplac model 200R out in MODEL = demif10 MODEL = demif10 Demif10 model BV = 7 IBV = 1m CJO = 25p M = 0.3333 RS = 1 VJ = 0.6 TT = 100n sub PCB grounding recommendations In order to ensure a good efficiency in terms of ESD protection and filtering behavior, we recommend to implement microvias (100 µm dia.) between the GND bumps and the GND layer. GND bumps can be connected together in PCB layer 1, and in addition, if possible, use through hole vias (200 µm dia.) in both sides of filter to improve contact to GND (layer). This layout will minimize the distance to the ground and thus parasitic inductances. In addition, we recommend to have GND plane wherever possible. 4/7 EMIF10-COM01F2 Figure 10: Ordering Information Scheme EMIF yy - xxx zz Fx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip-Chip x = 1: 500µm, Bump = 315µm = 2: Leadfree Pitch = 500µm, Bump = 315µm = 3: Leadfree Pitch = 400µm, Bump = 250µm Figure 11: FLIP-CHIP Package Mechanical Data 500µm ± 50 650µm ± 65 2.42mm ± 50µm 500µm ± 50 315µm ± 50 2.42mm ± 50µm Figure 12: Foot print recommendations Figure 13: Marking 545 400 545 Copper pad Diameter : 250µm recommended , 300µm max Dot, ST logo xx = marking z = packaging location yww = datecode (y = year ww = week) E Solder stencil opening : 330µm x x z y ww 100 230 Solder mask opening recommendation : 340µm min for 315µm copper pad diameter All dimensions in µm 5/7 EMIF10-COM01F2 Figure 14: FLIP-CHIP Tape and Reel Specification Dot identifying Pin A1 location 1.75 +/- 0.1 Ø 1.5 +/- 0.1 4 +/- 0.1 3.5 +/- 0.1 ST E xxz yww ST E xxz yww ST E xxz yww 8 +/- 0.3 0.73 +/- 0.05 4 +/- 0.1 User direction of unreeling All dimensions in mm Table 4: Ordering Information Ordering code Marking Package Weight Base qty Delivery mode EMIF10-COM01F2 FE Flip-Chip 8.3 mg 5000 Tape & reel Note: More informations are available in the application notes: AN1235: “Flip-Chip: Package description and recommendations for use” AN1751: "EMI Filters: Recommendations and measurements" Table 5: Revision History 6/7 Date Revision Description of Changes 14-Dec-2004 1 First issue. 12-Apr-2005 2 Die clearance reduction. EMIF10-COM01F2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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