GM71V17403C GM71VS17403CL 4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM Description Features The GM71V(S)17403C/CL is the new generation dynamic RAM organized 4,194,304 words x 4 bit. GM71V(S)17403C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)17403C/CL offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71V(S)17403C/CL to be packaged in a standard 300 mil 24(26) pin SOJ, and a standard 300 mil 24(26) pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply 3.3V +/- 0.3V tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. * 4,194,304 Words x 4 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (3.3V +/- 0.3V) * Fast Access Time & Cycle Time Pin Configuration tRAC tCAC GM71V(S)17403C/CL-5 GM71V(S)17403C/CL-6 GM71V(S)17403C/CL-7 50 60 70 13 15 18 tRC tHPC 84 104 124 20 25 30 * Low Power Active : 432/369/360mW (MAX) Standby : 7.2mW (CMOS level : MAX) : 0.36mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability *All inputs and outputs TTL Compatible * 2048 Refresh Cycles/32ms * 2048 Refresh Cycles/128ms (L-version) * Self Refresh Operation (L-version) * Battery Backup Operation (L-version) * Test Function : 16bit parallel test mode 24(26) SOJ 24(26) TSOP II VCC 1 26 VSS VCC 1 26 VSS I/O1 2 25 I/O4 I/O1 2 25 I/O4 I/O2 3 24 I/O3 I/O2 3 24 I/O3 WE 4 23 CAS WE 4 23 CAS RAS 5 22 OE RAS 5 22 OE NC 6 21 A9 A11 6 21 A9 A10 8 19 A8 A10 8 19 A8 A0 9 18 A7 A0 9 18 A7 A1 10 17 A6 A1 10 17 A6 A2 11 16 A5 A2 11 16 A5 A3 12 15 A4 A3 12 15 A4 VCC 13 14 VSS VCC 13 14 VSS (Top View) Rev 0.1 / Apr’01 (Unit: ns) GM71V17403C GM71VS17403CL Pin Description Pin Function Pin Function A0-A10 Address Inputs WE Read/Write Enable A0-A10 Refresh Address Inputs OE Output Enable I/O1-I/O4 Data Input/Data Output VCC Power (+3.3V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe NC No Connection Ordering Information Type No. Access Time Package GM71V(S)17403CJ/CLJ-5 GM71V(S)17403CJ/CLJ-6 GM71V(S)17403CJ/CLJ-7 50ns 60ns 70ns 300 Mil 24(26) Pin Plastic SOJ GM71V(S)17403CT/CLT-5 GM71V(S)17403CT/CLT-6 GM71V(S)17403CT/CLT-7 50ns 60ns 70ns 300 Mil 24(26) Pin Plastic TSOP II Absolute Maximum Ratings Symbol Parameter Rating Unit 0 ~ 70 C -55 ~ 125 C -0.5 ~ Vcc+0.5 (<=4.6V(MAX)) V -0.5 ~ 4.6 V TA Ambient Temperature under Bias TSTG Storage Temperature VIN/OUT Voltage on any Pin Relative to VSS VCC Supply Voltage Relative to VSS IOUT Short Circuit Output Current 50 mA PD Power Dissipation 1.0 W Recommended DC Operating Conditions (TA = 0 ~ 70C) Symbol Parameter Min Typ Max Unit VCC Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.0 - VCC + 0.3 V VIL Input Low Voltage -0.3 - 0.8 V Note: All voltage referred to Vss. Rev 0.1 / Apr’01 GM71V17403C GM71VS17403CL DC Electrical Characteristics (VCC = 3.3V+/-0.3V, VSS = 0V, TA = 0 ~ 70C) Symbol Parameter Min Max Unit VOH Output Level Output "H" Level Voltage (IOUT = -2mA) 2.4 VCC V VOL Output Level Output "L" Level Voltage (IOUT = 2mA) 0 0.4 V ICC1 Operating Current Average Power Supply Operating Current (RAS, CAS Cycling : tRC = tRC min) 50ns - 100 60ns - 90 70ns - 80 - 2 ICC2 Standby Current (TTL) Power Supply Standby Current (RAS, CAS = VIH, DOUT = High-Z) mA Note 1, 2 mA RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) 50ns - 100 60ns - 90 70ns - 80 EDO Page Mode Current Average Power Supply Current EDO Page Mode (tHPC = tHPC min) 50ns - 90 60ns - 80 70ns - 75 - 1 mA - 100 uA 50ns - 100 60ns - 90 70ns - 80 Battery Backup Operating Current(Standby with CBR Refresh) (CBR refresh, tRC = 31.3us, tRAS <= 0.3us, DOUT = High-Z, CMOS interface) - 300 uA 4,5 Standby Current RAS = VIH CAS = VIL DOUT = Enable - 5 mA 1 ICC9 Self-Refresh Mode Current (RAS, CAS<=0.2V, DOUT=High-Z, CMOS interface) - 200 uA 5 IL(I) Input Leakage Current Any Input (0V<=VIN<= 4.6V) -10 10 uA IL(O) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<= 4.6V) -10 10 uA ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 Standby Current (CMOS) Power Supply Standby Current (RAS, CAS >= VCC - 0.2V, DOUT = High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L (<=0.2) while RAS = L (<=0.2). 5. L - Version. Rev 0.1 / Apr’01 mA 2 mA 1, 3 5 mA GM71V17403C GM71VS17403CL Capacitance (VCC = 3.3V +/- 0.3V, TA = 25C) Symbol Parameter Min Max Unit Note CI1 Input Capacitance (Address) - 5 pF 1 CI2 Input Capacitance (Clocks) - 7 pF 1 CI/O Output Capacitance (Data-In/Out) - 7 pF 1, 2 Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable DOUT. AC Characteristics (VCC = 3.3V +/- 0.3V, VSS = 0V, TA = 0 ~ 70C, Notes 1, 2, 18) Test Conditions Input rise and fall times : 2ns Input levels : VIL = 0V, VIH = 3V Input timing reference levels : 0.8V, 2.0V Output timing reference levels : 0.8V, 2.0V Output load : 1 TTL gate + CL (100pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Symbol Parameter GM71V(S)17403 GM71V(S)17403 GM71V(S)17403 C/CL-6 C/CL-7 C/CL-5 Unit Note Min Max Min Max Min Max tRC Random Read or Write Cycle Time 84 - 104 - 124 - ns tRP RAS Precharge Time 30 - 40 - 50 - ns tCP CAS Precharge Time 8 - 10 - 13 - ns tRAS RAS Pulse Width 50 10,000 60 10,000 70 10,000 ns tCAS CAS Pulse Width 8 10,000 10 10,000 13 10,000 ns tASR Row Address Set up Time 0 - 0 - 0 - ns tRAH Row Address Hold Time 8 - 10 - 10 - ns tASC Column Address Set-up Time 0 - 0 - 0 - ns tCAH tRCD tRAD tRSH tCSH tCRP Column Address Hold Time 8 - 10 - 13 - ns RAS to CAS Delay Time 12 37 14 45 14 52 ns 3 RAS to Column Address Delay Time 10 25 12 30 12 35 ns 4 RAS Hold Time 10 - 13 - 13 - ns CAS Hold Time 35 - 40 - 45 - ns 5 - 5 - 5 - ns tODD tDZO OE to DIN Delay Time 13 - 15 - 18 - ns 5 0 - 0 - 0 - ns 6 tDZC tT CAS Delay Time from DIN 0 - 0 - 0 - ns 6 Transition Time (Rise and Fall) 2 50 2 50 2 50 ns 7 CAS to RAS Precharge Time OE Delay Time from DIN Rev 0.1 / Apr’01 GM71V17403C GM71VS17403CL Read Cycle Symbol Parameter GM71V(S)17403 GM71V(S)17403 GM71V(S)17403 C/CL-5 C/CL-6 C/CL-7 Min Max Min Unit Note Max Min Max tRAC tCAC Access Time from RAS - 50 - 60 - 70 ns 8.9.19 Access Time from CAS - 13 - 15 - 18 ns tAA Access Time from Address - 25 - 30 - 35 ns 9,10, 17,19 9,11, 17,19 tOAC tRCS Access Time from OE - 13 - 15 - 18 ns Read Command Setup Time 0 - 0 - 0 - ns tRCH Read Command Hold Time to CAS 0 - 0 - 0 - ns tRCHR Read Command Hold Time from RAS 50 - 60 - 70 - ns tRRH tRAL Read Command Hold Time to RAS 5 - 5 - 5 - ns Column Address to RAS Lead Time 25 - 30 - 35 - ns tCAL Column Address to CAS Lead Time 15 - 18 - 23 - ns tCLZ CAS to Output in low-Z 0 - 0 - 0 - ns tOH tOHO Output Data Hold Time 3 - 3 - 3 - ns Output Data Hold Time from OE 3 - 3 - 3 - ns tOEZ tOFF Output Buffer Turn-off Time to OE - 13 - 15 - 15 ns 13 Output Buffer Turn-off Time - 13 - 15 - 15 ns 13 tCDD tOHR tOFR CAS to DIN Delay Time 13 - 15 - 18 - ns 5 Output Data Hold Time from RAS 3 - 3 - 3 - ns Output Buffer Turn-off Time to RAS - 13 - 15 - 15 ns tWEZ tWDD Output Buffer Turn-off to WE - 13 - 15 - 15 ns WE to DIN Delay Time 13 - 15 - 18 - ns tRDD RAS to DIN Delay Time 13 - 15 - 18 - ns Rev 0.1 / Apr’01 9 12 12 GM71V17403C GM71VS17403CL Write Cycle GM71V(S)17403 GM71V(S)17403 GM71V(S)17403 C/CL-5 C/CL-6 C/CL-7 Symbol Parameter Min Max Min Max Min Max Unit Note 14 tWCS Write Command Setup Time 0 - 0 - 0 - ns tWCH Write Command Hold Time 8 - 10 - 13 - ns tWP Write Command Pulse Width 8 - 10 - 10 - ns tRWL Write Command to RAS Lead Time 8 - 10 - 13 - ns tCWL Write Command to CAS Lead Time 8 - 10 - 13 - ns tDS tDH Data-in Setup Time 0 - 0 - 0 - ns 15 Data-in Hold Time 8 - 10 - 13 - ns 15 Unit Note Read- Modify-Write Cycle Symbol Parameter GM71V(S)17403 GM71V(S)17403 GM71V(S)17403 C/CL-6 C/CL-7 C/CL-5 Min Max Min Max Min Max tRWC Read-Modify-Write Cycle Time tRWD 111 - 136 - 161 - ns RAS to WE Delay Time 67 - 79 - 92 - ns 14 tCWD CAS to WE Delay Time 30 - 34 - 40 - ns 14 tAWD Column Address to WE Delay Time 42 - 49 - 57 - ns 14 tOEH OE Hold Time from WE 13 - 15 - 18 - ns Refresh Cycle Symbol Parameter GM71V(S)17403 GM71V(S)17403 GM71V(S)17403 C/CL-5 C/CL-6 C/CL-7 Min Max Min Max Min Max Unit tCSR CAS Setup Time (CAS-before-RAS Refresh Cycle) 5 - 5 - 5 - ns tCHR CAS Hold Time (CAS-before-RAS Refresh Cycle) 8 - 10 - 10 - ns tWRP WE Setup Time (CAS-before-RAS Refresh Cycle) 0 - 0 - 0 - ns tWRH WE Hold Time (CAS-before-RAS Refresh Cycle) 10 - 10 - 10 - ns tRPC RAS Precharge to CAS Hold Time 5 - 5 - 5 - ns Rev 0.1 / Apr’01 Note GM71V17403C GM71VS17403CL EDO Page Mode Cycle Symbol Parameter GM71V(S)17403 GM71V(S)17403 GM71V(S)17403 C/CL-5 C/CL-6 C/CL-7 Min tHPC EDO Page Mode Cycle Time tRASP EDO Page Mode RAS Pulse Width - tACP tRHCP Access Time from CAS Precharge - RAS Hold Time from CAS Precharge tDOH Max Min 20 - Unit Note ns 20 ns 16 9,17,19 Max Min Max 25 - 30 - - 100,000 - 30 - 35 - 40 ns 30 - 35 - 40 - ns Output data Hold Time from CAS low 3 - 3 - 3 ns tCOL CAS Hold Time referred OE 8 - 10 - 13 ns tCOP CAS to OE Setup Time 5 - 5 - 5 ns tRCHP Read command Hold Time from CAS Precharge 30 - 35 - 40 ns 100,000 100,000 9 EDO Page Mode Read-Modify-Write Cycle Symbol Parameter GM71V(S)17403 GM71V(S)17403 GM71V(S)17403 C/CL-5 C/CL-6 C/CL-7 Unit Note Min Max Min Max Min Max tHPRWC EDO Page Mode Read-Modify-Write Cycle Time 57 - 68 - 79 - ns tCPW WE Delay Time from CAS Precharge 45 - 54 - 62 - ns 14 Unit Note Test Mode Cycle ∗18 Symbol Parameter GM71V(S)17403 GM71V(S)17403 GM71V(S)17403 C/CL-6 C/CL-7 C/CL-5 Min Max Min Max Min Max tWTS Test Mode WE Setup Time 0 - 0 - 0 - ns tWTH Test Mode WE Hold Time 10 - 10 - 10 - ns Refresh Symbol Parameter GM71V(S)17403 GM71V(S)17403 GM71V(S)17403 C/CL-5 C/CL-6 C/CL-7 Unit Note 2048 cycles 2048 cycles Min Max Min Max Min Max tREF Refresh Period - 32 - 32 - 32 ms tREF Refresh Period (L - version) - 128 - 128 - 128 ms Rev 0.1 / Apr’01 GM71V17403C GM71VS17403CL Self Refresh Mode ( L-version ) Symbol Parameter GM71VS17403 CL-5 GM71VS17403 CL-6 GM71VS17403 CL-7 Unit Note Min Max Min Max Min Max tRASS RAS Pulse Width ( Self-refresh ) tRPS tCHS RAS Precharge Time ( Self-refresh ) CAS Hold Time ( Self-refresh ) 100 - 100 - 100 - µs 90 - 110 - 130 - ns -50 - -50 - -50 - ns Notes: 1. AC Measurements assume tT = 2ns. 2. An initial pause of 200us is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH(min) and VIL(max). 8. Assume that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100pF. 10. Assume that tRCD >=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max). 11. Assume that tRAD >=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. Rev 0.1 / Apr’01 GM71V17403C GM71VS17403CL 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS>=tWCS(min), the cycles is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD>=tRWD(min), the tCWD>=tCWD(min), and tAWD>=tAWD(min), or tCWD>=tCWD(min), tAWD>= tAWD(min) and tCPW>=tCPW(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among tAA or tCAC or tACP. 18. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M x 4 are don't care during test mode. Test mode is set by performing a WE-and-CAS-beforeRAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular CAS-before-RAS refresh cycle or RAS-only refresh cycle. 19. In a test mode read cycle, the value of tRAC, tAA, tCAC and tACP is delayed by 2ns to 5ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 20. tHPC(min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle(EDO page mode mix cycle (1),(2)), minimum value of CAS cycle (tCAS + tCP + 2tT) becomes greater than the specified tHPC(min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). Rev 0.1 / Apr’01 GM71V17403C GM71VS17403CL Package Dimension Unit: Inches (mm) 24(26) SOJ 0.025(0.64) 0.275(6.99) MAX 0.260(6.60) MIN 0.340(8.64) MAX 0.329(8.38) MIN 0.305(7.75) MAX 0.295(7.49) MIN MIN 0.085(2.16) 0.661(16.80) MIN 0.669(17.00) MAX MIN 0.128(3.25) MIN 0.147(3.75) MAX 0.026(0.66) MIN 0.032(0.81) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.020(0.50) MAX 24(26) TSOP (TYPE II) 0.670(17.04) MIN 0.678(17.24) MAX 0.004(0.12) MIN 0.008(0.21) MAX 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX 0.012(0.30) MIN 0.020(0.50) MAX Rev 0.1 / Apr’01 0.016(0.40) MIN 0.024(0.60) MAX 0.371(9.42) MAX 0.355(9.02) MIN 0.303(7.72) MAX 0.296(7.52) MIN 0 ~ 5o 0.050(1.27) TYP 0.003(0.08) MIN 0.007(0.18) MAX