ISSI IS61SP6464-7PQ 64k x 64 synchronous pipeline static ram Datasheet

IS61SP6464
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
FEATURES
• Fast access time:
– 133, 117, 100 MHz; 6 ns (83 MHz);
7 ns (75 MHz); 8 ns (66 MHz)
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Five chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 128-Pin TQFP 14mm x 20mm
package
• Single +3.3V power supply
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
ISSI
®
APRIL 2001
DESCRIPTION
The ISSI IS61SP6464 is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, secondary cache for the i486™, Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 64 bits, fabricated with ISSI's advanced
CMOS technology. The device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs into
a single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49I/O56, BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally by the IS61SP6464 and controlled by the ADV (burst
address advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates
after the wake-up period. A LOW input, i.e., GNDQ, on MODE
pin selects LINEAR Burst. A VCCQ (or no connect) on MODE
pin selects INTERLEAVED Burst.
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1
ISSI
IS61SP6464
®
BLOCK DIAGRAM
MODE
CLK
Q0
CLK
A0'
A0
BINARY
COUNTER
ADV
ADSC
ADSP
A15-A0
Q1
CE
A1'
A1
64K x 64
MEMORY
ARRAY
CLR
16
D
Q
14
16
ADDRESS
REGISTER
CE
CLK
64
GW
BWE
BW8
D
64
Q
DQ57-DQ64
BYTE WRITE
REGISTERS
CLK
D
BW1
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
CLK
CE
CE2
CE2
CE3
CE3
8
D
Q
ENABLE
REGISTER
INPUT
REGISTERS
CLK
64
OUTPUT
REGISTERS
CLK
DATA[64:1]
OE
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61SP6464
®
PIN CONFIGURATION
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
VCCQ
CE3
CE2
CE3
CE2
GND
VCC
CE
BW8
BW7
BW6
BW5
OE
CLK
BWE
GW
BW4
BW3
GND
VCC
BW2
BW1
ADSC
ADSP
ADV
GNDQ
128-Pin TQFP
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCCQ
I/O32
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
I/O23
I/O22
GNDQ
VCCQ
I/O21
I/O20
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
GNDQ
VCCQ
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
GNDQ
GNDQ
NC
MODE
A15
A14
A13
VCC
GND
A12
A11
A10
A9
A8
NC
A7
A6
A5
A4
A3
VCC
GND
A2
A1
A0
ZZ
VCCQ
VCCQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GNDQ
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
VCCQ
GNDQ
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
VCCQ
GNDQ
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
PIN DESCRIPTIONS
A0-A15
Address Inputs
I/O1-I/O64
Data Input/Output
CLK
Clock
ZZ
Sleep Mode
ADSP
Processor Address Status
MODE
Burst Sequence Mode
ADSC
Controller Address Status
VCC
+3.3V Power Supply
ADV
Burst Address Advance
GND
Ground
BW1-BW8
Synchronous Byte Write Enable
VCCQ
BWE
Byte Write Enable
Isolated Output Buffer Supply:
+3.3V
GW
Global Write Enable
NC
No Connect
CE, CE2, CE2,
CE3, CE3
Synchronous Chip Enable
GNDQ
Isolated Output Buffer Ground
OE
Output Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
3
ISSI
IS61SP6464
®
TRUTH TABLE
OPERATION
ADDRESS
USED
CE3
CE2
CE3
CE2
CE
ADSP ADSC ADV WRITE
OE CLK
X
X
X
X
H
X
L
X
X
X
L-H
High-Z
I/O
Deselected, Power-down
None
Deselected, Power-down
None
L
X
X
X
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
L
X
X
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
H
X
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
X
H
L
L
X
X
X
X
L-H
High-Z
Deselected, Power-down
None
L
X
X
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
L
X
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
H
X
L
H
L
X
X
X
L-H
High-Z
Deselected, Power-down
None
X
X
X
H
L
H
L
X
X
X
L-H
High-Z
Read Cycle, Begin Burst
External
H
H
L
L
L
L
X
X
X
L
L-H
Dout
Read Cycle, Begin Burst
External
H
H
L
L
L
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
L
X
L-H
Din
Read Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
H
L
L-H
Dout
Read Cycle, Begin Burst
External
H
H
L
L
L
H
L
X
H
H
L-H
High-Z
Next
X
X
X
X
X
H
H
L
H
L
L-H
Dout
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
H
L
L-H
Dout
Read Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
X
X
H
H
L
L
X
L-H
Din
Write Cycle, Continue Burst
Next
X
X
X
X
H
X
H
L
L
X
L-H
Din
Read Cycle, Suspend Burst
Current
X
X
X
X
X
H
H
H
H
L
L-H
Dout
Read Cycle, Suspend Burst
Current
X
X
X
X
X
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
H
L
L-H
Dout
Read Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
X
X
H
H
H
L
X
L-H
Din
Write Cycle, Suspend Burst
Current
X
X
X
X
H
X
H
H
L
X
L-H
Din
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW.
WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61SP6464
®
ASYNCHRONOUS TRUTH TABLE
ZZ
OE
I/O STATUS
Pipelined Read
Pipelined Read
Write
Write
L
L
L
L
L
H
L
H
Dout
High-Z
High-Z
Din
Deselect
L
X
High-Z
Sleep
H
X
High-Z
Operation
WRITE TRUTH TABLE
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
Read
H
H
X
X
X
X
X
X
X
X
Read
H
L
H
H
H
H
H
H
H
H
Write all bytes
H
L
L
L
L
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
X
X
X
X
Write Byte 1
H
L
H
H
H
H
H
H
H
L
Write Byte 2
H
L
H
H
H
H
H
H
L
H
Write Byte 3
H
L
H
H
H
H
H
L
H
H
Write Byte 4
H
L
H
H
H
H
L
H
H
H
Write Byte 5
H
L
H
H
H
L
H
H
H
H
Write Byte 6
H
L
H
H
L
H
H
H
H
H
Write Byte 7
H
L
H
L
H
H
H
H
H
H
Write Byte 8
H
L
L
H
H
H
H
H
H
H
Operation
BW1
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
5
ISSI
IS61SP6464
®
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
A1’, A0’ = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TBIAS
TSTG
PD
IOUT
VIN, VOUT
VIN
Parameter
Temperature Under Bias
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to GND for I/O Pins
Voltage Relative to GND for
for Address and Control Inputs
VCC
Voltage on Vcc Supply Relatiive to GND
Value
Unit
–10 to +85
°C
–55 to +150
°C
1.0
W
100
mA
–0.5 to VCCQ + 0.3
V
–0.5 to 5.5
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE
Range
Commercial
Industrial
6
Ambient Temperature
0°C to +70°C
VCC
3.3V +10%, –5%
–40°C to +85°C
3.3V +10%, –5%
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61SP6464
®
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
IOL = 8 mA
—
0.4
V
VIH
Input HIGH Voltage
2.0
VCCQ + 0.3
V
VIL
Input LOW Voltage
–0.3
0.8
V
ILI
Input Leakage Current
GND - VIN - VCCQ(2)
Com.
Ind.
–2
–10
2
10
µA
ILO
Output Leakage Current
GND - VOUT - VCCQ, OE = VIH
Com.
Ind.
–2
–10
2
10
µA
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
5
pF
VOUT = 0V
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
317 Ω
3.3V
ZO = 50Ω
OUTPUT
Output
Buffer
50Ω
30 pF
1.5V
Figure 1
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
5 pF
Including
jig and
scope
351 Ω
Figure 2
7
ISSI
IS61SP6464
®
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-133
Max.
-117
Max.
-100
Max.
-6
Max.
-7
Max.
-8
Max.
Com.
Ind.
280
—
270
290
250
270
200
220
170
190
150
170
mA
Device Deselected,
VCC = Max.,
All Inputs = VIH or VIL
CLK Cycle Time • tKC min.
Com.
Ind.
70
—
70
80
70
80
70
80
70
80
70
80
mA
Standby Current
CMOS Inputs
Device Deselected,
VCC = Max.,
VIN = VCC • 0.2V, or VIN - 0.2V
CLK Cycle Time • tKC min.
Com.
Ind.
20
—
20
30
20
30
20
30
20
30
20
30
mA
Power-Down Mode
Current
ZZ = VCCQ, CLK Running
All Inputs - GND + 0.2V
or • VCC – 0.2V
Com.
Ind.
20
—
20
30
20
30
20
30
20
30
20
30
mA
Symbol
Parameter
Test Conditions
ICC
AC Operating
Supply Current
Device Selected,
All Inputs = VIL or VIH
OE = VIH,
Cycle Time • tKC min.
ISB1
Standby Current
TTL Inputs
ISB2
IZZ
Unit
Notes:
1. The MODE pin has an internal pullup. ZZ pin has an internal pull-down. This pin may be a No Connect, tied to GND, or tied to
VCCQ.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to - GND + 0.2V
or • Vcc – 0.2V.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61SP6464
®
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
-133 MHz
Min. Max.
-117 MHz
Min. Max.
tKC
Cycle Time
7.5
—
8.5
—
10
—
ns
tKH
Clock High Time
3
—
3.4
—
4
—
ns
tKL
Clock Low Time
3
—
3.4
—
4
—
ns
Clock Access Time
—
5
—
5
—
5
ns
Clock High to Output Invalid
1.5
—
1.5
—
2.5
—
ns
Clock High to Output Low-Z
0
—
0
—
0
—
ns
tKQHZ(1,2)
Clock High to Output High-Z
2
5
2
5
2
5
ns
tOEQ
tKQ
(1)
tKQX
tKQLZ
(1,2)
-100 MHz
Min. Max.
Unit
Output Enable to Output Valid
—
5
—
5
—
5
ns
(1)
Output Disable to Output Invalid
0
—
0
—
0
—
ns
(1,2)
Output Enable to Output Low-Z
0
—
0
—
0
—
ns
tOEHZ(1,2)
Output Disable to Output High-Z
—
—
—
—
2
5
ns
tAS
Address Setup Time
2.5
—
2.5
—
2.5
—
ns
tSS
Address Status Setup Time
2.5
—
2.5
—
2.5
—
ns
tWS
Write Setup Time
2.5
—
2.5
—
2.5
—
ns
tCES
Chip Enable Setup Time
2.5
—
2.5
—
2.5
—
ns
tAVS
Address Advance Setup Time
2.5
—
2.5
—
2.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
ns
tAVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
ns
tOEQX
tOELZ
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
9
ISSI
IS61SP6464
®
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns
Min. Max.
-7 ns
Min. Max.
-8 ns
Min. Max.
Symbol
Parameter
tKC
Cycle Time
12
—
13
—
15
—
ns
tKH
Clock High Time
4.5
—
5
—
6
—
ns
tKL
Clock Low Time
4.5
—
5
—
6
—
ns
Clock Access Time
—
6
—
7
—
8
ns
Clock High to Output Invalid
2.5
—
3
—
3
—
ns
Clock High to Output Low-Z
0
—
0
—
0
—
ns
tKQHZ(1,2)
Clock High to Output High-Z
2
5
2
5
2
6
ns
tOEQ
tKQ
(1)
tKQX
tKQLZ
(1,2)
Unit
Output Enable to Output Valid
—
5
—
5
—
5
ns
(1)
Output Disable to Output Invalid
0
—
0
—
0
—
ns
(1,2)
Output Enable to Output Low-Z
0
—
0
—
0
—
ns
tOEHZ(1,2)
Output Disable to Output High-Z
2
5
2
5
2
6
ns
tAS
Address Setup Time
2.5
—
2.5
—
2.5
—
ns
tSS
Address Status Setup Time
2.5
—
2.5
—
2.5
—
ns
tWS
Write Setup Time
2.5
—
2.5
—
2.5
—
ns
tCES
Chip Enable Setup Time
2.5
—
2.5
—
2.5
—
ns
tAVS
Address Advance Setup Time
2.5
—
2.5
—
2.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
ns
tAVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
ns
tOEQX
tOELZ
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61SP6464
®
READ CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
ADSC initiate read
tSH
ADSC
tAVH
tAVS
Suspend Burst
ADV
tAS
A15-A0
tAH
RD1
RD2
tWS
tWH
tWS
tWH
RD3
GW
BWE
BW8-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
Unselected with CE2, CE3
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
CE2, CE3
CE2, CE3
tOEHZ
tOEQ
OE
DATAOUT
tKQX
tOEQX
tOELZ
High-Z
1a
2a
2b
2c
2d
tKQLZ
3a
tKQHZ
tKQ
DATAIN
High-Z
Pipelined Read
Single Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
Burst Read
Unselected
11
ISSI
IS61SP6464
®
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
-133 MHz
Min. Max.
-117 MHz
Min. Max.
-100 MHz
Min. Max.
tKC
Cycle Time
7.5
—
8.5
—
10
—
ns
tKH
Clock High Time
3
—
3.4
—
4
—
ns
tKL
Clock Low Time
3
—
3.4
—
4
—
ns
tAS
Address Setup Time
2.5
—
2.5
—
2.5
—
ns
tSS
Address Status Setup Time
2.5
—
2.5
—
2.5
—
ns
tWS
Write Setup Time
2.5
—
2.5
—
2.5
—
ns
tDS
Data In Setup Time
2.5
—
2.5
—
2.5
—
ns
tCES
Chip Enable Setup Time
2.5
—
2.5
—
2.5
—
ns
tAVS
Address Advance Setup Time
2.5
—
2.5
—
2.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
ns
tDH
Data In Hold Time
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
ns
tAVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
ns
Unit
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns
Min. Max.
-7 ns
Min. Max.
-8 ns
Min. Max.
Symbol
Parameter
tKC
Cycle Time
12
—
13
—
15
—
ns
tKH
Clock High Time
4.5
—
5
—
6
—
ns
tKL
Clock Low Time
4.5
—
5
—
6
—
ns
tAS
Address Setup Time
2.5
—
2.5
—
2.5
—
ns
tSS
Address Status Setup Time
2.5
—
2.5
—
2.5
—
ns
tWS
Write Setup Time
2.5
—
2.5
—
2.5
—
ns
tDS
Data In Setup Time
2.5
—
2.5
—
2.5
—
ns
tCES
Chip Enable Setup Time
2.5
—
2.5
—
2.5
—
ns
tAVS
Address Advance Setup Time
2.5
—
2.5
—
2.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
ns
tDH
Data In Hold Time
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
ns
tAVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
ns
12
Unit
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61SP6464
®
WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
ADSC initiate Write
ADSC
tAVH
ADV must be inactive for ADSP Write tAVS
ADV
tAS
A15-A0
tAH
WR1
WR2
tWS
tWH
tWS
tWH
tWS
tWH
WR3
GW
BWE
BW8-BW1
WR1
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWS
tWH
WR2
WR3
CE Masks ADSP
CE
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
Unselected with CE2, CE3
CE2, CE3
CE2, CE3
OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
Single Write
tDH
1a
BW8-BW1 only are applied to first cycle of WR2
2a
2b
Burst Write
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
2c
2d
3a
Write
Unselected
13
ISSI
IS61SP6464
®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
-133 MHz
Min. Max.
-117 MHz
Min. Max.
tKC
Cycle Time
7.5
—
8.5
—
10
—
ns
tKH
Clock High Time
3
—
3.4
—
4.
—
ns
tKL
Clock Low Time
3
—
3.4
—
4
—
ns
Clock Access Time
—
5
—
5
—
5
ns
Clock High to Output Invalid
1.5
—
1.5
—
2.5
—
ns
Clock High to Output Low-Z
0
—
0
—
0
—
ns
tKQHZ(1,2)
Clock High to Output High-Z
1.5
7.5
1.5
8.5
2
5
ns
tOEQ
tKQ
(1)
tKQX
tKQLZ
(1,2)
-100 MHz
Min. Max.
Unit
Output Enable to Output Valid
—
5
—
5
—
5
ns
(1)
Output Disable to Output Invalid
0
—
0
—
0
—
ns
(1,2)
Output Enable to Output Low-Z
0
—
0
—
0
—
ns
tOEHZ(1,2)
Output Disable to Output High-Z
—
—
—
—
2
5
ns
tAS
Address Setup Time
2.5
—
2.5
—
2.5
—
ns
tSS
Address Status Setup Time
2.5
—
2.5
—
2.5
—
ns
tWS
Write Setup Time
2.5
—
2.5
—
2.5
—
ns
tCES
Chip Enable Setup Time
2.5
—
2.5
—
2.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
ns
tOEQX
tOELZ
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61SP6464
®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns
Min. Max.
-7 ns
Min. Max.
-8 ns
Min. Max.
Symbol
Parameter
tKC
Cycle Time
12
—
13
—
15
—
ns
tKH
Clock High Time
4.5
—
5
—
6
—
ns
tKL
Clock Low Time
4.5
—
5
—
6
—
ns
Clock Access Time
—
6
—
7
—
8
ns
Clock High to Output Invalid
2.5
—
3
—
3
—
ns
Clock High to Output Low-Z
0
—
0
—
0
—
ns
tKQHZ(1,2)
Clock High to Output High-Z
2
5
2
5
2
6
ns
tOEQ
tKQ
(1)
tKQX
tKQLZ
(1,2)
Unit
Output Enable to Output Valid
—
5
—
5
—
5
ns
(1)
Output Disable to Output Invalid
0
—
0
—
0
—
ns
(1,2)
Output Enable to Output Low-Z
0
—
0
—
0
—
ns
tOEHZ(1,2)
Output Disable to Output High-Z
2
5
2
5
2
6
ns
tAS
Address Setup Time
2.5
—
2.5
—
2.5
—
ns
tSS
Address Status Setup Time
2.5
—
2.5
—
2.5
—
ns
tWS
Write Setup Time
2.5
—
2.5
—
2.5
—
ns
tCES
Chip Enable Setup Time
2.5
—
2.5
—
2.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
ns
tOEQX
tOELZ
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
15
ISSI
IS61SP6464
®
READ/WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
tSH
ADSC
ADV
tAS
A15-A0
tAH
RD1
WR1
tWS
tWH
tWS
tWH
RD2
RD3
GW
BWE
tWS
tWH
WR1
BW8-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
CE2, CE3 and CE2, CE3 only sampled with ADSP or ADSC
CE2, CE3
Unselected with CE2, CE3
CE2, CE3
tOEHZ
tOEQ
OE
DATAOUT
High-Z
2a
1a
tKQLZ
tKQ
DATAIN
tKQX
tOEQX
tOELZ
2c
2d
tKQHZ
tKQX
tKQHZ
High-Z
1a
tDS
Single Read
16
2b
tDH
Single Write
Burst Read
Unselected
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61SP6464
®
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
-133 MHz
Min. Max.
-117 MHz
Min. Max.
tKC
Cycle Time
7.5
—
8.5
—
10
—
ns
tKH
Clock High Time
3
—
3.4
—
4
—
ns
tKL
Clock Low Time
3
—
3.4
—
4
—
ns
Clock Access Time
—
5
—
5
—
5
ns
Clock High to Output Invalid
0
—
—
—
2.5
—
ns
Clock High to Output Low-Z
0
—
0
—
0
—
ns
tKQHZ(3,4)
Clock High to Output High-Z
1.5
7.5
1.5
8.5
2
5
ns
tOEQ
tKQ
(3)
tKQX
tKQLZ
(3,4)
-100 MHz
Min. Max.
Unit
Output Enable to Output Valid
—
5
—
4
—
5
ns
(3)
Output Disable to Output Invalid
0
—
0
—
0
—
ns
(3,4)
Output Enable to Output Low-Z
0
—
0
—
0
—
ns
tOEHZ(3,4)
Output Disable to Output High-Z
—
—
—
—
2
5
ns
tAS
Address Setup Time
2.5
—
2.5
—
2.5
—
ns
tSS
Address Status Setup Time
2.5
—
2.5
—
2.5
—
ns
tCES
Chip Enable Setup Time
2.5
—
2.5
—
2.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
ns
tOEQX
tOELZ
(1)
tZZS
ZZ Standby
2
—
2
—
2
—
cyc
tZZREC
ZZ Recovery(2)
2
—
2
—
2
—
cyc
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
17
ISSI
IS61SP6464
®
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns
Min. Max.
-7 ns
Min. Max.
-8 ns
Min. Max.
Symbol
Parameter
tKC
Cycle Time
12
—
13
—
15
—
ns
tKH
Clock High Time
4.5
—
5
—
6
—
ns
tKL
Clock Low Time
4.5
—
5
—
6
—
ns
Clock Access Time
—
6
—
7
—
8
ns
Clock High to Output Invalid
2.5
—
3
—
3
—
ns
Clock High to Output Low-Z
0
—
0
—
0
—
ns
tKQHZ(3,4)
Clock High to Output High-Z
2
5
2
5
2
6
ns
tOEQ
tKQ
(3)
tKQX
tKQLZ
(3,4)
Unit
Output Enable to Output Valid
—
5
—
5
—
5
ns
(3)
Output Disable to Output Invalid
0
—
0
—
0
—
ns
(3,4)
Output Enable to Output Low-Z
0
—
0
—
0
—
ns
tOEHZ(3,4)
Output Disable to Output High-Z
2
5
2
5
2
6
ns
tAS
Address Setup Time
2.5
—
2.5
—
2.5
—
ns
tSS
Address Status Setup Time
2.5
—
2.5
—
2.5
—
ns
tCES
Chip Enable Setup Time
2.5
—
2.5
—
2.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
ns
tOEQX
tOELZ
(1)
tZZS
ZZ Standby
2
—
2
—
2
—
cyc
tZZREC
ZZ Recovery(2)
2
—
2
—
2
—
cyc
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
ISSI
IS61SP6464
®
SNOOZE AND RECOVERY CYCLE TIMING
tKC
CLK
tSS
tSH
tAS
tAH
tKH
tKL
ADSP
ADSC
ADV
A15-A0
RD2
RD1
GW
BWE
BW8-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE
CE2, CE3
CE2, CE3
tOEHZ
tOEQ
OE
tOEQX
tOELZ
DATAOUT
High-Z
1a
tKQLZ
tKQ
DATAIN
tKQX
tKQHZ
High-Z
tZZS
tZZREC
ZZ
Single Read
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
Snooze with Data Retention
Read
19
ISSI
IS61SP6464
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
Order Part Number
Package
133
IS61SP6464-133TQ
IS61SP6464-133PQ
TQFP
PQFP
117
IS61SP6464-117TQ
IS61SP6464-117PQ
TQFP
PQFP
100
IS61SP6464-100TQ
IS61SP6464-100PQ
TQFP
PQFP
83
IS61SP6464-6TQ
IS61SP6464-6PQ
TQFP
PQFP
75
IS61SP6464-7TQ
IS61SP6464-7PQ
TQFP
PQFP
66
IS61SP6464-8TQ
IS61SP6464-8PQ
TQFP
PQFP
Industrial Range: –40°C to +85°C
Speed
Order Part Number
Package
133
IS61SP6464-133TQI
IS61SP6464-133PQI
TQFP
PQFP
117
IS61SP6464-117TQI
IS61SP6464-117PQI
TQFP
PQFP
100
IS61SP6464-100TQI
IS61SP6464-100PQI
TQFP
PQFP
83
IS61SP6464-6TQI
IS61SP6464-6PQI
TQFP
PQFP
75
IS61SP6464-7TQI
IS61SP6464-7PQI
TQFP
PQFP
66
IS61SP6464-8TQI
IS61SP6464-8PQI
TQFP
PQFP
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01