INTEGRATED CIRCUITS 74ABT16646 74ABTH16646 16-bit bus transceiver/register (3-State) Product specification Supersedes data of 1995 Aug 17 IC23 Data Handbook 1998 Feb 27 Philips Semiconductors Product specification 74ABT16646 74ABTH16646 16-bit bus transceiver/register (3-State) FEATURES DESCRIPTION • Independent registers for A and B buses • Multiple VCC and GND pins minimize switching noise • Live insertion/extraction permitted • Power–up 3-State • Power–up reset • Multiplexed real-time and stored data • Outputs sink 64mA and source 32mA • Latch–up protection exceeds 500mA per JEDEC Std 17 • 74ABTH16646 incorporates bus-hold data inputs which eliminate The 74ABT16646 high–performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16646 16-bit transceiver/register consists of two sets of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes High. Output Enable (nOE) and Direction (nDIR) pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or both. The select (nSAB, nSBA) pins determine whether data is stored or transferred through the device in real-time. The nDIR determines which bus will receive data when the nOE is active Low. In the isolation mode (nOE = High), data from Bus A may be stored in the B register and/or data from Bus B may be stored in the A register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B may be driven at a time. the need for external pull-up resistors to hold unused inputs • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model Two options are available, 74ABT16646 which does not have the bus-hold feature and 74ABTH16646 which incorporates the bus-hold feature. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay nAx to nBx CL = 50pF; VCC = 5V 3.3 2.7 ns CIN Input capacitance VI = 0V or VCC 3 pF CI/O I/O capacitance VO = 0V or VCC; 3-State 7 pF µA Quiescent supply current Outputs disabled; VCC =5.5V 550 ICCZ CC Outputs low; VCC =5.5V 9 mA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABT16646 DL BT16646 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABT16646 DGG BT16646 DGG SOT364-1 56-Pin Plastic SSOP Type III –40°C to +85°C 74ABTH16646 DL BH16646 DL SOT371-1 56-Pin Plastic TSSOP Type II –40°C to +85°C 74ABTH16646 DGG BH16646 DGG SOT364-1 PIN DESCRIPTION PIN NUMBER SYMBOL 2, 55, 27, 30 1CPAB, 1CPBA, 2CPAB, 2CPBA Clock input A to B / Clock input B to A 3, 54, 26, 31 1SAB, 1SBA, 2SAB, 2SBA Select input A to B / Select input B to A 1, 28 1DIR, 2DIR Direction control inputs 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24 1A0 – 1A7, 2A0 – 2A7 Data inputs/outputs (A side) 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33 1B0 – 1B7, 2B0 – 2B7 Data inputs/outputs (B side) 56, 29 1OE, 2OE Output enable inputs 4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V) 7, 22, 35, 50 VCC Positive supply voltage 1998 Feb 27 NAME AND FUNCTION 2 853-1782 19026 Philips Semiconductors Product specification 74ABT16646 74ABTH16646 16-bit bus transceiver/register (3-State) PIN CONFIGURATION 1DIR 1 56 1OE 1CPAB 2 55 1CPBA 1SAB 3 54 1SBA GND 4 53 GND 1A0 5 52 1B0 1A1 6 51 1B1 VCC 7 50 VCC 1A2 8 49 1B2 1A3 9 48 1B3 1A4 10 47 1B4 GND 11 46 GND 1A5 12 45 1B5 1A6 13 44 1B6 1A7 14 43 1B7 2A0 15 42 2B0 2A1 16 41 2B1 2A2 17 40 2B2 GND 18 39 GND 2A3 19 38 2B3 2A4 20 37 2B4 2A5 21 36 2B5 VCC 22 35 VCC 2A6 23 34 2B6 2A7 24 33 2B7 GND 25 32 GND 2SAB 26 31 2SBA 2CPAB 27 30 2CPBA 2DIR 28 29 20E SH00026 FUNCTION TABLE INPUTS OPERATING MODE nDIR nCPAB nCPBA nSAB nSBA nAx nBx X X ↑ X X X Input Unspecified output* Store A, B unspecified X X X ↑ X X Unspecified output* Input Store B, A unspecified H H X X ↑ H or L ↑ H or L X X X X Input Input Store A and B data Isolation, hold storage L L L L X X X H or L X X L H Output Input Real time B data to A bus Stored B data to A bus L L H L X ↑ * DATA I/O nOE = = = = H X X L X Real time A data to B bus Input Output H H or L X H X Stored A data to B bus High voltage level Low voltage level Don’t care Low-to-High clock transition The data output function may be enabled or disabled by various signals at the nOE input. Data input functions are always enabled, i.e., data at the bus pins will be stored on every Low–to–High transition of the clock. 1998 Feb 27 3 Philips Semiconductors Product specification 74ABT16646 74ABTH16646 16-bit bus transceiver/register (3-State) LOGIC SYMBOL (IEEE/IEC) 1OE 56 1DIR 1 LOGIC SYMBOL G3 5 3 EN1 [BA] 6 8 9 10 12 13 14 3 EN2 [AB] 1CPBA 55 1SBA 54 G5 1CPAB 2 1SAB 3 G7 2OE C4 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 C6 29 2DIR 28 G10 10 EN8 [BA] 2 1CPAB 3 1SAB 1 1DIR 55 1CPBA 54 1SBA 56 1OE 10 EN9 [AB] 2CPBA 30 2SBA 31 G12 2CPAB 27 2SAB 26 1A0 5 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 C11 G14 1 5 ∇1 4D 52 1B0 7 1 1 2∇ 7 1A1 6 51 1B1 1A2 8 49 1B2 1A3 9 48 1B3 1A4 10 47 1B4 1A5 12 45 1B5 1A6 13 44 1B6 1A7 14 43 1B7 ∇8 1 12 12 13D 14 1 14 11D 47 45 44 43 15 16 17 19 20 21 23 24 9∇ 38 2B3 2A4 20 2A5 21 37 2B4 2CPAB 26 2SAB 28 2DIR 30 2CPBA 31 2SBA 29 2OE 40 38 37 36 34 33 SH00027 1 2A3 19 27 42 41 1 41 2B1 40 2B2 36 2B5 34 2B6 33 2B7 SH00025 1998 Feb 27 48 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 42 2B0 2A1 16 2A2 17 2A6 23 2A7 24 49 2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 5 1 6D 2A0 15 52 51 C13 4 Philips Semiconductors Product specification 74ABT16646 74ABTH16646 16-bit bus transceiver/register (3-State) The following examples demonstrate the four fundamental bus-management functions that can be performed with the 74ABT16646. REAL TIME BUS TRANSFER BUS B TO BUS A A REAL TIME BUS TRANSFER BUS A TO BUS B B A B B nOE L } nDIR nCPAB nCPBA nSAB nSBA L X X X L A } } nOE L STORAGE FROM A, B, OR A AND B nDIR nCPAB nCPBA nSAB nSBA H X X L X nOE L L H nDIR nCPAB nCPBA nSAB nSBA H ↑ X X X L X X ↑ ↑ ↑ X X X X TRANSFER STORED DATA TO A OR B A B } nOE L L nDIR nCPAB nCPBA nSAB nSBA L X H|L X H H H|L X H X SH00028 1998 Feb 27 5 Philips Semiconductors Product specification 74ABT16646 74ABTH16646 16-bit bus transceiver/register (3-State) LOGIC DIAGRAM nOE nDIR nCPBA nSBA nCPAB nSAB 1 of 16 Channels 1D C1 Q nA0 nB0 1D C1 Q nA1 nB1 nA2 nB2 nA3 nB3 DETAIL A X 7 nA4 nB4 nA5 nB5 nA6 nB6 nA7 nB7 SH00029 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA output in High state –64 mA –65 to 150 °C DC supply voltage IIK DC input diode current VI DC input voltage3 IOK DC output diode current VOUT DC output voltage3 IOUT DC output out ut current Tstg Storage temperature range VI < 0 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Feb 27 6 Philips Semiconductors Product specification 74ABT16646 74ABTH16646 16-bit bus transceiver/register (3-State) RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER MIN VCC DC supply voltage VI Input voltage VIH High-level input voltage UNIT MAX 4.5 5.5 V 0 VCC V 2.0 V VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 64 mA 0 10 ns/V –40 +85 °C DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA TYP MAX –0.9 –1.2 MIN UNIT MAX –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.35 0.55 0.55 V VRST Power-up output voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V ±0 01 ±0.01 ±1 0 ±1.0 ±1 0 ±1.0 µA II IHOLD Input leakage g current Bus Hold current A or B Ports5 74ABTH16646 5V; VI = GND or 5 5V VCC = 5 5.5V 5.5V Control pins VCC = 4.5V; VI = 0.8V 35 35 VCC = 4.5V; VI = 2.0V –75 –75 VCC = 5.5V; VI = 0 to 5.5V ±800 µA Power-off leakage current VCC = 0.0V; VO = 4.5V; VI = 0.0V or 5.5V ±2.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.0V or VCC; VI = GND or VCC; OE/OE = X ±1.0 ±50 ±50 µA IIH + IOZH 3-State output High current VCC = 5.5V; VO = 5.5V; VI = VIL or VIH 1.0 10 10 µA IIL + IOZL 3-State output Low current VCC = 5.5V; VO = 0.0V; VI = VIL or VIH –1.0 –10 –10 µA Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA Output current1 VCC = 5.5V; VO = 2.5V –80 –180 –180 mA 0.55 2 2 mA IOFF IPU/PD ICEX IO ICCH ICCL –50 VCC = 5.5V; Outputs High, VI = GND or VCC Quiescent supply current ICCZ VCC = 5.5V; Outputs Low, VI = GND or VCC –50 9 19 19 mA VCC = 5.5V; Outputs 3–State; VI = GND or VCC 0.55 2 2 mA ∆ICC Additional supply current per input pin2 74ABT16646 VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 5.0 50 50 µA ∆ICC Additional supply current per input pin2 74ABTH16646 VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 200 500 500 µA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.0V, with a transition time of up to 100msec. From VCC = 21.V to VCC = 5V ± 10% a transition time of up to 100µsec is permitted. 5. This is the bus hold overdrive current required to force the input to the opposite logic state. 1998 Feb 27 7 Philips Semiconductors Product specification 74ABT16646 74ABTH16646 16-bit bus transceiver/register (3-State) AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM MIN TYP MAX MIN UNIT MAX fMAX Maximum clock frequency 1 125 125 MHz tPLH tPHL Propagation delay nCPAB to nBx or nCPBA to nAx 1 1.5 1.5 3.3 2.7 4.0 4.1 1.5 1.5 4.9 4.7 ns tPLH tPHL Propagation delay nAx to nBx or nBx to nAx 2 1.0 1.0 2.3 2.0 3.2 4.1 1.0 1.0 3.9 4.6 ns tPLH tPHL Propagation delay nSAB to nBx or nSBA to nAx 2, 3 1.0 1.0 3.1 2.7 4.3 4.3 1.0 1.0 5.0 5.0 ns tPZH tPZL Output enable time nOE to nAx or nBx 5, 6 1.0 1.5 3.2 3.3 4.6 4.9 1.0 1.5 5.5 5.7 ns tPHZ tPLZ Output disable time nOE to nAx or nBx 5, 6 1.5 1.5 3.5 2.7 4.9 4.1 1.5 1.5 5.4 4.5 ns tPZH tPZL Output enable time nDIR to nAx or nBx 5, 6 1.0 1.5 4.1 4.3 4.8 4.8 1.0 1.5 5.4 5.6 ns tPHZ tPLZ Output disable time nDIR to nAx or nBx 5, 6 2.0 1.5 3.6 2.7 5.7 5.1 2.0 1.5 6.7 5.9 ns AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT MIN TYP MIN 4 2.0 1.5 1.0 0.8 2.0 1.5 ns Hold time nAx to nCPAB, nBx to nCPBA 4 1.5 1.0 0.0 –0.7 1.5 1.0 ns Pulse width, High or Low nCPAB or nCPBA 1 4.5 3.0 2.5 2.0 4.5 3.0 ns ts(H) ts(L) Setup time nAx to nCPAB, nBx to nCPBA th(H) th(L) tw(H) tw(L) AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V 1/fMAX nCPBA or nCPAB VM 3.0V or VCC whichever is less VM 3.0V or VCC nSBA or nSAB VM VM nAx or nBx VM 0V tw(H) 0V tw(L) tPHL tPLH VOH tPLH VOH nAx or nBx tPHL VM nAx or nBx VM VM VM nAx or nBx VOL VOL SH00030 SH00031 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency 1998 Feb 27 Waveform 2. Propagation Delay, nSAB to nBx or nSBA to nAx, nAx to nBx or nBx to nAx 8 Philips Semiconductors Product specification 74ABT16646 74ABTH16646 16-bit bus transceiver/register (3-State) AC WAVEFORMS (Continued) VM = 1.5V, VIN = GND to 3.0V nSBA or nSAB VM 3.0V or VCC whichever is less nOE, nDIR 3.0V or VCC VM VM tPHL VM 0V nDIR 0V tPZH tPLH tPHZ VOH VOH nAx or nBx VM nAx or nBx VM VY VM VOL 0V SH00032 SH00034 Waveform 3. Propagation Delay, nSBA to nAx or nSAB to nBx Waveform 5. 3–State Output Enable Time to High Level and Output Disable Time from High Level ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ nAx or nBx VM VM VM 3.0V or VCC VM 3.0V or VCC nOE, nDIR 0V ts(H) ts(L) th(H) nCPBA or nCPAB VM th(L) VM VM nDIR 3.0V or VCC 0V tPZL tPLZ 3.0V or VCC VM 0V VM nAx or nBx NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VX VOL 0V SH00033 SH00035 Waveform 4. Data Setup and Hold Times Waveform 6. 3–State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORMS VCC 7.0V PULSE GENERATOR VOUT VIN tW 90% VM NEGATIVE PULSE CL 10% 0V RL tTHL (tF) tTLH (tR) tTLH (tR) tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. AMP (V) VM 10% RL D.U.T. RT 90% FAMILY 74ABT/H16 Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00018 1998 Feb 27 9 Philips Semiconductors Product specification 16-bit bus transceiver/register (3-State) SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 1998 Feb 27 10 74ABT16646 74ABTH16646 SOT371-1 Philips Semiconductors Product specification 16-bit bus transceiver/register (3-State) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Feb 27 11 74ABT16646 74ABTH16646 SOT364-1 Philips Semiconductors Product specification 74ABT16646 74ABTH16646 16-bit bus transceiver/register (3-State) Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 05-96 9397-750-03498