LINER LTC2288 Dual 10-bit, 65/40/25msps low noise 3v adc Datasheet

LTC2288/LTC2287/LTC2286
Dual 10-Bit, 65/40/25Msps
Low Noise 3V ADCs
U
FEATURES
DESCRIPTIO
■
The LTC®2288/LTC2287/LTC2286 are 10-bit 65Msps/
40Msps/25Msps, low noise dual 3V A/D converters designed for digitizing high frequency, wide dynamic range
signals. The LTC2288/LTC2287/LTC2286 are perfect for
demanding imaging and communications applications
with AC performance that includes 61.6dB SNR and 85dB
SFDR for signals well beyond the Nyquist frequency.
■
■
■
■
■
■
■
■
■
■
■
■
■
Integrated Dual 10-Bit ADCs
Sample Rate: 65Msps/40Msps/25Msps
Single 3V Supply (2.7V to 3.4V)
Low Power: 400mW/235mW/150mW
61.6dB SNR at 70MHz Input
85dB SFDR at 70MHz Input
110dB Channel Isolation at 100MHz
Multiplexed or Separate Data Bus
Flexible Input: 1VP-P to 2VP-P Range
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit)
65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit)
40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit)
25Msps: LTC2291 (12-Bit), LTC2286 (10-Bit)
64-Pin (9mm × 9mm) QFN Package
DC specs include ±0.1LSB INL (typ), ±0.05LSB DNL (typ)
and ±0.6 LSB INL, ±0.5 LSB DNL over temperature. The
transition noise is a low 0.07LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.3V
logic. An optional multiplexer allows both channels to
share one digital output bus.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
U
APPLICATIO S
■
■
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
U
TYPICAL APPLICATIO
+
ANALOG
INPUT A
INPUT
S/H
–
OVDD
10-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
LTC2288: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
D9A
•
••
D0A
62.5
OGND
CLK A
MUX
CLK B
CLOCK/DUTY CYCLE
CONTROL
OVDD
+
ANALOG
INPUT B
INPUT
S/H
–
10-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
SNR (dBFS)
61.5
CLOCK/DUTY CYCLE
CONTROL
60.5
59.5
58.5
D9B
•
••
D0B
OGND
57.5
0
100
50
150
INPUT FREQUENCY (MHz)
200
228876 TA02
228876 TA01
228876f
1
LTC2288/LTC2287/LTC2286
U
W
U
PACKAGE/ORDER I FOR ATIO
U
W W
W
ABSOLUTE
AXI U RATI GS
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation ............................................ 1500mW
Operating Temperature Range
LTC2288C, LTC2287C, LTC2286C ........... 0°C to 70°C
LTC2288I, LTC2287I, LTC2286I ..........–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
64 GND
63 VDD
62 SENSEA
61 VCMA
60 MODE
59 SHDNA
58 OEA
57 OFA
56 DA9
55 DA8
54 DA7
53 DA6
52 DA5
51 DA4
50 OGND
49 OVDD
TOP VIEW
AINA+ 1
AINA– 2
REFHA 3
REFHA 4
REFLA 5
REFLA 6
VDD 7
CLKA 8
CLKB 9
VDD 10
REFLB 11
REFLB 12
REFHB 13
REFHB 14
AINB– 15
AINB+ 16
48 DA3
47 DA2
46 DA1
45 DA0
44 NC
43 NC
42 NC
41 NC
40 OFB
39 DB9
38 DB8
37 DB7
36 DB6
35 DB5
34 DB4
33 DB3
GND 17
VDD 18
SENSEB 19
VCMB 20
MUX 21
SHDNB 22
OEB 23
NC 24
NC 25
NC 26
NC 27
DB0 28
DB1 29
DB2 30
OGND 31
OVDD 32
65
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 125°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB
ORDER PART
NUMBER
QFN PART*
MARKING
LTC2288CUP
LTC2288IUP
LTC2287CUP
LTC2287IUP
LTC2286CUP
LTC2286IUP
LTC2288UP
LTC2287UP
LTC2286UP
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
U
CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
Resolution
(No Missing Codes)
Integral Linearity Error
Differential
Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
CONDITIONS
●
Differential Analog Input (Note 5)
Differential Analog Input
●
(Note 6)
External Reference
●
Internal Reference
External Reference
External Reference
SENSE = 1V
●
●
MIN
10
LTC2288
TYP
MAX
MIN
10
LTC2287
TYP
MAX
MIN
10
LTC2286
TYP
MAX
UNITS
Bits
–0.6
–0.5
±0.1
±0.05
0.6
0.5
–0.6
–0.5
±0.1
±0.05
0.6
0.5
–0.6
–0.5
±0.1
±0.05
0.6
0.5
LSB
LSB
–12
–2.5
±2
±0.5
±10
±30
±15
±0.3
±2
0.07
12
2.5
–12
–2.5
±2
±0.5
±10
±30
±15
±0.3
±2
0.07
12
2.5
–12
–2.5
±2
±0.5
±10
±30
±15
±0.3
±2
0.07
12
2.5
mV
%FS
µV/°C
ppm/°C
ppm/°C
%FS
mV
LSBRMS
228876f
2
LTC2288/LTC2287/LTC2286
U
U
A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ –AIN–)
2.7V < VDD < 3.4V (Note 7)
●
VIN,CM
Analog Input Common Mode
Differential Input (Note 7)
●
1
1.9
V
IIN
Analog Input Leakage Current
0V < AIN+, AIN– < VDD
●
–1
1
µA
ISENSE
SENSEA, SENSEB Input Leakage
0V < SENSEA, SENSEB < 1V
●
–3
3
µA
IMODE
MODE Input Leakage Current
0V < MODE < VDD
●
–3
3
µA
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
CMRR
MIN
TYP
MAX
UNITS
1V to 2V
1.5
V
0
0.2
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
Figure 8 Test Circuit
ns
psRMS
80
dB
575
MHz
W U
DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
SNR
Signal-to-Noise Ratio
SFDR
SFDR
S/(N+D)
IMD
Spurious Free
Dynamic Range
2nd or 3rd
Harmonic
Spurious Free
Dynamic Range
4th Harmonic
or Higher
Signal-to-Noise
Plus Distortion
Ratio
CONDITIONS
MIN
5MHz Input
LTC2288
TYP
MAX
MIN
61.8
12.5MHz Input
●
20MHz Input
●
30MHz Input
●
LTC2287
TYP
MAX
MIN
61.8
60
60
60
LTC2286
TYP
MAX
UNITS
61.8
dB
61.8
dB
61.8
dB
61.8
dB
70MHz Input
61.7
61.7
61.6
dB
140MHz Input
61.6
61.6
61.6
dB
85
85
5MHz Input
12.5MHz Input
●
20MHz Input
●
30MHz Input
●
69
69
69
85
dB
85
dB
85
dB
85
dB
70MHz Input
85
85
85
dB
140MHz Input
80
80
80
dB
85
85
5MHz Input
12.5MHz Input
●
20MHz Input
●
30MHz Input
●
74
74
74
85
dB
85
dB
85
dB
85
dB
70MHz Input
85
85
85
dB
140MHz Input
85
85
85
dB
61.8
61.8
5MHz Input
12.5MHz Input
●
20MHz Input
●
30MHz Input
●
60
60
60
61.8
dB
61.8
dB
61.7
dB
61.8
dB
70MHz Input
61.7
61.6
61.6
dB
140MHz Input
61.6
61.6
61.5
dB
85
85
85
dB
–110
–110
–110
dB
Intermodulation
Distortion
fIN = Nyquist,
Nyquist + 1MHz
Crosstalk
fIN = Nyquist
228876f
3
LTC2288/LTC2287/LTC2286
U U
U
I TER AL REFERE CE CHARACTERISTICS
(Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM Output Voltage
IOUT = 0
1.475
1.500
1.525
V
VCM Output Tempco
ppm/°C
±30
VCM Line Regulation
2.7V < VDD < 3.3V
3
mV/V
VCM Output Resistance
–1mA < IOUT < 1mA
4
Ω
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.8
V
10
µA
LOGIC INPUTS (CLK, OE, SHDN, MUX)
VIH
High Level Input Voltage
VDD = 3V
●
VIL
Low Level Input Voltage
VDD = 3V
●
IIN
Input Current
VIN = 0V to VDD
●
CIN
Input Capacitance
(Note 7)
2
V
–10
3
pF
LOGIC OUTPUTS
OVDD = 3V
COZ
Hi-Z Output Capacitance
OE = High (Note 7)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = 3V
50
mA
VOH
High Level Output Voltage
IO = –10µA
IO = –200µA
●
IO = 10µA
IO = 1.6mA
●
VOL
Low Level Output Voltage
2.7
2.995
2.99
0.005
0.09
V
V
0.4
V
V
OVDD = 2.5V
VOH
High Level Output Voltage
IO = –200µA
2.49
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
VOH
High Level Output Voltage
IO = –200µA
1.79
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
OVDD = 1.8V
228876f
4
LTC2288/LTC2287/LTC2286
U W
POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
MIN
LTC2288
TYP
MAX
MIN
LTC2287
TYP
MAX
MIN
LTC2286
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
UNITS
VDD
Analog Supply
Voltage
(Note 9)
●
2.7
3
3.4
2.7
3
3.4
2.7
3
3.4
V
OVDD
Output Supply
Voltage
(Note 9)
●
0.5
3
3.6
0.5
3
3.6
0.5
3
3.6
V
IVDD
Supply Current
Both ADCs at fS(MAX)
●
133
150
78
95
50
60
mA
PDISS
Power Dissipation
Both ADCs at fS(MAX)
●
400
450
235
285
150
180
mW
PSHDN
Shutdown Power
(Each Channel)
SHDN = H,
OE = H, No CLK
2
2
2
mW
PNAP
Nap Mode Power
(Each Channel)
SHDN = H,
OE = L, No CLK
15
15
15
mW
WU
TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
CONDITIONS
MIN
LTC2288
TYP
MAX
MIN
LTC2287
TYP
MAX
PARAMETER
fs
Sampling Frequency (Note 9)
●
1
65
1
40
1
25
MHz
tL
CLK Low Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
●
●
7.3
5
7.7
7.7
500
500
11.8
5
12.5
12.5
500
500
18.9
5
20
20
500
500
ns
ns
tH
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
●
●
7.3
5
7.7
7.7
500
500
11.8
5
12.5
12.5
500
500
18.9
5
20
20
500
500
ns
ns
tAP
Sample-and-Hold
Aperture Delay
tD
CLK to DATA Delay
CL = 5pF (Note 7)
●
1.4
2.7
5.4
1.4
2.7
5.4
1.4
2.7
5.4
ns
tMD
MUX to DATA Delay CL = 5pF (Note 7)
●
1.4
2.7
5.4
1.4
2.7
5.4
1.4
2.7
5.4
ns
Data Access Time
After OE↓
●
4.3
10
4.3
10
4.3
10
ns
●
3.3
8.5
3.3
8.5
3.3
8.5
0
CL = 5pF (Note 7)
BUS Relinquish Time (Note 7)
Pipeline
Latency
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 65MHz (LTC2288), 40MHz (LTC2287), or
25MHz (LTC2286), input range = 2VP-P with differential drive, unless
otherwise noted.
6
MIN
LTC2286
TYP
MAX
SYMBOL
0
6
0
6
UNITS
ns
ns
Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 and 11 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 65MHz (LTC2288), 40MHz (LTC2287), or
25MHz (LTC2286), input range = 1VP-P with differential drive. The supply
current and power dissipation are the sum total for both channels with
both channels active.
Note 9: Recommended operating conditions.
228876f
5
LTC2288/LTC2287/LTC2286
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2288/LTC2287/LTC2286:
Crosstalk vs Input Frequency
LTC2288: Typical INL,
2V Range, 65Msps
INL ERROR (LSB)
CROSSTALK (dB)
–105
–110
–115
–120
–125
–130
1.00
1.00
0.75
0.75
0.50
0.50
0.25
0
–0.25
20
–0.25
–0.75
–0.75
–1.00
0
256
512
1024
768
LTC2288: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
65Msps
0
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–70
–80
AMPLITUDE (dB)
0
–10
AMPLITUDE (dB)
0
–60
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
20
15
10
25
FREQUENCY (MHz)
–120
0
30
5
20
15
10
25
FREQUENCY (MHz)
0
–10
–20
–20
–30
–30
–40
–40
–80
70000
–70
–80
–100
–100
–110
–110
5
20
15
10
25
FREQUENCY (MHz)
30
228876 G07
40000
30000
20000
10000
0
–120
0
65520
50000
–50
–90
30
60000
–60
–90
–120
20
15
10
25
FREQUENCY (MHz)
LTC2288: Grounded Input
Histogram, 65Msps
COUNT
AMPLITUDE (dB)
AMPLITUDE (dB)
0
–70
5
228876 G06
LTC2288: 8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz,
–1dB, 2V Range 65Msps
–10
–50
0
30
228876 G05
228876 G04
LTC2288: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
65Msps
–60
1024
768
22876 G03
LTC2288: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
65Msps
–50
512
CODE
–10
5
256
228876 G02
LTC2288: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
65Msps
0
0
CODE
228876 G01
AMPLITUDE (dB)
0
–0.50
100
40
60
80
INPUT FREQUENCY (MHz)
0.25
–0.50
–1.00
0
DNL ERROR (LSB)
–100
LTC2288: Typical DNL,
2V Range, 65Msps
0
5
20
15
10
25
FREQUENCY (MHz)
30
228876 G08
0
0
511
512
CODE
513
228876 G09
228876f
6
LTC2288/LTC2287/LTC2286
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2288: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
LTC2288: SNR and SFDR vs
Sample Rate, 2V Range,
fIN = 5MHz, –1dB
LTC2288: SFDR vs Input Frequency,
–1dB, 2V Range, 65Msps
100
62.5
100
SFDR
95
90
SNR AND SFDR (dBFS)
61.5
SFDR (dBFS)
60.5
59.5
85
80
75
58.5
65
100
50
150
INPUT FREQUENCY (MHz)
50
0
200
100
200
150
INPUT FREQUENCY (MHz)
70
SNR
50
0 10 20 30 40 50 60 70 80 90 100 110
SAMPLE RATE (Msps)
228876 G11
228876 G10
LTC2288: SNR vs Input Level,
fIN = 30MHz, 2V Range, 65Msps
228876 G12
LTC2288: SFDR vs Input Level,
fIN = 30MHz, 2V Range, 65Msps
80
120
110
70
dBFS
100
SFDR (dBc AND dBFS)
60
50
dBc
40
30
20
dBFS
90
80
70
dBc
60
50
80dBc SFDR
REFERENCE LINE
40
30
20
10
10
0
–60
–50
–40
–20
–30
INPUT LEVEL (dBFS)
–10
0
–60
0
–50
–40
–30
–20
INPUT LEVEL (dBFS)
228876 G13
0
228876 G14
LTC2288: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
155
12
145
10
135
8
1V RANGE
125
2V RANGE
6
115
4
105
2
95
–10
LTC2288: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
IOVDD (mA)
0
SNR (dBc AND dBFS)
57.5
80
60
70
IVDD (mA)
SNR (dBFS)
90
0
10
20 30 40 50 60
SAMPLE RATE (Msps)
70
80
228876 G15
0
0
10
20 30 40 50 60
SAMPLE RATE (Msps)
70
80
228876 G16
228876f
7
LTC2288/LTC2287/LTC2286
U W
TYPICAL PERFOR A CE CHARACTERISTICS
1.00
0.75
0.75
0.50
0.50
0.25
0
–0.25
0
–0.25
–0.50
–0.75
–0.75
–1.00
–1.00
512
1024
768
–20
0.25
–0.50
256
0
–10
AMPLITUDE (dB)
1.00
0
LTC2287: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
40Msps
LTC2287: Typical DNL,
2V Range, 40Msps
DNL ERROR (LSB)
INL ERROR (LSB)
LTC2287: Typical INL,
2V Range, 40Msps
–60
–70
–80
–100
–110
0
256
512
–120
1024
768
228876 G19
0
–10
–20
–30
–40
–70
–80
AMPLITUDE (dB)
–20
–30
–40
AMPLITUDE (dB)
–20
–30
–40
–60
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
–120
10
20
15
0
5
FREQUENCY (MHz)
10
20
15
0
FREQUENCY (MHz)
5
10
15
228876 G21
228876 G22
LTC2287: Grounded Input
Histogram, 40Msps
0
–10
70000
–20
60000
–30
–40
50000
–50
40000
20
FREQUENCY (MHz)
228876 G20
LTC2287: 8192 Point 2-Tone FFT,
fIN = 21.6MHz and 23.6MHz,
–1dB, 2V Range, 40Msps
20
15
LTC2287: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
40Msps
0
–10
–50
10
228876 G18
LTC2287: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
40Msps
0
–10
5
5
FREQUENCY (MHz)
228876 G17
0
0
CODE
LTC2287: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
40Msps
AMPLITUDE (dB)
–50
–90
CODE
LTC2287: SNR vs Input Frequency,
–1dB, 2V Range, 40Msps
62.5
65520
–60
–70
SNR (dBFS)
61.5
COUNT
AMPLITUDE (dB)
–30
–40
30000
60.5
59.5
–80
20000
–90
–100
–110
–120
58.5
10000
0
0
5
10
15
20
FREQUENCY (MHz)
228876 G23
0
0
510
511
CODE
512
228876 G24
57.5
0
100
50
150
INPUT FREQUENCY (MHz)
200
228876 G25
228876f
8
LTC2288/LTC2287/LTC2286
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2287: SNR and SFDR vs
Sample Rate, 2V Range,
fIN = 5MHz, –1dB
LTC2287: SFDR vs Input Frequency,
–1dB, 2V Range, 40Msps
100
LTC2287: SNR vs Input Level,
fIN = 5MHz, 2V Range, 40Msps
100
80
SFDR
95
70
dBFS
SFDR (dBFS)
90
85
80
75
60
SNR (dBc AND dBFS)
SNR AND SFDR (dBFS)
90
80
70
SNR
50
30
20
60
70
dBc
40
10
65
50
0
100
50
200
150
INPUT FREQUENCY (MHz)
0
10
20 30 40 50 60
SAMPLE RATE (Msps)
228876 G26
70
0
–60
80
–50
–20
–40
–30
INPUT LEVEL (dBFS)
228876 G27
228876 G28
LTC2287: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
LTC2287: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2287: SFDR vs Input Level,
fIN = 5MHz, 2V Range, 40Msps
120
0
–10
100
8
90
6
110
90
70
dBc
60
80dBc SFDR
REFERENCE LINE
50
IOVDD (mA)
dBFS
80
IVDD (mA)
SFDR (dBc AND dBFS)
100
2V RANGE
80
40
4
1V RANGE
2
70
30
20
10
0
–60
60
–50
–40
–30
–20
–10
0
0
0
INPUT LEVEL (dBFS)
10
30
40
20
SAMPLE RATE (Msps)
LTC2286: Typical INL,
2V Range, 25Msps
1.00
0.50
0.50
0
0
–0.25
–0.50
–0.75
–0.75
–1.00
–1.00
0
256
512
768
1024
CODE
–20
–30
0.25
–0.50
50
–10
AMPLITUDE (dB)
0.75
DNL ERROR (LSB)
0.75
–0.25
30
40
20
SAMPLE RATE (Msps)
228876 G31
1.00
0
10
LTC2286: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
25Msps
LTC2286: Typical DNL,
2V Range, 25Msps
0.25
0
228876 G30
228876 G29
INL ERROR (LSB)
50
–40
–50
–60
–70
–80
–90
–100
–110
0
256
512
768
1024
CODE
–120
0
2
8
6
4
10
FREQUENCY (MHz)
12
228876 G32
228876 G33
228876 G34
228876f
9
LTC2288/LTC2287/LTC2286
U W
TYPICAL PERFOR A CE CHARACTERISTICS
0
0
0
–10
–10
–10
–20
–20
–30
–30
–30
–40
–40
–40
–50
–60
–70
–80
AMPLITUDE (dB)
–20
AMPLITUDE (dB)
AMPLITUDE (dB)
LTC2286: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
25Msps
LTC2286: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
25Msps
LTC2286: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
25Msps
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
0
8
6
4
10
FREQUENCY (MHz)
2
0
12
8
6
4
10
FREQUENCY (MHz)
2
–120
12
0
2
8
6
4
10
FREQUENCY (MHz)
228876 G36
228876 G35
LTC2286: 8192 Point 2-Tone FFT,
fIN = 10.9MHz and 13.8MHz,
–1dB, 2V Range, 25Msps
228876 G37
LTC2286: Grounded Input
Histogram, 25Msps
70000
0
12
LTC2286: SNR vs Input Frequency,
–1dB, 2V Range, 25Msps
62.5
65520
–10
60000
–20
61.5
50000
–50
–60
–70
–80
SNR (dBFS)
–40
COUNT
AMPLITUDE (dB)
–30
40000
30000
59.5
20000
–90
–100
58.5
10000
–110
0
8
6
4
10
FREQUENCY (MHz)
2
0
0
0
–120
511
12
512
CODE
57.5
513
LTC2286: SFDR vs Input
Frequency, –1dB, 2V Range,
25Msps
100
LTC2286: SNR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
100
80
SFDR
95
70
80
75
SNR (dBc AND dBFS)
SNR AND SFDR (dBFS)
90
85
200
228876 G40
LTC2286: SNR and SFDR vs
Sample Rate, 2V Range,
fIN = 5MHz, –1dB
90
100
50
150
INPUT FREQUENCY (MHz)
0
228876 G39
228876 G38
SFDR (dBFS)
60.5
80
70
SNR
dBFS
60
50
dBc
40
30
20
60
70
10
65
0
50
100
150
INPUT FREQUENCY (MHz)
200
228876 G41
50
0
5
10 15 20 25 30 35 40 45 50
SAMPLE RATE (Msps)
228876 G42
0
–60
–50
–40
–20
–30
INPUT LEVEL (dBFS)
–10
0
228876 G43
228876f
10
LTC2288/LTC2287/LTC2286
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2286: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
LTC2286: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2286: SFDR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
70
120
6
110
60
dBFS
80
4
70
60
dBc
50
80dBc SFDR
REFERENCE LINE
40
IOVDD (mA)
90
IVDD (mA)
SFDR (dBc AND dBFS)
100
2V RANGE
50
1V RANGE
2
40
30
20
10
0
–60
30
–50
–40
–30
–20
INPUT LEVEL (dBFS)
–10
0
0
5
25
20
15
10
SAMPLE RATE (Msps)
228876 G44
30
35
0
0
5
25
20
15
10
SAMPLE RATE (Msps)
228876 G45
30
35
228876 G46
U
U
U
PI FU CTIO S
AINA+ (Pin 1): Channel A Positive Differential Analog
Input.
AINA– (Pin 2): Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.
AINB– (Pin 15): Channel B Negative Differential Analog
Input.
AINB+ (Pin 16): Channel B Positive Differential Analog
Input.
GND (Pins 17, 64): ADC Power Ground.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to VCMB selects the internal reference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of ±VSENSEB. ±1V is the largest valid input range.
VCMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to VCMA.
228876f
11
LTC2288/LTC2287/LTC2286
U
U
U
PI FU CTIO S
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13, OFA; Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal operation with the outputs at high impedance. Connecting
SHDNB to VDD and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to VDD
and OEB to VDD results in sleep mode with the outputs at
high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24 to 27, 41 to 44): Do Not Connect These Pins.
DB0 – DB9 (Pins 28 to 30, 33 to 39): Channel B Digital
Outputs. DB9 is the MSB.
OGND (Pins 31, 50): Output Driver Ground.
OVDD (Pins 32, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor.
OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA9 (Pins 45 to 48, 51 to 56): Channel A Digital
Outputs. DA9 is the MSB.
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting
SHDNA to VDD and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to VDD
and OEA to VDD results in sleep mode with the outputs at
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects straight binary output format and turns the clock duty cycle stabilizer
off. 1/3 VDD selects straight binary output format and turns
the clock duty cycle stabilizer on. 2/3 VDD selects 2’s
complement output format and turns the clock duty cycle
stabilizer on. VDD selects 2’s complement output format
and turns the clock duty cycle stabilizer off.
VCMA (Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to VCMB.
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to VCMA selects the internal reference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of ±VSENSEA. ±1V is the largest valid input range.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
228876f
12
LTC2288/LTC2287/LTC2286
W
FUNCTIONAL BLOCK DIAGRA
U
U
AIN+
AIN–
VCM
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
1.5V
REFERENCE
SIXTH PIPELINED
ADC STAGE
SHIFT REGISTER
AND CORRECTION
2.2µF
RANGE
SELECT
REFH
SENSE
REFL
INTERNAL CLOCK SIGNALS
OVDD
REF
BUF
OF
D9
CLOCK/DUTY
CYCLE
CONTROL
DIFF
REF
AMP
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
D0
REFH
0.1µF
228876 F01
REFL
OGND
CLK
MODE
SHDN
OE
2.2µF
1µF
1µF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
228876f
13
LTC2288/LTC2287/LTC2286
W
UW
TI I G DIAGRA S
Dual Digital Output Bus Timing
(Only One Channel is Shown)
tAP
N+4
N+2
N
ANALOG
INPUT
N+1
tH
N+3
N+5
tL
CLK
tD
N–5
N–6
D0-D9, OF
N–4
N–3
N–2
N–1
228876 TD01
Multiplexed Digital Output Bus Timing
tAPA
ANALOG
INPUT A
A+4
A+2
A
A+1
A+3
tAPB
ANALOG
INPUT B
B+4
B+2
B
B+1
tH
tL
A–6
B–6
B+3
CLKA = CLKB = MUX
D0A-D9A, OFA
A–5
tD
D0B-D9B, OFB
B–6
B–5
A–4
B–4
A–3
B–3
B–4
A–4
B–3
A–3
A–2
t MD
A–6
B–5
A–5
B–2
228876 TD02
228876f
14
LTC2288/LTC2287/LTC2286
U
W
U U
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log √(V22 + V32 + V42 + . . . Vn2)/V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Aperture Delay Time
The time from when CLK reaches midsupply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π) • fIN • tJITTER
Intermodulation Distortion
Crosstalk
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
CONVERTER OPERATION
As shown in Figure 1, the LTC2288/LTC2287/LTC2286 are
dual CMOS pipelined multistep converters. The converters have six pipelined ADC stages; a sampled analog input
will result in a digitized value six cycles later (see the
Timing Diagram section). For optimal AC performance the
analog inputs should be driven differentially. For cost
228876f
15
LTC2288/LTC2287/LTC2286
U
U
W
U
APPLICATIO S I FOR ATIO
sensitive applications, the analog inputs can be driven
single-ended with slightly worse harmonic distortion. The
CLK input is single-ended. The LTC2288/LTC2287/
LTC2286 have two phases of operation, determined by the
state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2288/
LTC2287/LTC2286 CMOS differential sample-and-hold.
The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors
shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
LTC2288/LTC2287/LTC2286
VDD
AIN+
CPARASITIC
1pF
VDD
AIN–
CSAMPLE
4pF
15Ω
CSAMPLE
4pF
15Ω
CPARASITIC
1pF
VDD
CLK
228876 F02
Figure 2. Equivalent Input Circuit
228876f
16
LTC2288/LTC2287/LTC2286
U
W
U U
APPLICATIO S I FOR ATIO
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin may
be used to provide the common mode bias level. VCM can
be tied directly to the center tap of a transformer to set the
DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2288/LTC2287/LTC2286 being
driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM,
setting the ADC input signal at its optimum DC level.
Terminating on the transformer secondary is desirable, as
this provides a common mode path for charging glitches
caused by the sample and hold. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedance seen by the ADC does not exceed 100Ω
for each ADC input. A disadvantage of using a transformer
is the loss of low frequency response. Most small RF
transformers have poor performance at frequencies below 1MHz.
VCM
2.2µF
0.1µF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
0.1µF
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2288/LTC2287/LTC2286
can be influenced by the input drive circuitry, particularly
the second and third harmonics. Source impedance and
reactance can influence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 4pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when CLK rises, holding the
sampled input on the sampling capacitor. Ideally the input
circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
AIN+
LTC2288
LTC2287
LTC2286
12pF
25Ω
T1 = MA/COM ETC1-1T 25Ω
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
228876 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
228876f
17
LTC2288/LTC2287/LTC2286
U
W
U U
APPLICATIO S I FOR ATIO
VCM
HIGH SPEED
DIFFERENTIAL
25Ω
AMPLIFIER
ANALOG
INPUT
+
–
2.2µF
AIN+
+
CM
VCM
2.2µF
0.1µF
LTC2288
LTC2287
LTC2286
25Ω
25Ω
0.1µF
AIN–
AIN+
0.1µF
T1
12pF
–
12Ω
ANALOG
INPUT
LTC2288
LTC2287
LTC2286
8pF
25Ω
12Ω
AIN–
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
228876 F04
228876 F06
Figure 4. Differential Drive with an Amplifier
Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
VCM
2.2µF
VCM
1k
0.1µF
ANALOG
INPUT
0.1µF
1k
AIN+
ANALOG
INPUT
2.2µF
25Ω
25Ω
AIN+
0.1µF
25Ω
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
0.1µF
LTC2288
LTC2287
LTC2286
T1
LTC2288
LTC2287
LTC2286
12pF
25Ω
0.1µF
AIN–
228876 F07
228876 F05
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
Figure 5. Single-Ended Drive
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux
coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In
Figure 8, the series inductors are impedance matching
elements that maximize the ADC bandwidth.
VCM
2.2µF
0.1µF
6.8nH
ANALOG
INPUT
25Ω
AIN+
0.1µF
LTC2288
LTC2287
LTC2286
T1
0.1µF
25Ω
6.8nH
AIN
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
–
228876 F08
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
228876f
18
LTC2288/LTC2287/LTC2286
U
W
U U
APPLICATIO S I FOR ATIO
Reference Operation
Figure 9 shows the LTC2288/LTC2287/LTC2286 reference circuitry consisting of a 1.5V bandgap reference, a
difference amplifier and switching and control circuit. The
internal voltage reference can be configured for two pin
selectable input ranges of 2V (±1V differential) or 1V
(±0.5V differential). Tying the SENSE pin to VDD selects
the 2V range; tying the SENSE pin to VCM selects the 1V
range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9. Each
ADC channel has an independent reference with its own
bypass capacitors. The two channels can be used with the
same or different input ranges.
Other voltage ranges between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
For the best channel matching, connect an external reference
to SENSEA and SENSEB.
LTC2288/LTC2287/LTC2286
1.5V
VCM
4Ω
1.5V
1.5V BANDGAP
REFERENCE
2.2µF
2.2µF
12k
0.5V
1V
0.75V
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
RANGE
DETECT
AND
CONTROL
12k
BUFFER
0.1µF
LTC2288
LTC2287
LTC2286
1µF
Figure 10. 1.5V Range ADC
INTERNAL ADC
HIGH REFERENCE
Input Range
REFH
2.2µF
SENSE
228876 F10
SENSE
1µF
VCM
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 0.6dB. See the Typical Performance Characteristics section.
DIFF AMP
1µF
REFL
INTERNAL ADC
LOW REFERENCE
228876 F09
Figure 9. Equivalent Reference Circuit
Driving the Clock Input
The CLK inputs can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low jitter squaring circuit before the CLK pin (Figure 11).
228876f
19
LTC2288/LTC2287/LTC2286
U
W
U U
APPLICATIO S I FOR ATIO
CLEAN
SUPPLY
4.7µF
FERRITE
BEAD
0.1µF
SINUSOIDAL
CLOCK
INPUT
0.1µF
1k
CLK
50Ω
1k
LTC2288
LTC2287
LTC2286
NC7SVU04
228876 F11
Figure 11. Sinusoidal Single-Ended CLK Drive
The noise performance of the LTC2288/LTC2287/LTC2286
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this delay exceeds 1ns, the
performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2288/LTC2287/
LTC2286 is 65Msps (LTC2288), 40Msps (LTC2287), and
25Msps (LTC2286). For the ADC to operate properly, the
CLK signal should have a 50% (±5%) duty cycle. Each half
cycle must have at least 7.3ns (LTC2288), 11.8ns
(LTC2287), and 18.9ns (LTC2286) for the ADC internal
circuitry to have enough settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary from 40% to 60% and the
clock duty cycle stabilizer will maintain a constant 50%
internal duty cycle. If the clock is turned off for a long
period of time, the duty cycle stabilizer circuit will require
a hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3VDD or 2/3VDD using external
resistors. The MODE pin controls both Channel A and
Channel B—the duty cycle stabilizer is either on or off for
both channels.
The lower limit of the LTC2288/LTC2287/LTC2286 sample
rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on
storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified
minimum operating frequency for the LTC2288/LTC2287/
LTC2286 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital
outputs of the LTC2288/LTC2287/LTC2286 should drive a
minimal capacitive load to avoid possible interaction
228876f
20
LTC2288/LTC2287/LTC2286
U
W
U
U
APPLICATIO S I FOR ATIO
LTC2288/LTC2287/LTC2286
VDD
OVDD
0.5V
TO VDD
VDD
0.1µF
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
228876 F12
Figure 12. Digital Output Buffer
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Overflow Bit
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Output Driver Power
Data Format
Using the MODE pin, the LTC2288/LTC2287/LTC2286
parallel digital output can be selected for offset binary or
2’s complement format. Note that MODE controls both
Channel A and Channel B. Connecting MODE to GND or
1/3VDD selects straight binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 1 shows the logic
states for the MODE pin.
Table 1. MODE Pin Function
MODE Pin
Output Format
Clock Duty
Cycle Stabilizer
0
Straight Binary
Off
1/3VDD
Straight Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
When OF outputs a logic high the converter is either
overranged or underranged.
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data access and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long
periods of inactivity. Channels A and B have independent
output enable pins (OEA, OEB).
228876f
21
LTC2288/LTC2287/LTC2286
U
W
U
U
APPLICATIO S I FOR ATIO
Sleep and Nap Modes
Grounding and Bypassing
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
The LTC2288/LTC2287/LTC2286 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA, and
Channel B is controlled by SHDNB and OEB. The nap, sleep
and output enable modes of the two channels are completely
independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode.
Digital Output Mulitplexer
The digital outputs of the LTC2288/LTC2287/LTC2286 can
be multiplexed onto a single data bus. The MUX pin is a
digital input that swaps the two data busses. If MUX is High,
Channel A comes out on DA0-DA9, OFA; Channel B comes
out on DB0-DB9, OFB. If MUX is Low, the output busses
are swapped and Channel A comes out on DB0-DB9, OFB;
Channel B comes out on DA0-DA9, OFA. To multiplex both
channels onto a single output bus, connect MUX, CLKA and
CLKB together (see the Timing Diagram for the multiplexed
mode). The multiplexed data is available on either data
bus—the unused data bus can be disabled with its OE pin.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
ceramic capacitor is recommended. The large 2.2µF capacitor between REFH and REFL can be somewhat further
away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as
possible.
The LTC2288/LTC2287/LTC2286 differential inputs should
run parallel and close to each other. The input traces
should be as short as possible to minimize capacitance
and to minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTC2288/LTC2287/
LTC2286 is transferred from the die through the bottomside exposed pad and package leads onto the printed
circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large
grounded pad on the PC board. It is critical that all ground
pins are connected to a ground plane of sufficient area.
228876f
22
J3
CLOCK
INPUT
R14
49.9Ω
C19
0.1µF
VDD
R15
1k
R10
1k
L1
BEAD
VCMA
C7
0.1µF
J4
ANALOG
R17
INPUT B
OPT
U6
NC7SVU04
VCM
VDD
4
2
EXT REF
5
6
3
1
4
R8
51
R32
22Ω
VCMB
C33
0.1µF
5
•
R23
51
•3
2
C29
T2
0.1µF ETC1-1T
4
1
R16
33Ω
C17
0.1µF
VDD
R7
24.9Ω
R6
24.9Ω
R5
24.9Ω
C6
12pF
R24
24.9Ω
C34
0.1µF
R22
24.9Ω
C31
12pF
C23 1µF
VDD
C21
0.1µF
C11
0.1µF
C4
0.1µF
VCMB
VDD
VCMB
8
6
4
2
E2
EXT
REF B
VDD
GND
1/3VDD
2/3VDD
C20
2.2µF
C18 1µF
R20
24.9Ω
7
5
3
1
C10
2.2µF
C9 1µF
R3
1k
R2
1k
R1
1k
C13 1µF
R18
24.9Ω
C44
0.1µF
R9
24.9Ω
C8
0.1µF
C14
0.1µF
VDD
•3
C13
0.1µF
•
2
C3
T1
0.1µF ETC1-1T
5
1
C15
0.1µF
C12
4.7µF
6.3V
U3
NC7SVU04
J2
ANALOG R4
INPUT A OPT
VCMA
E1
EXT
REF A
VDD
JP2 SENSE A
VDD
JP1 MODE
AINA+
AINA–
REFHA
REFHA
REFLA
REFLA
VDD
CLKA
CLKB
VDD
REFLB
REFLB
REFHB
REFHB
AINB–
AINB+
VCM
4
2
EXT REF
5
6
3
1
VDD
C2
2.2µF
C27
0.1µF
JP3 SENSE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C1
0.1µF
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
U1
LTC2288
GND
VDD
SENSEA
VCMA
MODE
SHDNA
OEA
OFA
DA9
DA8
DA7
DA6
DA5
DA4
OGND
OVDD
C35
0.1µF
C28
2.2µF
VDD
C37
10µF
6.3V
R26
100k
R25
105k
VCC
U8
LT1763
1
IN
OUT
2
ADJ GND
3
GND GND
4
BYP SHDN
C25
0.1µF
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
DA3
DA2
DA1
DA0
NC
NC
NC
NC
OFB
DB9
DB8
DB7
DB6
DB5
DB4
DB3
VCC
C5
0.1µF
C38
0.01µF
GND
VDD
SENSEB
VCMB
MUX
SHDNB
OEB
NC
NC
NC
NC
DB0
DB1
DB2
OGND
OVDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
5
6
8
7
VDD
C39
1µF
R31
TBD
R27
TBD
VCC
VCC
U10
NC7SV86P5X
VCC
VDD
C40
0.1µF
E4
GND
U4
NC7SV86P5X
E3
VDD
3V
VCC
R29
51Ω
8
VCC
7
WP
6
SCL
5
SDA
R12
10k
C30
18pF
L2
47nH
R30
15Ω
R11
10k
RN4B 33Ω
RN4C 33Ω
RN4D 33Ω
RN3A 33Ω
RN3B 33Ω
RN3C 33Ω
RN3D 33Ω
RN2A 33Ω
RN2B 33Ω
RN2C 33Ω
RN2D 33Ω
RN1A 33Ω
RN1B 33Ω
RN1D 33Ω
RN1C 33Ω
C16 0.1µF
U5
24LC025
1
A0
2
A1
3
A2
4
A3
U7
NC7SV86P5X
C26
0.1µF
C24
0.1µF
C41
0.1µF
C36
E5
4.7µF
PWR
GND
VCC
74VCX245BQX
20
VCC
18
2
A0
B0
17
3
A1
B1
16
4
B2
A2
15
5
A3
B3
14
6
B4
A4
13
7
A5
B5
12
8
A6
B6
11
9
B7
A7
1
T/R
19
10
OE GND
VCC
74VCX245BQX
20
VCC
18
2
A0
B0
17
3
A1
B1
16
4
B2
A2
15
5
A3
B3
14
6
B4
A4
13
7
A5
B5
12
8
A6
B6
11
9
A7
B7
1
T/R
19
10
OE GND
C32
18pF
L3
47nH
R13
10k
C42
8.2pF
L4
47nH
9
7
7
5
5
3
3
1
1
12
10
16
14
18
20
24
22
26
34
32
30
28
40
38
36
228876 AI01
C43
8.2pF
R28
24Ω
8
8
6
6
4
4
2
2
10
3201S-40G1
39
40
39
37
38
37
35
35
36
33
34
33
31
31
32
29
30
29
27
27
28
25
25
26
23
23
24
21
21
22
19
19
20
17
17
18
15
15
16
13
13
14
11
11
12
9
U
U
W
VDD
APPLICATIO S I FOR ATIO
U
VCC
LTC2288/LTC2287/LTC2286
228876f
23
LTC2288/LTC2287/LTC2286
U
W
U
U
APPLICATIO S I FOR ATIO
Silkscreen Top
Top Side
228876f
24
LTC2288/LTC2287/LTC2286
U
W
U
U
APPLICATIO S I FOR ATIO
Inner Layer 2 GND
Inner Layer 3 Power
228876f
25
LTC2288/LTC2287/LTC2286
U
W
U
U
APPLICATIO S I FOR ATIO
Bottom Side
228876f
26
LTC2288/LTC2287/LTC2286
U
PACKAGE DESCRIPTIO
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705)
0.70 ±0.05
7.15 ±0.05
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
9 .00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.115
TYP
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
7.15 ± 0.10
(4-SIDES)
(UP64) QFN 1003
0.25 ± 0.05
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
228876f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2288/LTC2287/LTC2286
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1403A/LTC1403
14-Bit/12-Bit 2.8Msps Serial ADC
3V, 14mW, Differential Input, MSOP Package
LTC1407A/LTC1407
14-Bit/12-Bit 3Msps, Simultaneous Sampling Serial ADC
3V, 14mW, 2-Ch. Differential Input, MSOP Package
LTC1749
12-Bit, 80Msps Wideband ADC
Up to 500MHz IF Undersampling, 87dB SFDR
LTC1750
14-Bit, 80Msps Wideband ADC
Up to 500MHz IF Undersampling, 90dB SFDR
LTC2225
12-Bit, 10Msps ADC
60mW, 71dB SNR, 5mm × 5mm QFN
LTC2226
12-Bit, 25Msps ADC
75mW, 71dB SNR, 5mm × 5mm QFN
LTC2227
12-Bit, 40Msps ADC
125mW, 71dB SNR, 5mm × 5mm QFN
LTC2228
12-Bit, 65Msps ADC
210mW, 71dB SNR, 5mm × 5mm QFN
LTC2229
12-Bit, 80Msps ADC
230mW, 70.6dB SNR, 5mm × 5mm QFN
LTC2236
10-Bit, 25Msps ADC
75mW, 61dB SNR, 5mm × 5mm QFN
LTC2237
10-Bit, 40Msps ADC
125mW, 61dB SNR, 5mm × 5mm QFN
LTC2238
10-Bit, 65Msps ADC
210mW, 61dB SNR, 5mm × 5mm QFN
LTC2239
10-Bit, 80Msps ADC
230mW, 61dB SNR, 5mm × 5mm QFN
LTC2245
14-Bit, 10Msps ADC
60mW, 74.4dB SNR, 5mm × 5mm QFN
LTC2246
14-Bit, 25Msps ADC
75mW, 74dB SNR, 5mm × 5mm QFN
LTC2247
14-Bit, 40Msps ADC
125mW, 74dB SNR, 5mm × 5mm QFN
LTC2248
14-Bit, 65Msps ADC
210mW, 74dB SNR, 5mm × 5mm QFN
LTC2249
14-Bit, 80Msps ADC
230mW, 73dB SNR, 5mm × 5mm QFN
LTC2289
Dual 10-Bit, 80Msps ADC
445mW, 61dB SNR, 9mm × 9mm QFN
LTC2290
Dual 12-Bit, 10Msps ADC
120mW, 71dB SNR, 9mm × 9mm QFN
LTC2291
Dual 12-Bit, 25Msps ADC
150mW, 71dB SNR, 9mm × 9mm QFN
LTC2292
Dual 12-Bit, 40Msps ADC
235mW, 71dB SNR, 9mm × 9mm QFN
LTC2293
Dual 12-Bit, 65Msps ADC
400mW, 71dB SNR, 9mm × 9mm QFN
LTC2294
Dual 12-Bit, 80Msps ADC
445mW, 70.6dB SNR, 9mm × 9mm QFN
LTC2295
Dual 14-Bit, 10Msps ADC
120mW, 74.4dB SNR, 9mm × 9mm QFN
LTC2296
Dual 14-Bit, 25Msps ADC
150mW, 74dB SNR, 9mm × 9mm QFN
LTC2297
Dual 14-Bit, 40Msps ADC
235mW, 74dB SNR, 9mm × 9mm QFN
LTC2298
Dual 14-Bit, 65Msps ADC
400mW, 74dB SNR, 9mm × 9mm QFN
LTC2299
Dual 14-Bit, 80Msps ADC
445mW, 73dB SNR, 9mm × 9mm QFN
LT5512
DC-3GHz High Signal Level Downconverting Mixer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514
Ultralow Distortion IF Amplifier/ADC Driver
with Digitally Controlled Gain
450MHz 1dB BW, 47dB OIP3, Digital Gain
Control 10.5dB to 33dB in 1.5dB/Step
LT5515
1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator
20dBm IIP3, Integrated LO Quadrature Generator
LT5516
0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator
21.5dBm IIP3, Integrated LO Quadrature Generator
LT5517
40MHz to 900MHz Direct Conversion Quadrature Demodulator
21dBm IIP3, Integrated LO Quadrature Generator
LT5522
600MHz to 2.7GHz High Linearity Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,
50Ω Single Ended RF and LO Ports
228876f
28
Linear Technology Corporation
LT/TP 0105 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005