CY2DP314 1 of 2:4 Differential Clock/Data Fanout Buffer Features Functional Description • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs (CLKA) • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable The CY2DP314 is a low-skew, low propagation delay 2-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz (full swing). The device features two differential input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2DP314 may function not only as a differential clock buffer but also as a signal-level translator and fanout on HSTL or LVCMOS /LVTTL single-ended signal to four ECL/PECL differential loads. • 50-ps output-to-output skew • 150-ps device-to-device skew • 400-ps propagation delay (typical) • 0.8-ps RMS period jitter (max.) • 1.5-GHz operation (2.7-GHz maximum toggle frequency) • PECL and HSTL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V • ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5% with VCC = 0V Since the CY2DP314 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP314 delivers consistent performance over various platforms. • Industrial temperature range: –40°C to 85°C • 20-pin SSOP package • Temperature compensation like 100K ECL Block Diagram Q0 Q0# VCC CLKA CLKA# VCC NC Q1 Q1# VCC CLK_SEL CLKA VEE VCC Q2 Q2# CLKB CLKB# CLKA# CLKB CLKB# VEE VCC Q3 Q3# VEE CLK_SEL 1 2 3 4 5 6 7 8 9 10 CY2DP314 Pin Configuration 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q0# Q1 Q1# Q2 Q2# Q3 Q3# VCC 20 pin SSOP VEE Cypress Semiconductor Corporation Document #: 38-07550 Rev.*E • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 27, 2004 CY2DP314 Pin Definitions Pin Name I/O +PWR Type Power Description 1,10,11,20,3 VCC 2 NC Power supply, positive connection 4 CLK_SEL I,PD LVCMOS InPut Clock Select 5 CLKA I,PD[1] ECL/PECL Default differential clock input No connect 6 CLKA# I, PD/PU ECL/PECL Default differential clock input 7 CLKB I,PD HSTL Alternate differential clock input 8 CLKB# I, PD/PU HSTL Alternate differential clock input 9 VEE[2] –PWR Power Power supply, negative connection 18,16,14,12 Q[0:3]# O ECL/PECL Complement output 19,17,15,13 Q[0:3] O ECL/PECL True output Table 1. Control Operation CLK_SEL 0 CLKA, CLKA# input pair is active (Default condition with no connection to pin) CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations 1 CLKB, CLKB# input pair is active. CLKB can be driven with HSTL-compatible signals with respective power configurations Governing Agencies The following agencies provide specifications that apply to the CY2DP314. The agency name and relevant specification is listed below in Table 2. Table 2. Agency Name Specification JEDEC JESD 020B (MSL) JESD 8-6 (HSTL) JESD 51 (Theta JA) JESD 8–2 (ECL) JESD 65–B (skew,jitter) Mil-Spec 883E Method 1012.1 (Thermal Theta JC) Notes: 1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power 2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are between VCC and VEE. Document #: 38-07550 Rev.*E Page 2 of 9 CY2DP314 Absolute Maximum Ratings Parameter Description Condition Min. Max. Unit VCC Positive Supply Voltage Non-Functional –0.3 4.6 V VEE Negative Supply Voltage Non-Functional -4.6 0.3 V TS Temperature, Storage Non-Functional –65 +150 °C TJ Temperature, Junction Non-Functional 150 °C ESDh ESD Protection Human Body Model MSL Moisture Sensitivity Level Gate Count Total Number of Used Gates 2000 V 3 N.A. 50 gates Assembled Die Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Operating Conditions Parameter Description Condition Min. Max. Unit IBB Output Reference Current Relative to VBB LUI Latch Up Immunity Functional, typical TA Temperature, Operating Ambient Functional ØJc Dissipation, Junction to Case Functional 37[3] ØJa Dissipation, Junction to Ambient Functional 132[3] IEE Maximum Quiescent Supply Current VEE pin CIN Input pin capacitance 3 pF LIN Pin Inductance 1 nH VIN Input Voltage Relative to VCC[5] VTT Output Termination Voltage Relative to VCC[5] VOUT Output Voltage Relative to VCC[5] IIN Input Current[6] |200| uA 100 mA –40 +85 °C °C/W °C/W 130[4] –0.3 mA VCC + 0.3 VCC – 2 –0.3 V V VCC + 0.3 V l150l uA Min. Max. Unit 2.375 3.135 2.625 3.465 V V 1.2 VCC V 0.68 0.9 V VCC – 1.25 VCC – 0.7 V VCC – 1.995 VCC –1.995 VCC – 1.5 VCC – 1.3 V V VIN = VIL, or VIN = VIH PECL/HSTL DC Electrical Specifications Parameter Description Condition VCC Operating Voltage 2.5V ± 5%, VEE = 0.0V 3.3V ± 5%, VEE = 0.0V VCMR PECL Input Differential Crosspoint Voltage[7] Differential operation VX HSTL Input Differential Crosspoint Volt- Standard Load Differential age[8] Operation VOH Output High Voltage IOH = –30 mA[9] VOL Output Low Voltage VCC = 3.3V ± 5% VCC = 2.5V ± 5% IOL = –5 mA[9] VIH Input Voltage, High Single-ended operation VCC – 1.165 VCC – 0.880 [10] V VIL Input Voltage, Low Single-ended operation VCC – 1.945 [10] VCC – 1.625 V Notes: 3. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1. 4. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip. 5. where VCC is 3.3V±5% or 2.5V±5%. 6. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 7. Refer to Figure 1. 8. VX(AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX(AC) range and the input swing lies within the VDIF(AC) specification. Violation of VX(AC) or VDIF(AC) impacts the device propagation delay, device and part-to-part skew. Refer to Figure 2. 9. Equivalent to a termination of 50Ω to VTT. IOHMIN = (VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50. 10. VIL will operate down to VEE; VIH will operate up to VCC. Document #: 38-07550 Rev.*E Page 3 of 9 CY2DP314 ECL DC Electrical Specifications Parameter Description Condition Min. Max. Unit –2.625 –3.465 –2.375 –3.135 V VEE + 1.2 0V V –1.25 –0.7 V –1.995 –1.995 –1.5 –1.3 V VEE Negative Power Supply –2.5V ± 5%, VCC = 0.0V –3.3V ± 5%, VCC = 0.0V VCMR ECL Input Differential cross point voltage[7] Differential operation VOH Output High Voltage IOH = –30 mA[9] VOL Output Low Voltage VEE = –3.3V ± 5% VEE = –2.5V ± 5% IOL = –5 mA[9] VIH Input Voltage, High Single-ended operation –1.165 –0.880[10] V VIL Input Voltage, Low Single-ended operation –1.945 [10] –1.625 V Min. Max. Unit 0.1 1.3 V AC Electrical Specifications Parameter Description Condition VPP ECL/PECL Input Differential Input Voltage[7] VCMRO Output Common Voltage Range (typ.) FCLK Input Frequency 50% duty cycle Standard load – 1.5 GHz TPD Propagation Delay CLKA or CLKB to Output pair[12] PECL, ECL = 660 MHz HSTL < 1GHz 280 280 650 750 ps ps VDIF HSTL Differential Input Voltage[11] Duty Cycle Standard Load Differential Operation 0.4 1.9 V VX HSTL Input Differential Crosspoint Volt- Standard Load Differential age[8] Operation 0.68 0.9 V Vo Output Voltage (peak-to-peak; see Figure 2) < 1 GHz 0.375 – V tsk(0) Output-to-output Skew 660 MHz [12], See Figure 3 Differential operation VCC – 1.425 – 50 ps [12] – 150 ps – 0.8 ps – 50 ps 0.08 0.3 ns tsk(PP) Part-to-Part Output Skew 660 MHz TPER Output Period Jitter (rms)[13] 660 MHz [12] Skew[14] tsk(P) Output Pulse TR,TF Output Rise/Fall Time (see Figure 2) 660 MHz V [12], See Figure 3 660 MHz 50% duty cycle Differential 20% to 80% Notes: 11. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tkpd and device-to-device skew. 12. 50% duty cycle; standard load; differential operation. 13. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000 data points. 14. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |. . Document #: 38-07550 Rev.*E Page 4 of 9 CY2DP314 Timing Definitions VCC VCM R M ax = VCC V IH VPP V P P ra n g e 0 .1 V - 1 .3 V VCM R V IL V C M R M in = V E E + 1 .2 VEE Figure 1. PECL/ECL Input Waveform Definitions VCC V C C = 3 .3 V V X m a x = 0 .9 V V IH V D IF V D IF = > = 0 .4 V m in VX V IL V E E = 0 .0 V VEE V X M in = 0 .6 8 Figure 2. HSTL Differential Input Waveform Definitions tr, tf, 2 0 -8 0 % VO Figure 3. ECL/LVPECL Output In p u t C lo c k V P P TP L H , T P D TP H L O u tp u t C lo c k V O tS K (O ) A n o th e r O u tp u t C lo c k Figure 4. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O)) for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL Document #: 38-07550 Rev.*E Page 5 of 9 CY2DP314 Test Configuration Standard test load using a differential pulse generator and differential measurement instrument. VTT VTT R T = 50 ohm R T = 50 ohm 5" P u ls e G e n e ra to r Z = 50 ohm Zo = 50 ohm Zo = 50 ohm 5" R T = 50 ohm DUT C Y2D P314 R T = 50 ohm VTT VTT Figure 5. CY2DP314 AC Test Reference Applications Information Termination Examples CY2DP314 VTT VCC R T = 50 ohm R T = 50 ohm 5" Zo = 50 ohm 5" VTT VEE Figure 6. Standard LVPECL – PECL Output Termination CY2DP314 VTT R T = 50 ohm VCC 5" Zo = 50 ohm 5" VTT R T = 50 ohm V B B (3 .3 V ) VEE Figure 7. Driving a PECL/ECL Single-ended Input Document #: 38-07550 Rev.*E Page 6 of 9 CY2DP314 C Y 2D P 314 3 .3 V V C C = 3 .3 V 120 ohm L V D S 5" Z o = 50 ohm 33 ohm ( 2 p la c e s ) 5" 120 ohm 3 .3 V 51 ohm ( 2 p la c e s ) L V P E C L to L V D S V E E = 0V Figure 8. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Interface VDD-2 VCC X Y Z One output is shown for clarity Figure 9. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note entitled PECL Translation, SAW Oscillators, and Specs for Other Signalling Standards and Supplies Ordering Information Part Number Package Type Product Flow CY2DP314OI 20-pin SSOP Industrial, –40° to 85°C CY2DP314OIT 20-pin SSOP – Tape and Reel Industrial, –40° to 85°C CY2DP314OXI 20-pin SSOP Industrial, –40° to 85°C CY2DP314OXIT 20-pin SSOP – Tape and Reel Industrial, –40° to 85°C Lead-free Document #: 38-07550 Rev.*E Page 7 of 9 CY2DP314 Package Drawing and Dimensions 20-Lead (5.3 mm) Shrunk Small Outline Package O20 51-85077-*C FastEdge is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07550 Rev.*E Page 8 of 9 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2DP314 Document History Page Document Title: CY2DP314 FastEdge SERIES 1 of 2:4 Differential Clock/Data Fanout Buffer Document Number: 38-07550 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 126779 06/13/03 RGL New data sheet *A 128940 08/19/03 RGL Changed the operation value from 1.5 GHz, reduced swing to 3 GHz to from DC to above 1.5 GHz Changed VCC value in the IIN parameter from 3.6V to 3.645V. Changed the VOL min value from VCC–1.9 to VCC–1.945 Changed the IEE max value from 48 mA to 130 mA Specified the max input frequency (FCLK) to 2200 MHz Specified the TTB max value to 250 ps *B 207710 See ECN RGL Added Junction Temperature (TJ) parameter in the Absolute Max. Conditions table Replaced ICC calculation with power calculation in the footnote *C 237748 See ECN RGL Provided data for TBDs to match the device *D 247603 See ECN *E 270151 See ECN Document #: 38-07550 Rev.*E RGL/GGK Changed VOH and VOL to match the Char Data RGL Removed all VBB references Added Lead-free devices Page 9 of 9