AVAGO ACPL-34JT 1.9 a miller clamp sinking current Datasheet

ACPL-34JT
Automotive 2.5 Amp Gate Drive Optocoupler
with Integrated IGBT DESAT Overcurrent Sensing,
Miller Current Clamping and UnderVoltage LockOut Feedback
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Avago’s Automotive 2.5Amp Gate Drive Optocoupler features fast propagation delay with excellent timing skew
performance. Smart features that are integrated to protect the IGBT include IGBT desaturation sensing with softshutdown protection and fault feedback, under voltage
lockout and feedback and active Miller current clamping.
This full featured and easy-to-implement IGBT gate drive
optocoupler comes in a compact, surface-mountable
SO-16 package for space-saving. It is suitable for traction
power train inverter, power converter, battery charger,
air-con and oil pump motor drives in HEV and EV applications and satisfies automotive AEC-Q100 semiconductor
requirements.
•
•
•
•
•
•
•
Avago R2Coupler isolation products provide reinforced
insulation and reliability that delivers safe signal isolation
critical in automotive and high temperature industrial applications.
- Desat sensing, “Soft” IGBT turn-off and Fault
Feedback
- Under Voltage Lock-Out protection (UVLO) with
Feedback
• >50 kV/μs Common Mode Rejection (CMR) at VCM =
1500 V
• High Noise Immunity
- Miller Current Clamping
Functional Diagram
VE
- Direct LED input with low input impedance and low
noise sensitivity
VCC2
LED2+
UVLO
UVLO
VCC1
UVLO
FAULT
VEE1
VEE1
VEE1
AN
CA
Input
Driver
DESAT
Over
OutputDriverOver
Output
Current
Current
Driver
SSD/
CLAMP
Miller Control
Figure 1. ACPL-34JT Functional Diagram
VEE2 VEE2
•
•
•
•
- Negative Gate Bias
SO-16 package with 8 mm clearance and creepage
Regulatory approvals:
UL1577, CSA
IEC/EN/DIN EN 60747-5-5
Applications
VO
SS Control
Qualified to AEC-Q100 Grade 1 Test Guidelines
-40 °C to +125 °C operating temperature range
2.5 A maximum peak output current
1.9 A Miller Clamp Sinking Current
Wide Operating Voltage: 15V to 25V
Propagation delay: 280 ns (max.)
Integrated fail-safe IGBT protection
•
•
•
•
Automotive Isolated IGBT/MOSFET Inverter gate drive
Automotive DC-DC Converter
AC and brushless DC motor drives
Industrial inverters for power supplies and motor
controls
• Uninterruptible Power Supplies
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
RoHS
Compliant
Package
Surface Mount
ACPL-34JT
-000E
SO-16
X
ACPL-34JT
-500E
Part Number
Tape & Reel
X
IEC/EN/DIN EN
60747-5-5
X
Quantity
X
45 per tube
X
850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-34JT-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
16-Lead Surface Mount
0.018
(0.457)
16 15 14 13 12 11 10 9
0.050
(1.270)
LAND PATTERN RECOMMENDATION
TYPE NUMBER
DATE CODE
A 34JT
YYWW
EE
0.458 (11.63)
0.295 ± 0.010
(7.493 ± 0.254)
1 2 3 4 5 6 7 8
0.406 ± 0.010
(10.312 ± 0.254)
EXTENDED
DATECODE FOR
LOT TRACKING
0.085 (2.16)
0.025 (0.64)
0.345 ± 0.010
(8.763 ± 0.254)
9°
0.018
(0.457)
0.138 ± 0.005
(3.505 ± 0.127)
ALL LEADS
TO BE
COPLANAR
± 0.002
0–8°
0.025 MIN.
0.408 ± 0.010
(10.363 ± 0.254)
Dimensions in inches (millimeters)
Lead coplanarity = 0.1mm (0.004 inches)
Floating lead protrusion = 0.25mm (10mils) max.
Recommended Lead-free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision).
Non-halide flux should be used.
2
Product Overview Description
The ACPL-34JT (shown in Figure 1) is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT gate drive circuit. It features IGBT desaturation sensing with soft-shutdown protection and fault feedback, under voltage lockout and feedback and active Miller current clamping in a SO-16 package.
Direct LED input allows flexible logic configuration and differential current mode driving with low input impedance,
greatly increased its noise immunity.
Package Pin Out
1
VEE1
VEE2 16
2
VEE1
LED2+ 15
3
VCC1
DESAT 14
4
VEE1
VE 13
5
UVLO
VCC2 12
6
FAULT
7
AN
SSD/CLAMP 10
8
CA
VEE2 9
VO 11
Figure 2. Pin out of ACPL-34JT
Pin Description
Pin Name
Function
Pin Name
Function
VEE1
Input common
VEE2
Negative power supply
VEE1
Input common
LED2+
No connection, for testing only
VCC1
Input power supply
DESAT
Desat Over current sensing
VEE1
Input common
VE
IGBT Emitter Reference
UVLO
VCC2 under voltage lock out feedback
VCC2
Positive power supply
FAULT
Over current fault feedback
VO
Driver output to IGBT gate
AN
Input LED anode
SSD/CLAMP
Soft Shutdown / Miller current clamping output
CA
Input LED cathode
VEE2
Negative Power Supply
3
Typical Application/Operation
Introduction to Fault Detection and Protection
The power stage of a typical three phase inverter is susceptible to several types of failures, most of which are potentially
destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase and/or rail supply
short circuits due to user misconnect or bad wiring, control signal failures due to noise or computational errors, overload
conditions induced by the load, and component failures in the gate drive circuitry. Under any of these fault conditions,
the current through the IGBTs can increase rapidly, causing excessive power dissipation and heating. The IGBTs become
damaged when the current load approaches the saturation current of the device, and the collector to emitter voltage
rises above the saturation voltage level. The drastically increased power dissipation very quickly overheats the power
device and destroys it. To prevent damage to the drive, fault protection must be implemented to reduce or turn-off the
overcurrent during a fault condition.
A circuit providing fast local fault detection and shutdown is an ideal solution, but the number of required components,
board space consumed, cost, and complexity have until now limited its use to high performance drives. The features
which this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size.
The ACPL-34JT satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT desaturation detection and shut down, and optically isolated fault and
UVLO status feedback signal into a single 16-pin surface mount package.
The fault detection method, which is adopted in the ACPL-34JT, is to monitor the saturation (collector) voltage of the
IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small
gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before
the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect
circuitry is simply disabled to prevent false ‘fault’ signals.
The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit
capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only
partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-34JT limits the power dissipation in the
IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method
is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold
to predict the safe limit of operation. Therefore, an overly- conservative overcurrent threshold is not needed to protect
the IGBT.
Recommended Application Circuit
The ACPL-34JT has non-inverting gate control inputs, and an open collector fault and UVLO outputs suitable for wired
‘OR’ applications.
The recommended application circuit shown in Figure 3 illustrates a typical gate drive implementation using the ACPL34JT.
The two supply bypass capacitors (0.1 μF) provide the large transient currents necessary during a switching transition.
The desat diode and 220pF blanking capacitor are the necessary external components for the fault detection circuitry.
The gate resistor (10Ω) serves to limit gate charge current and indirectly control the IGBT collector voltage rise and fall
times. The open collector fault and UVLO outputs have a passive 10kΩ pull-up resistor and a 330 pF filtering capacitor.
4
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to
allow the collector voltage to fall below the DESAT theshold. This time period, called the DESAT blanking time, is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor.
The nominal blanking time is calculated in terms of external capacitance (CBLANK), FAULT threshold voltage (VDESAT ), and
DESAT charge current (ICHG) in addition to an internal DESAT blanking time (tDESAT(BLANKING)).
tBLANK = CBLANK x (VDESAT/ICHG) + tDESAT(BLANKING)
VCC1
VCC2
+ 5V
0.1uF
10kΩ
10kΩ
uC
150Ω
330pF
330pF
150Ω
VEE1
VEE2
VEE1
LED2+
VCC1
DESAT
VEE1
VE
UVLO
VCC2
1kΩ
220pF
10uF
0.1uF
VO
FAULT
AN
SSD/CLAMP
CA
VEE2
ACPL-34JT
10Ω
10uF
VEE2
Figure 3. Typical gate drive circuit with Desat current sensing using ACPL-34JT
Description of Gate Driver and Miller Clamping
The gate driver is directly controlled by the LED current. When LED current is driven high, the output of ACPL-34JT can
deliver 2.5 A sourcing current to drive the IGBT’s gate. While LED is switched off, the gate driver can provide 2.5 A sinking current to switch the gate off fast. Additional Miller clamping pull-down transistor is activated when output voltage
reaches about 2 V with respect to VEE2 to provide low impedance path to Miller current as shown in Figure 5.
IF
VO
V GATE
Figure 4. Gate Drive Signal Behavior
5
Description of UnderVoltage LockOut
Insufficient gate voltage to IGBT can increase turn on resistance of IGBT, resulting in large power loss and IGBT damage
due to high heat dissipation. ACPL-34JT monitors the output power supply constantly. When output power supply is
lower than undervoltage lockout (UVLO) threshold gate driver output will shut off to protect IGBT from low voltage bias.
During power up, the UVLO feature forces the gate driver output to low to prevent unwanted turn-on at lower voltage.
V CC1
VCC2
V UVLO -
V UVLO+
LED I F
t UVLO_OFF
VO
t UVLO_ON
FAULT
UVLO
t PHL_UVLO
t PLH_UVLO
Figure 5. Circuit Behaviors at Power up and Power down
Description of Operation during Over Current Condition
1. DESAT terminal monitors IGBT’s VCE voltage.
2. When the voltage on the DESAT terminal exceeds 7 volts, the output voltage (VOUT ) to IGBT gate goes to Hi-Z state
and the SSD/CLAMP output is slowly lowered.
3. FAULT output goes low, notifying the microcontroller of the fault condition.
4. Microcontroller takes appropriate action.
5. When tDESAT(MUTE) expires LED input need to be kept low for tDESAT(RESET) before fault condition is cleared. FAULT
status will return to high and SSD/CLAMP output will return to Hi-Z state.
6. Output (VOUT ) starts to respond to LED input after fault condition is cleared.
tDESAT(RESET)
IF
V O state
Clamp State
Hi-Z
Clamp
tDESAT(90%)
V GATE
VDESAT_TH
V DESAT
tDESAT(BLANKING)
V FAULT
tDESAT(MUTE)
tDESAT(FAULT)
Figure 6. Circuit Behaviors During Overcurrent Event
6
Hi-Z
Clamp
Hi-Z
Clamp
The ACPL-34JT is approved by the following organizations:
UL
CSA
IEC/EN/DIN EN 60747-5-5
UL 1577, component recognition program up to VISO = 5000 VRMS expected
prior to product release.
CSA Component Acceptance Notice
#5, File CA 88324.
IEC 60747-5-5
EN 60747-5-5
DIN EN 60747-5-5
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Description
Symbol
Characteristic
Insulation Classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150Vrms
for rated mains voltage ≤ 300Vrms
for rated mains voltage ≤ 600Vrms
for rated mains voltage ≤ 1000Vrms
I – IV
I – IV
I – IV
I – III
Climatic Classification
40/125/21
Pollution Degree (DIN VDE 0110/1.89)
Unit
2
Maximum Working Insulation Voltage
VIORM
1230
VPEAK
Input to Output Test Voltage, Method b
VIORM x 1.875 = VPR, 100% Production Test with tm = 1sec,
Partial discharge < 5 pC
VPR
2306
VPEAK
Input to Output Test Voltage, Method a
VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial Discharge < 5 pC
VPR
1968
VPEAK
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
8000
VPEAK
Safety-limiting values
– maximum values allowed in the event of a failure (also see Figure 7)
Case Temperature
Input Power
Output Power
TS
PS,INPUT
PS,OUTPUT
175
400
1200
°C
mW
mW
Insulation Resistance at TS, VIO = 500V
RS
> 109
Ohm
Notes:
1. Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
2. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulation section IEC/EN/DIN
EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles.
1400
PS, OUTPUT
PS, INPUT
PS – POWER – mW
1200
1000
800
600
400
200
0
0
25
50
75
100 125 150
TS – CASE TEMPERATURE – °C
175
Figure 7. Dependence of safety limiting values on temperature.
7
200
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External
Air Gap (Clearance)
L(101)
8.3
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External
Tracking (Creepage)
L(102)
8.3
mm
Measured from input terminals to output terminals,
shortest distance path along body.
0.5
mm
Through insulation distance conductor to conductor, usually the
straight line distance thickness between the emitter and detector.
>175
Volts
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic
Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
CTI
Isolation Group
IIIa
Material Group (DIN VDE 0110)
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
150
°C
Operating Temperature
TA
-40
125
°C
IC Junction Temperature
TJ
150
°C
Average Input Current
IF(AVG)
20
mA
Peak Transient Input Current
(<1us pulse width, 300pps)
IF(TRAN)
1
A
Reverse Input Voltage
VR
6
V
Peak Output Current
|IO(peak)|
2.5
A
Fault Output Current (Sinking)
IFAULT
10
mA
Fault Pin Voltage
VFAULT
6
V
UVLO Output Current (Sinking)
IUVLO
10
mA
UVLO Pin Voltage
VUVLO
-0.5
6
V
Positive Input Supply Voltage
VCC1
-0.5
26
V
Total Output Supply Voltage
VCC2 - VEE2
-0.5
30
V
Negative Output Supply Voltage
VE - VEE2
-0.5
15
V
Positive Output Supply Voltage
VCC2 - VE
-0.5
30
V
Gate Drive Output Voltage
Vo(peak)
-0.5
VCC2 + 0.5
V
Peak Clamping Sinking Current
ICLAMP
2
A
Miller Clamping Pin Voltage
VCLAMP - VEE2
-0.5
VCC2
V
DESAT Voltage
VDESAT - VE
VE – 0.5
VCC2 + 0.5
V
4
Output IC Power Dissipation
PO
580
mW
1
Input IC Power Dissipation
PI
150
mW
Absolute Maximum Ratings
-0.5
Note
1
2
3
2
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Operating Temperature
TA
-40
125
°C
Input Supply Voltage
VCC1
8
18
Volts
5
Total Output Supply Voltage
VCC2 - VEE2
15
25
V
6
Negative Output Supply Voltage
VE - VEE2
0
10
V
3
Positive Output Supply Voltage
VCC2 - VE
15
25
V
Input LED Current
IF(ON)
10
16
mA
Input Voltage (OFF)
VF(OFF)
-3.6
0.8
V
Input pulse width
tON(LED)
500
8
ns
Notes
Electrical Specifications
Unless otherwise specified, all Minimum/Maximum specifications are at recommended operating conditions, all voltages at input IC are referenced to VEE1, all voltages at output IC referenced to VEE2. All typical values at TA = 25 °C, VCC1 =
12 V, VCC2-VEE2 = 20 V, VE-VEE2 = 0 V.
Parameter
Symbol
Input Low Supply Current
Typ.
Max.
Units
Test Conditions
Fig
ICC1L
3.7
6.0
mA
IF=0mA
8
Input High Supply Current
ICC1H
3.7
6.0
mA
IF=10mA
8
Output Low Supply Current
ICC2L
10.5
13.2
mA
IF=0mA
9
Output High Supply Current
ICC2H
10.6
13.6
mA
IF=10mA
9
LED Forward Voltage
VF
1.25
1.55
1.85
V
IF=10mA
10
LED Reverse Breakdown Voltage
VBR
6
V
IF =10mA
Input Capacitance
CIN
90
LED Turn on Current Threshold
Low to High
ITH+
2.7
6.6
mA
VO=5V
LED Turn on Current Threshold
High to Low
ITH-
2.1
6.4
mA
VO=5V
LED Turn on Current Hysteresis
ITH_HYS
0.6
mA
High Level Output Current
IOH
-0.75
-2.0
A
VOUT = VCC2 - 3 V
11
2
Low Level Output Current
IOL
1.0
2.2
A
VOUT = VEE2 + 2.5 V
12
2
Low Level Soft Shutdown
Current During Fault Condition
ISSD
22
35
mA
VSSD - VEE2 = 14V
13
High Level Output Voltage
VOH
VCC2
– 0.5
VCC2
– 0.2
V
IOUT = -100 mA
11,14 7, 8, 9
Low Level Output Voltage
VOL
0.1
0.5
V
IOUT = 100 mA
12,15
Clamp Threshold Voltage
V TH_CLAMP
2.0
3.0
V
Clamp Low Level Sinking Current
ICLAMP
0.75
1.9
VCC2 UVLO Threshold Low to High
VUVLO+
11.0
12.4
VCC2 UVLO Threshold High to Low
VUVLO-
10.1
11.3
VCC2 UVLO Hysteresis
VUVLO_HYS
Desat Sensing Threshold
VDESAT
6.2
7.0
7.8
V
Desat Charging Current
ICHG
0.6
0.9
1.2
mA
VOC = 2V
17
Desat Discharging Current
IDSCHG
20
53
mA
VOC = 7V
18
FAULT Logic Low Output Current
IFAULT_L
4.0
9.0
mA
VFAULT = 0.4V
FAULT Logic High Output Current
IFAULT_H
uA
VFAULT = 5V
UVLO Logic Low Output Current
IUVLO_L
mA
VUVLO = 0.4V
UVLO Logic High Output Current
IUVLO_H
uA
VUVLO = 5V
9
Min.
pF
48
A
VCLAMP = VEE2 + 2.5
13.7
V
VOUT > 5 V
9, 10
12.8
V
VOUT < 5 V
9, 11
1.1
V
20
4.0
Note
9.0
20
9
16
9
Switching Specifications
Unless otherwise specified, all Minimum/Maximum specifications are at recommended operating conditions, all voltages at input IC are referenced to VEE1, all voltages at output IC referenced to VEE2. All typical values at TA = 25 °C, VCC1 =
12 V, VCC2-VEE2 = 20 V, VE-VEE2 = 0 V.
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Fig
Note
VIN to High Level Output
Propagation Delay Time
tPLH
50
130
250
ns
19-21
12
VIN to Low Level Output
Propagation Delay Time
tPHL
50
150
280
ns
Rg = 10 Ω
Cg = 10 nF
f = 10 kHz
Duty Cycle = 50%
19-21
13
Pulse Width Distortion
PWD
20
100
ns
14, 15
Propagation Delay Difference
Between Any 2 Parts (tPHL-tPLH)
PDD
20
150
ns
15, 16
10% to 90% Rise Time
tR
60
90% to 10% Fall Time
tF
50
Desat Blanking Time
tDESAT(BLANKING)
0.6
Desat Sense to 90% VOUT Delay
tDESAT(90%)
1.0
µs
Desat Sense to 10% VOUT Delay
tDESAT(10%)
2.0
µs
19
Desat to Desat Low Propagation Delay
tDESAT(LOW)
0.3
µs
20
Desat to Low Level FAULT Signal Delay
tDESAT(FAULT)
µs
21
Output Mute Time due to Desat
tDESAT(MUTE)
2.3
3.2
ms
22
Time Input Kept Low
Before Fault Reset to High
tDESAT(RESET)
2.3
3.2
ms
23
VCC2 to UVLO High Delay
tPLH_UVLO
10
µs
24
VCC2 to UVLO Low Delay
tPHL_UVLO
10
µs
25
VCC2 UVLO to VOUT High Delay
tUVLO_ON
10
µs
26
VCC2 UVLO to VOUT Low Delay
tUVLO_OFF
10
µs
27
Output High Level Common Mode
Transient Immunity
|CMH|
30
>50
kV/μs
TA=25°C, IF=10mA,
VCM =1500V,
VCC1=12V
22, 24, 28
26
Output Low Level Common Mode
Transient Immunity
|CML|
30
>50
kV/μs
TA = 25°C, IF=0mA,
VCM=1500V,
VCC1=12V
23, 25, 29
27
Parameter
Symbol
Min.
Typ.
Units
Test Conditions
Note
Input-Output Momentary
Withstand Voltage
VISO
5000
VRMS
RH < 50%, t = 1
min. TA = 25°C
30, 31, 32
Resistance (Input-Output)
RI-O
1014
Ω
VI-O = 500 Vdc
32
Capacitance (Input-Output)
CI-O
1.3
pF
f = 1 MHz
Thermal coefficient between
LED and input IC
LED and output IC
input IC and output IC
LED and Ambient
input IC and Ambient
output IC and Ambient
AEI
AEO
AIO
AEA
AIA
AOA
35.4
33.1
25.6
176.1
92
76.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
ns
ns
1.0
5
µs
Rg=10 Ohm,
Cg= 0 - 1nF
17
18
Package Characteristics
10
Max.
Notes on Thermal Calculation
Application and environmental design for ACPL-34JT needs to ensure that the junction temperature of the internal ICs
and LED within the gate driver optocoupler do not exceed 150°C. The equations provided below are for the purposes of
calculating the maximum power dissipation and corresponding effect on junction temperatures.
LED Junction Temperature = AEA*PE + AEI*PI + AEO*PO + TA
Input IC Junction Temperature = AEI*PE + AIA*PI + AIO*PO + TA
Output IC Junction Temperature = AEO*PE + AIO*PI + AOA*PO + TA
PE - LED Power Dissipation
PI - Input IC Power Dissipation
PO - Output IC Power Dissipation
Calculation of LED Power Dissipation
LED Power Dissipation, PE = IF(LED) (Recommended Max) * VF(LED) (125°C) * Duty Cycle
Example: PE = 16mA * 1.25 * 50% duty cycle = 10mW
Calculation of Input IC Power Dissipation
Input IC Power Dissipation, PI = ICC1 (Max) * VCC1 (Recommended Max)
Example: PI = 6mA * 18V = 108mW
Calculation of Output IC Power Dissipation
Output IC Power Dissipation, PO = VCC2 (Recommended Max) * ICC2 (Max) + PHS + PLS
PHS - High Side Switching Power Dissipation
PLS - Low Side Switching Power Dissipation
PHS = (VCC2 * QG * fPWM) * ROH(MAX) / (ROH(MAX) + RGH) / 2
PLS = (VCC2 * QG * fPWM) * ROL(MAX) / (ROL(MAX) + RGL) / 2
QG – IGBT Gate Charge at Supply Voltage
fPWM - LED Switching Frequency
ROH(MAX) – Maximum High Side Output Impedance - VOH(MIN) / IOH(MIN)
RGH - Gate Charging Resistance
ROL(MAX) – Maximum Low Side Output Impedance - VOL(MIN) / IOL(MIN)
RGL - Gate Discharging Resistance
Example:
ROH(MAX) = VOH(MIN) / IOH(MIN) = 2.5V / 0.75A = 3.33Ω
ROL(MAX) = VOL(MIN) / IOL(MIN) = 2.5V / 1A = 2.5Ω
PHS =(20V * 1uC * 10kHz) * 3.33Ω / (3.33Ω + 10Ω) / 2 = 24.98mW
PLS =(20V * 1uC * 10kHz) * 2.5Ω / (2.5Ω + 10Ω) / 2 = 20mW
PO = 20V * 13.6mA + 24.98mW + 20mW = 316.98mW
Calculation of Junction Temperature
LED Junction Temperature
= 176.1°C/W *10mW + 35.4°C/W *108mW + 33.1*316.98mW + TA
= 16.1°C + TA
Input IC Junction Temperature
= 35.4°C/W *10mW + 92°C/W *108mW + 25.6*316.98mW + TA
= 18.4°C + TA
Output IC Junction Temperature = 33.1°C/W *10mW + 25.6°C/W *108mW + 76.7*316.98mW + TA
= 27.4°C + TA
11
Notes:
1. Output IC power dissipation is derated linearly above 100°C from 580mW to 260mW at 125°C.
2. Maximum pulse width = 1 μs, maximum duty cycle = 1%.
3. This supply is optional. Required only when negative gate drive is implemented.
4. Maximum 500ns pulse width if peak VDESAT > 10V
5. In most applications VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the
IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that input remains low until VCC1 reaches the proper operating
voltage to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down.
6. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 13.5 V.
7. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will approach VCC as IOH
approaches zero.
8. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
9. Once VOUT of the ACPL-34JT is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the ACPL-34JT will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once VCC2 exceeds VUVLO+ threshold, DESAT will remain functional until VCC2 is
below VUVLO- threshold. Thus, the DESAT detection and UVLO features of the ACPL-34JT work in conjunction to ensure constant IGBT protection.
10. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE.
11. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE.
12. tPLH is defined as propagation delay from 50% of LED input IF to 50% of High level output.
13. tPHL is defined as propagation delay from 50% of LED input IF to 50% of Low level output.
14. Pulse Width Distortion (PWD) is defined as |tPHL – tPLH| of any given unit.
15. As measured from IF to VO.
16. The difference between tPHL and tPLH between any two ACPL-34JT parts under the same test conditions.
17. The delay time for ACPL-34JT to respond to a DESAT fault condition without any external DESAT capacitor.
18. The amount of time from when DESAT threshold is exceeded to 90% of VGATE at mentioned test conditions.
19. The amount of time from when DESAT threshold is exceeded to 10% of VGATE at mentioned test conditions.
20. The amount of time from when DESAT threshold is exceeded to DESAT Low voltage, 0.7 V.
21. The amount of time from when DESAT threshold is exceeded to FAULT output Low – 50% of VCC1 voltage.
22. The amount of time when DESAT threshold is exceeded, Output is mute to LED input.
23. The amount of time when DESAT Mute time is expired, LED input must be kept Low for Fault status to return to High.
24. The delay time when VCC2 exceeds UVLO+ threshold to UVLO High – 50% of UVLO positive going edge.
25. The delay time when VCC2 falls below UVLO- threshold to UVLO Low – 50% of UVLO negative going edge.
26. The delay time when VCC2 exceeds UVLO+ threshold to 50% of High level output.
27. The delay time when VCC2 falls below UVLO- threshold to 50% of Low level output.
28. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in the high state (i.e., VO > 15 V or FAULT > 2 V or UVLO > 2V). A 330 pF and a 10 kΩ pull-up resistor is needed in fault and UVLO detection
mode.
29. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V or UVLO < 0.8 V). A 330 pF and a 10 kΩ pull-up resistor is needed in fault and UVLO
detection mode.
30. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 VRMS for 1 second.
31. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Table
32. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together.
12
12
ICC2 - INPUT SUPPLY CURRENT - mA
ICC1 - INPUT SUPPLY CURRENT - mA
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
-40
ICCL1
ICCH1
-20
0
20
40
60
80
TA - TEMPERATURE - °C
100
120
VOH - OUTPUT HIGH VOLTAGE - V
IF - FORWARD CURRENT - mA
10.00
1.00
0.10
1.2
2.5
-40
-20
0
20 40 60 80
TA - TEMPERATURE - °C
100
1.3
1.4
1.5
VF - FORWARD VOLTAGE - V
1.6
1.5
0.5
0
Figure 12. VOL vs IOL
0.5
1
1.5
2
IOL - OUTPUT LOW CURRENT - A
19
18.5
18
17.5
17
0
0.5
1
1.5
IOH - OUTPUT HIGH CURRENT - A
2
2.5
45
1
0
140
Figure 11. VOH vs IOH
-40°C
25°C
125°C
2
120
-40°C
25°C
125°C
19.5
ISSD - SOFT SHUTDOWN CURRENT
DURING FAULT CONDITION - mA
VOL - OUTPUT LOW VOLTAGE - V
9.5
20
Figure 10. Typical Diode Input Forward Current Characteristic
13
10
Figure 9. ICC2 across temperature
Ta = 25°C
-0.5
10.5
9
100.00
0.01
11
140
Figure 8. ICC1 across temperature
ICCL2
ICCH2
11.5
2.5
40
35
30
25
20
15
-40°C
25°C
125°C
10
5
0
0
Figure 13. ISSD vs VSSD
5
10
15
20
VSSD - SOFT SHUTDOWN VOLTAGE - V
25
VOL - LOW OUTPUT VOLTAGE - V
(VOH-VCC) - HIGH OUTPUT VOLTAGE DROP - V
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
-0.45
-0.5
-40
-20
0
20 40 60 80
TA - TEMPERATURE - °C
100
120
140
Figure 14. VOH across temperature
ICHG - DESAT CHARGING CURRENT - mA
VDESAT - DESAT THRESHOLD - V
7
6.8
6.6
6.4
6.2
-20
0
20
40
60
80
TA - TEMPERATURE - °C
100
120
PROPAGATION DELAY - ns
IDSCHG - DESAT DISCHARGING CURRENT - mA
60
50
40
30
20
10
-20
0
20
40
60
80
TA - TEMPERATURE - °C
Figure 18. IDCHG across temperature
14
100
120
140
100
120
140
-0.8
-0.85
-0.9
-0.95
-40
-20
0
20 40 60 80
TA - TEMPERATURE - °C
Figure 17. ICHG across temperature
70
-40
20 40 60 80
TA - TEMPERATURE - °C
-0.75
-1
140
Figure 16. VDESAT Threshold across temperature
0
0
-0.7
7.2
-40
-20
Figure 15. VOL across temperature
7.4
6
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-40
100
120
140
200
180
160
140
120
100
80
60
40
20
0
-40
Tplh_2010
Tphl_2010
-20
0
20 40 60 80
TA - TEMPERATURE - °C
Figure 19. tP across temperature
100
120
140
180
160
160
140
140
PROPAGATION DELAY - ns
PROPAGATION DELAY - ns
180
120
100
80
60
40
TPLH
TPHL
20
0
15
17
19
21
VCC - SUPPLY VOLTAGE - V
23
+
5V
_
150R
100
80
60
40
TPLH
TPHL
20
0
25
0
10
20
30
LOAD RESISTANCE - Ω
VEE1
VEE2
VEE1
LED2+
VCC1
DESAT
VEE1
VE
UVLO
VCC2
FAULT
VO
_
+
0.1µF
AN
SSD/CLAMP
CA
VEE2
20 V
Scope
150R
10R
10nF
150R
VEE1
VEE2
VEE1
LED2+
VCC1
DESAT
VEE1
VE
UVLO
VCC2
FAULT
VO
AN
SSD/CLAMP
CA
VEE2
-
+
+
0.1 F
10k
Scope
330 pF
5V
+
_
150R
VEE2
VEE1
LED2+
VCC1
DESAT
VEE1
VE
UVLO
VCC2
FAULT
VO
AN
SSD/CLAMP
CA
VEE2
150R
+
High Voltage Pulse
VCM = 1500 V
Figure 24. CMR Fault High Test Circuit
15
+
0.1µF
20 V
Scope
10R
10nF
Figure 23. CMR Vo Low Test Circuit
VEE1
-
_
High Voltage Pulse
VCM = 1500 V
Figure 22. CMR Vo High Test Circuit
12V
50
-
+
High Voltage Pulse
VCM = 1500 V
_
40
Figure 21. tP vs Load Resistance
Figure 20. tP vs Supply Voltage
150R
120
0.1 F
_
+
12V
_
+
0.1 F
20 V
10k
Scope
330 pF
10R
10 nF
5V
+
_
150R
VEE1
VEE2
VEE1
LED2+
VCC1
DESAT
VEE1
VE
UVLO
VCC2
FAULT
VO
AN
SSD/CLAMP
CA
VEE2
150R
-
+
High Voltage Pulse
VCM = 1500 V
Figure 25. CMR Fault Low Test Circuit
_
0.1 F
+
10R
10nF
20V
_
12 V
+
0.1 F
10k
Scope
330 pF
5V
+
_
150R
150R
VEE1
VEE2
VEE1
LED2+
VCC1
DESAT
VEE1
VE
UVLO
VCC2
FAULT
VO
AN
SSD/CLAMP
CA
VEE2
-
_
_
0.1 F
+
12 V
20 V
+
0.1 F
10k
Scope
330 pF
10R
10 nF
5V
+
_
150R
150R
VEE1
LED2+
VCC1
DESAT
VEE1
VE
UVLO
VCC2
FAULT
VO
AN
SSD/CLAMP
CA
VEE2
+
High Voltage Pulse
VCM = 1500 V
High Voltage Pulse
VCM = 1500 V
For product information and a complete list of distributors, please go to our web site:
VEE2
-
+
Figure 26. CMR UVLO High Test Circuit
VEE1
Figure 27. CMR UVLO Low Test Circuit
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-3831EN - November 18, 2013
10R
10 nF
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