CY2304 3.3V Zero Delay Buffer Features ■ Zero input-output propagation delay, adjustable by capacitive load on FBK input required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. ■ Multiple configurations The CY2304 has two banks of two outputs each. ■ Multiple low-skew outputs ■ 10 MHz to 133 MHz operating range ■ 90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz ■ Space-saving 8-pin 150-mil SOIC package ■ 3.3V operation ■ Industrial temperature available The CY2304 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps. The CY2304 is available in two different configurations, as shown in Table 1 on page 1. The CY2304–1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. Functional Description The CY2304 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is The CY2304–2 allows the user to obtain Ref and 1/2x or 2x frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. Logic Block Diagram FBK CLKA1 PLL REF CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 Table 1. Available Configurations Device FBK from Bank A Frequency Bank B Frequency CY2304-1 Bank A or B Reference Reference CY2304-2 Bank A Reference Reference/2 CY2304-2 Bank B 2 × Reference Reference Pinouts Figure 1. 8-Pin SOIC - Top View REF CLKA1 CLKA2 GND Cypress Semiconductor Corporation Document #: 38-07247 Rev. *F • 1 2 3 4 198 Champion Court 8 7 6 5 FBK VDD CLKB2 CLKB1 • San Jose, CA 95134-1709 • 408-943-2600 Revised March 12, 2009 [+] Feedback CY2304 l Table 2. Pin Definitions - 8-Pin SOIC Pin Signal 1 REF[1] Description 2 CLKA1[2] 3 [2] CLKA2 4 GND 5 CLKB1[2] Clock output, Bank B 6 [2] CLKB2 Clock output, Bank B 7 VDD 3.3V supply 8 FBK PLL feedback input Input reference frequency, 5V tolerant input Clock output, Bank A Clock output, Bank A Ground Zero Delay and Skew Control Figure 2. REF. Input to CLKA/CLKB Delay vs. Difference in Loading Between FBK Pin and CLKA/CLKB Pins To close the feedback loop of the CY2304, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin is driving a total load of 7 pF, with any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in Figure 2. For applications requiring zero input-output delay, all outputs including the one providing feedback must be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. For further information on using CY2304, refer to the application note AN1234 “CY2308: Zero Delay Buffer.” Notes 1. Weak pull down. 2. Weak pull down on all outputs. Document #: 38-07247 Rev. *F Page 2 of 9 [+] Feedback CY2304 Maximum Ratings Supply Voltage to Ground Potential.................–0.5V to +7.0V Storage Temperature ..................................–65°C to +150°C DC Input Voltage (Except Ref) ...............–0.5V to VDD + 0.5V Junction Temperature ..................................................150°C DC Input Voltage REF.............................................–0.5 to 7V Static Discharge Voltage (per MIL-STD-883, Method 3015) .............................> 2000V Operating Conditions for CY2304SC-X Commercial Temperature Devices Parameter Description Min Max Unit 3.0 3.6 V 0 70 °C VDD Supply Voltage TA Operating Temperature (Ambient Temperature) CL Load Capacitance (below 100 MHz) – 30 pF Load Capacitance (from 100 MHz to 133 MHz) – 15 pF CIN Input Capacitance[3] – 7 pF tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms Electrical Characteristics for CY2304SC-X Commercial Temperature Devices Parameter Description Test Conditions Min Max Unit VIL Input LOW Voltage – 0.8 V VIH Input HIGH Voltage 2.0 – V IIL Input LOW Current VIN = 0V – 50.0 μA IIH Input HIGH Current VIN = VDD – 100.0 μA VOL Output LOW Voltage[4] IOL = 8 mA (–1, –2) – 0.4 V VOH Voltage[4] 2.4 – V Output HIGH IOH = –8 mA (–1, –2) IDD (PD mode) Power Down Supply Current REF = 0 MHz – 12.0 μA IDD Unloaded outputs, 100 MHz REF, Select inputs at VDD or GND – 45.0 mA Unloaded outputs, 66 MHz REF (–1,–2) – 32.0 mA Unloaded outputs, 33 MHz REF (–1,–2) – 18.0 mA Supply Current Switching Characteristics for CY2304SC-X Commercial Temperature Devices Parameter[5] Name Test Conditions Min Typ. Max Unit t1 Output Frequency 30 pF load, all devices 10 – 100 MHz t1 Output Frequency 15 pF load, –1, –2 devices 10 – 133.3 MHz Measured at 1.4V, FOUT = 66.66 MHz, 30 pF load 40.0 50.0 60.0 % 45.0 50.0 55.0 % Cycle[4] = t2 ÷ t1 tDC Duty (–1,–2) tDC Duty Cycle[4] = t2 ÷ t1 (–1,–2) Measured at 1.4V, FOUT < 50 MHz, 15 pF load t3 Rise Time[4] (–1, –2) Measured between 0.8V and 2.0V, 30 pF load – – 2.20 ns t3 Rise Time[4] (–1, –2) Measured between 0.8V and 2.0V, 15 pF load – – 1.50 ns Notes 3. Applies to both REF clock and FBK. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 5. All parameters are specified with loaded output. Document #: 38-07247 Rev. *F Page 3 of 9 [+] Feedback CY2304 Switching Characteristics for CY2304SC-X Commercial Temperature Devices (continued) Parameter[5] Name Min Typ. Max Unit Measured between 0.8V and 2.0V, 30 pF load – – 2.20 ns Fall Time[4] (–1, –2) Measured between 0.8V and 2.0V, 15 pF load – – 1.50 ns Output-to-Output Skew on same Bank (–1,–2)[4] All outputs equally loaded – – 200 ps Output Bank A to Output Bank B Skew (–1) All outputs equally loaded – – 200 ps Output Bank A to Output Bank B Skew (–2) All outputs equally loaded – – 400 ps t6 Skew, REF Rising Edge to FBK Rising Edge[4] Measured at VDD/2 – 0 ±250 ps t7 Device-to-Device Skew[4] Measured at VDD/2 on the FBK pins of devices – 0 500 ps tJ Cycle-to-Cycle Jitter[4] (–1) Measured at 66.67 MHz, loaded outputs, 15 pF load – 90 175 ps Measured at 66.67 MHz, loaded outputs, 30 pF load – – 200 ps Measured at 133.3 MHz, loaded outputs, 15 pF load – – 100 ps Measured at 66.67 MHz, loaded outputs 30 pF load – – 400 ps Measured at 66.67 MHz, loaded outputs 15 pF load – – 375 ps Stable power supply, valid clocks presented on REF and FBK pins – – 1.0 ms t4 Fall Time (–1, –2) [4] t4 t5 Test Conditions Cycle-to-Cycle Jitter[4] (–2) tJ tLOCK PLL Lock Time[4] Operating Conditions for CY2304SI-X Industrial Temperature Devices Parameter Description Min Max Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) –40 85 °C CL Load Capacitance (below 100 MHz) – 30 pF Load Capacitance (from 100 MHz to 133 MHz) – 15 pF Input Capacitance – 7 pF Min Max Unit – 0.8 V CIN Electrical Characteristics for CY2304SI-X Industrial Temperature Devices Parameter Description VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current IIH Input HIGH Current VOL VOH Test Conditions – V – 50.0 μA VIN = VDD – 100.0 μA [4] IOL = 8 mA (–1, –2) – 0.4 V [4] IOH = –8 mA (–1, –2) 2.4 – V Output LOW Voltage Output HIGH Voltage Document #: 38-07247 Rev. *F 2.0 VIN = 0V Page 4 of 9 [+] Feedback CY2304 Electrical Characteristics for CY2304SI-X Industrial Temperature Devices (continued) Parameter Description Min Max IDD (PD mode) Power Down Supply Current REF = 0 MHz – 25.0 μA IDD Unloaded outputs, 100 MHz, Select inputs at VDD or GND – 45.0 mA Unloaded outputs, 66 MHz REF (–1, –2) – 35.0 mA Unloaded outputs, 33 MHz REF (–1, –2) – 20.0 mA Supply Current Test Conditions Unit Switching Characteristics for CY2304SI-X Industrial Temperature Devices Parameter[5] Name Test Conditions Min Typ. Max Unit t1 Output Frequency 30 pF load, All devices 10 100 MHz t1 Output Frequency 15 pF load, All devices 10 133.3 MHz Cycle[4] tDC Duty (–1,–2) tDC = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66 MHz, 30 pF load 40.0 50.0 60.0 % Duty Cycle[4] = t2 ÷ t1 (–1,–2) Measured at 1.4V, FOUT < 50 MHz, 15 pF load 45.0 50.0 55.0 % t3 Rise Time[4] (–1, –2) Measured between 0.8V and 2.0V, 30 pF load – – 2.50 ns t3 Rise Time[4] (–1, –2) Measured between 0.8V and 2.0V, 15 pF load – – 1.50 ns t4 Fall Time[4] (–1, –2) Measured between 0.8V and 2.0V, 30 pF load – – 2.50 ns t4 Fall Time[4] (–1, –2) Measured between 0.8V and 2.0V, 15 pF load – – 1.50 ns t5 Output-to-Output Skew on same Bank (–1,–2)[4] All outputs equally loaded – – 200 ps Output Bank A to Output Bank B Skew (–1) All outputs equally loaded – – 200 ps Output Bank A to Output Bank B Skew (–2) All outputs equally loaded – – 400 ps t6 Skew, REF Rising Edge to FBK Rising Edge[4] Measured at VDD/2 – 0 ±250 ps t7 Device-to-Device Skew[4] Measured at VDD/2 on the FBK pins of devices – 0 500 ps tJ Cycle-to-Cycle Jitter[4] (–1) Measured at 66.67 MHz, loaded outputs, 15 pF load – – 180 ps Measured at 66.67 MHz, loaded outputs, 30 pF load – – 200 ps Measured at 133.3 MHz, loaded outputs, 15 pF load – – 100 ps Measured at 66.67 MHz, loaded outputs, 30 pF load – – 400 ps Measured at 66.67 MHz, loaded outputs, 15 pF load – – 380 ps Stable power supply, valid clocks presented on REF and FBK pins – – 1.0 ms tJ tLOCK Cycle-to-Cycle Jitter[4] (–2) PLL Lock Time[4] Document #: 38-07247 Rev. *F Page 5 of 9 [+] Feedback CY2304 Switching Waveforms Figure 2. Duty Cycle Timing t1 t2 1.4V 1.4V 1.4V Figure 3. All Outputs Rise/Fall Time OUTPUT 2.0V 0.8V 2.0V 0.8V t3 3.3V 0V t4 Figure 4. Output-Output Skew OUTPUT 1.4V 1.4V OUTPUT t5 Figure 5. Input-Output Skew INPUT VDD/2 VDD/2 FBK t6 Figure 6. Device-Device Skew VDD/2 FBK, Device 1 VDD/2 FBK, Device 2 t7 Document #: 38-07247 Rev. *F Page 6 of 9 [+] Feedback CY2304 Figure 7. Test Circuit # 1 VDD 0.1 μF OUTPUTS CLK OUT C LOAD V DD 0.1 μF GND GND Test circuit for all parameters except t8 Ordering Information Ordering Code [6] Package Type Operating Range 8-pin 150-mil SOIC Commercial CY2304SC–1T[6] 8-pin 150-mil SOIC - Tape and Reel Commercial CY2304SI–1[6] 8-pin 150-mil SOIC Industrial CY2304SI–1T[6] 8-pin 150-mil SOIC- Tape and Reel Industrial CY2304SC–2[6] 8-pin 150-mil SOIC Commercial CY2304SC–2T[6] 8-pin 150-mil SOIC- Tape and Reel Commercial CY2304SXC–1 8-pin 150-mil SOIC Commercial CY2304SXC–1T 8-pin 150-mil SOIC - Tape and Reel Commercial CY2304SXI–1 8-pin 150-mil SOIC Industrial CY2304SXI–1T 8-pin 150-mil SOIC- Tape and Reel Industrial CY2304SXC–2 8-pin 150-mil SOIC Commercial CY2304SXC–2T 8-pin 150-mil SOIC- Tape and Reel Commercial CY2304SXI–2 8-pin 150-mil SOIC Industrial CY2304SXI–2T 8-pin 150-mil SOIC- Tape and Reel Industrial CY2304SC–1 Pb-Free Note 6. Not recommended for new designs. Document #: 38-07247 Rev. *F Page 7 of 9 [+] Feedback CY2304 Package Drawing and Dimensions Figure 8 Lead (150 Mil) SOIC S088. 8-Pin (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] Document #: 38-07247 Rev. *F 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85066-*C Page 8 of 9 [+] Feedback CY2304 Document History Page Document Title: CY2304 3.3V Zero Delay Buffer Document Number: 38-07247 Rev. ECN Orig. of Change Submission Date ** 110512 SZV 12/11/01 Description of Change Change from Spec number: 38-01010 to 38-07247 *A 112294 CKN 03/04/02 On Pin Configuration Diagram (p.1), swapped CLKA2 and CLKA1 *B 113934 CKN 05/01/02 Added Operating Conditions for CY2304SI-X Industrial Temperature Devices, p. 4 *C 121851 RBI 12/14/02 Power up requirements added to Operating Conditions Information *D 308436 RGL 01/26/05 Added Lead-free Devices *E 2542331 AESA 09/18/08 Updated template. Added Note “Not recommended for new designs.” Removed part number CY2304SI-2 and CY2304SI-2T. Changed Lead-Free to Pb-Free. Changed IDD (PD mode) from 12.0 to 25.0 μA. Deleted Duty Cycle parameters for FOUT < 50.0 MHz for commercial and industrial devices. *F 2673353 KVM/PYRS 03/13/09 Reverted IDD (PD mode) and Duty Cycle parameters back to the values in revision *D: Changed IDD (PD mode) from 25 to 12 μA for commercial devices. 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Document #: 38-07247 Rev. *F Revised March 12, 2009 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback