F1975 Datasheet 6-Bit, 75 Ω, Digital Step Attenuator 5 to 3000 MHz General Description FEATURES This document describes the specification for the IDT F1975 Digital Step Attenuator. The F1975 is part of a family of Glitch-FreeTM DSAs optimized for the demanding requirements of CATV and Satellite systems. This device is offered in a compact 4 mm x 4 mm 20 pin Thin QFN package with 75 Ω impedance for ease of integration. • • • • • • • • • • • • • • • COMPETITIVE ADVANTAGE Digital step attenuators are used in Receivers and Transmitters to provide gain control. The F1975 is a 6-bit step attenuator optimized for these demanding applications. The silicon design has very low insertion loss and low distortion (+64 dBm IIP3). The device has pinpoint attenuation accuracy. Most importantly, the F1975 includes IDT’s Glitch-FreeTM technology which results in low overshoot & ringing during MSB transitions. Serial & 6-Bit Parallel Interface 31.5 dB Control Range 0.5 dB step Glitch-FreeTM, low transient overshoot 3.0 V to 5.25 V supply 1.8 V or 3.3 V control logic Attenuator Step Error: 0.1 dB @ 1 GHz Low Insertion Loss: 1.2 dB @ 1 GHz Ultra linear IIP3: +64 dBm IIP2: +125 dBm typical Stable Integral Non-Linearity over temperature Low Current Consumption: 550 µA typical Bi-Directional -40 °C to +105 °C Operating Temperature 4 mm x 4 mm Thin QFN 20 pin package FUNCTIONAL BLOCK DIAGRAM TM Glitch-Free Technology protects PA or ADC from damage during transitions between attenuation states. Extremely accurate attenuation levels Ultra low distortion Lowest insertion loss for best SNR APPLICATIONS • • • • • CATV Infrastructure CATV Set-Top Boxes CATV Satellite Modems Data Network Equipment Fiber Networks ORDERING INFORMATION Tape & Reel F1975NCGI8 Green F1975, Rev O 01/15/2016 1 © 2016 Integrated Device Technology, Inc. F1975 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units VDD to GND VDD -0.3 +5.5 V DATA, LE, CLK, D[5:0] VLogic -0.3 Min (VDD+0.3, 3.6) V RF1, RF2 VRF -0.3 +0.3 V Maximum Input Power applied to RF1 or RF2 (>100 MHz) PRF +34 dBm TJmax +140 °C 150 °C 260 °C Maximum Junction Temperature Storage Temperature Range Tst -65 Lead Temperature (soldering, 10 s) Electrostatic Discharge – HBM (JEDEC/ESDA JS-001-2012) VESDHBM 2000 (Class 2) Volts ESD Voltage – CDM (Per JESD22-C101F) VESDCDM 250 (Class C1) Volts Stresses above those listed above may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION This product features proprietary protection circuitry. However, it may be damaged if subjected to high energy ESD. Please use proper ESD precautions when handling to avoid damage or loss of performance. PACKAGE THERMAL AND MOISTURE CHARACTERISTICS θJA (Junction – Ambient) 50 °C/W θJC (Junction – Case) [The Case is defined as the exposed paddle] Moisture Sensitivity Rating (Per J-STD-020) 6-Bit, 75 Ω, Digital Step Attenuator 3 °C/W MSL1 2 Rev O 01/15/2016 F1975 F1975 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Supply Voltage(s) Conditions VDD Frequency Range FRF Min Typ Max Units 3.00 5.25 V 5 3000 MHz -40 105 °C See Figure 1 dBm Operating Temperature Range TCASE Exposed Paddle RF CW Input Power PCW RF1 or RF2 RF1 Impedance ZRF1 Single Ended 75 Ω RF2 Impedance ZRF2 Single Ended 75 Ω 32 Max CW PIN (dBm) 28 24 20 16 12 8 4 0 0.01 0.10 1.00 10.00 100.00 1000.00 Frequency (MHz) Figure 1 Maximum Continuous Operating RF input power versus Input Frequency Rev O 01/15/2016 3 6-Bit, 75 Ω, Digital Step Attenuator F1975 F1975 SPECIFICATION Specifications apply at VDD = +3.3 V, TCASE = +25 °C, FRF = 1000 MHz, Pin = 0 dBm, Serial Mode, ZRF1 = ZRF2 = 75 Ω, unless otherwise noted. EvKit losses are de-embedded. Parameter Symbol Logic Input High VIH Conditions All Control Pins VDD > 3.6 V 3.0 ≤ VDD ≤ 3.6 V All Control Pins All Control Pins VDD = 3.3 V Min Typ 1.17 1.17 Max Units 3.6 V V V µA VDD 0.63 +35 8301 900 Logic Input Low Logic Current VIL IIH, IIL Supply Current IDD RF1 Return Loss RF2 Return Loss Attenuation Step Insertion Loss (Minimum Attenuation) Attenuation Range Step Error Absolute Error S11 S22 LSB Least Significant Bit 620 18 18 0.5 AMIN D[5:0]=[000000] (IL State) 1.2 2.0 dB ARANGE DNL INL D[5:0]=[111111]=31.5 dB 30.52 31.1 0.1 31.7 D[5:0]=[100111]= 19.5 dB At 0.5 GHz (AMAX to AMIN) At 1.0 GHz (AMAX to AMIN) PIN = +10 dBm/tone, F1 = 900 MHz, F2 = 950 MHz Attn = 0.0 dB, RFIN = RF1 Attn =15.5 dB, RFIN = RF1 PIN = +12 dBm/tone, F1= 945 MHz, F2 = 949 MHz F1+F2 = 1894 MHz RFIN= RF1 PIN = +15 dBm, RFIN = 945 MHz RFOUT = 1890 MHz RFIN Port = RF1 D[5:0] = [000000] = AMIN, RFIN = RF1 -0.7 dB dB dB Insertion Phase Delta Φ∆ Input IP3 IIP3 Input IP2 IIP2 Second Harmonic H2 0.1dB Compression3 P0.1 Note 1: Note 2: Note 3: Note 4: Note 5: -35 550 VDD = 5.0 V 60 59 dB dB dB +0.5 10 20 µA degrees 64 62 dBm 125 dBm 108 dBc 30.5 dBm Items in min/max columns in bold italics are Guaranteed by Test. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. The input 0.1dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input power. Measured in a 50 ohm system. Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2 MHz. Speeds are measured after SPI programming is completed (data latched with LE = HIGH). 6-Bit, 75 Ω, Digital Step Attenuator 4 Rev O 01/15/2016 F1975 F1975 SPECIFICATION (CONTINUED) Specifications apply at VDD = +3.3 V, TCASE = +25 °C, FRF = 1000 MHz, Pin = 0 dBm, Serial Mode, ZRF1 = ZRF2 = 75 Ω, unless otherwise noted. EvKit losses are de-embedded. Parameter MSB Step Time Maximum spurious level on any RF port4 Maximum Switching Rate DSA Settling time5 Control Interface Serial Clock Speed Note 1: Note 2: Note 3: Note 4: Note 5: Symbol Conditions TLSB Start at LE rising edge End ±0.10 dB Pout settling for 15.5 dB to 16.0 dB transition SpurMAX SWRATE τSET Max to Min Attenuation to settle to within 0.5 dB of final value Min to Max Attenuation to settle to within 0.5 dB of final value SPIBIT SPICLK Min Typ Max Units 500 ns -130 dBm 25 kHz 0.9 µs 1.8 6 10 25 bit MHz Items in min/max columns in bold italics are Guaranteed by Test. Items in min/max columns that are not bold/italics are Guaranteed by Design Characterization. The input 0.1dB compression point is a linearity figure of merit. Refer to Absolute Maximum Ratings section for the maximum RF input power. Spurious due to on-chip negative voltage generator. Typical generator fundamental frequency is 2.2 MHz. Speeds are measured after SPI programming is completed (data latched with LE = HIGH). Rev O 01/15/2016 5 6-Bit, 75 Ω, Digital Step Attenuator F1975 PROGRAMMING OPTIONS F1975 can be programmed using either the parallel or serial interface which is selectable via VMODE (pin 13). Serial Mode is selected by floating VMODE or pulling it to a logic high and parallel mode is selected by setting VMODE to a logic low. SERIAL CONTROL MODE F1975 Serial Mode is selected by floating VMODE (pin 13) or pulling it to a logic high. The serial interface is a 6bit shift register and shifts in the MSB (D5) first. When serial programming is used, all the parallel control input pins (1, 15, 16, 17, 19, 20) must be grounded. Table 1 - 6 Bit SPI Word Sequence D5 Attenuation 16 dB Control Bit D4 Attenuator 8 dB Control Bit D3 Attenuator 4 dB Control Bit D2 Attenuator 2 dB Control Bit D1 Attenuator 1 dB Control Bit D0 Attenuator 0.5 dB Control Bit Table 2 - Truth Table for Serial Control Word D5 (MSB) D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 0 0 0 1 0.5 0 0 0 0 1 0 1 0 0 0 1 0 0 2 0 0 1 0 0 0 4 0 1 0 0 0 0 8 1 0 0 0 0 0 16 1 1 1 1 1 1 31.5 6-Bit, 75 Ω, Digital Step Attenuator 6 D0 Attenuation (LSB) (dB) Rev O 01/15/2016 F1975 Serial Mode Register Timing Diagram: (Note the Timing Spec Intervals in Blue) The F1975 can be programmed via the serial port on the rising edge of Latch Enable (LE). Refer to Figure 2. Figure 2 - Serial Register Timing Diagram Note - When Latch enable is high, the shift register is disabled and DATA is NOT continuously clocked into the shift register which minimizes noise. It is recommended that Latch Enable be left high when the device is not being programmed. Table 3 - Serial Mode Timing Table Interval Symbol Description Min Spec tmc Parallel to Serial Setup Time - From rising edge of VMODE to rising edge of CLK for D5 100 ns tds Clock high pulse width 10 ns tcls LE Setup Time - From the rising edge of CLK pulse for D0 to LE rising edge minus half the clock period. 10 ns tlew LE pulse width 30 ns tdsc Data Setup Time - From the starting edge of Data bit to rising edge of CLK 10 ns Tdht Data Hold Time - From rising edge of CLK to falling edge of the Data bit. 10 ns Rev O 01/15/2016 7 Max Spec Units 6-Bit, 75 Ω, Digital Step Attenuator F1975 Serial Mode Default Startup Condition: When the device is first powered up it will default to the Maximum Attenuation of 31.5 dB independent of the VMODE and parallel pin [D5:D0] conditions. Table 4 - Default Control Word for the Serial Mode D5 (MSB) D4 D3 D2 D1 1 1 1 1 1 D0 Attenuation (LSB) (dB) 1 31.5 PARALLEL CONTROL MODE For the F1975 the user has the option of running in one of two parallel modes: Direct Parallel Mode or Latched Parallel Mode. Direct Parallel Mode: Direct Parallel Mode is selected when VMODE (pin 13) is set to a logic low and LE (pin 5) is set to a logic high. In this mode the device will immediately react to any voltage changes to the parallel control pins (1, 15, 16, 17, 19, 20). Use direct parallel mode for the fastest settling time. Direct Parallel Default Startup Condition: Attenuation value using Direct Parallel Mode is determined by logic condition of the parallel pins (1, 15, 16, 17, 19, 20) at the time of start up. Latched Parallel Mode: Latched Parallel Mode is selected when VMODE is set to a logic low and LE (pin 5) is toggled from a logic low to a logic high. To utilize Latched Parallel Mode: • Set LE to a logic low. • Set pins (1, 15, 16, 17, 19, 20) for desired attenuation setting. (While LE is set to a logic low, the attenuation state will not change.) • Toggle LE to a logic high. The device will then transition to the attenuation settings reflected by pins D5 – D0. Latched Parallel Default Startup Condition: Latched Parallel Mode establishes a default attenuation state when the device is first powered up. The default setting is MAXIMUM Attenuation. Table 5 - Truth Table for the Parallel Pins D5 D4 D3 D2 D1 D0 Attenuation (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0.5 0 0 0 0 1 0 1 0 0 0 1 0 0 2 0 0 1 0 0 0 4 0 1 0 0 0 0 8 1 0 0 0 0 0 16 1 1 1 1 1 1 31.5 6-Bit, 75 Ω, Digital Step Attenuator 8 Rev O 01/15/2016 F1975 Figure 3 - Latched Parallel Mode Timing Diagram Table 6 - Latched Parallel Mode Timing Interval Symbol tsps tpdh tpds tle Rev O 01/15/2016 Description Serial to Parallel Mode Setup Time Parallel Data Hold Time LE minimum pulse width Parallel Data Setup Time 9 Min Spec 100 10 10 10 Max Spec Units ns ns ns ns 6-Bit, 75 Ω, Digital Step Attenuator F1975 TYPICAL OPERATING CONDITIONS (TOC) Unless otherwise noted for the TOC graphs on the following pages, the following conditions apply. • • • • • • • • VDD = +3.30 V TCASE = +25 °C FRF = 1 GHz PIN = 0 dBm for single tone measurements PIN = +10 dBm/tone for multi-tone measurements Tone Spacing = 50 MHz EVKit connector and board losses are de-embedded Measured in a 75 ohm system unless otherwise specified 6-Bit, 75 Ω, Digital Step Attenuator 10 Rev O 01/15/2016 F1975 TYPICAL OPERATING CONDITIONS (- 1 -) Insertion Loss vs Frequency Insertion Loss vs Attenuation State 0.0 0 1 GHz, -40 C -40 C +25 C 1 GHz, +25 C -5 +105 C Insertion Loss (dB) Insertion Loss (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 1 GHz, +105 C -10 -15 -20 -25 -30 -3.5 -4.0 -35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency (GHz) Attenuation (dB) RF1 Return Loss vs Attenuation State 0 0 -5 -5 -10 -10 -15 -15 Match(dB) Match (dB) RF1 Return Loss vs Frequency (All States) -20 -25 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz -20 -25 -30 -30 -35 -35 -40 0.01 GHz -40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency (GHz) Attenuation (dB) RF2 Return Loss vs Attenuation State 0 0 -5 -5 -10 -10 -15 -15 Match (dB) Match (dB) RF2 Return Loss vs Frequency (All States) -20 -25 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz -20 -25 -30 -30 -35 -35 -40 0.01 GHz -40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 Frequency (GHz) Rev O 01/15/2016 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation (dB) 11 6-Bit, 75 Ω, Digital Step Attenuator F1975 TYPICAL OPERATING CONDITIONS (- 2 -) Relative Insertion Phase vs Attenuation 45 45 40 40 35 35 Phase (degrees) Phase (degrees) Relative Insertion Phase vs Frequency (All States) 30 25 20 15 10 5 0.01 GHz 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz 30 25 20 15 10 5 0 0 -5 -5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency (GHz) Attenuation (dB) Worst Case Absolute Accuracy Error Accuracy Error vs Attenuation 0.5 0.5 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz 0.0 Error (dB) Error (dB) 0.0 0.01 GHz -0.5 -1.0 -1.5 -40 C Min +25 C Min +105 C Min -0.5 -1.0 -1.5 -40 C Max +25 C Max +105 C Max -2.0 -2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency (GHz) Attenuation (dB) Worst Case Step Accuracy Step Error vs Attenuation 0.3 0.3 -40 C Min +25 C Min +105 C Min 0.2 -40 C Max +25 C Max +105 C Max 0.50 GHz 0.75 GHz 1.00 GHz 1.25 GHz 1.50 GHz 1.75 GHz 2.00 GHz 0.2 0.1 Error (dB) 0.1 Error (dB) 0.01 GHz 0.0 0.0 -0.1 -0.1 -0.2 -0.2 -0.3 -0.3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 Frequency (GHz) 6-Bit, 75 Ω, Digital Step Attenuator 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation (dB) 12 Rev O 01/15/2016 F1975 TYPICAL OPERATING CONDITIONS (- 3 -) Compression [Attenuation = 0.0 dB] Input IP3 0.5 75 0.005 GHz 0.050 GHz 0.100 GHz 1.000 GHz 1.500 GHz 2.000 GHz 0.500 GHz 70 65 Input IP3 (dBm) Compression (dB) 0.0 -0.5 -1.0 -1.5 60 55 50 45 40 35 0.035 GHz 0.065 GHz 0.130 GHz 0.920 GHz 1.400 GHz 2.000 GHz 0.500 GHz 30 Measured in a 50 ohm system -2.0 25 16 18 20 22 24 26 28 30 32 34 0 Input Power (dBm) Rev O 01/15/2016 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Attenuation Setting (dB) 13 6-Bit, 75 Ω, Digital Step Attenuator F1975 PACKAGE DRAWING (4 mm x 4 mm 24-pin TQFN), NCG20 LAND PATTERN DIMENSION 6-Bit, 75 Ω, Digital Step Attenuator 14 Rev O 01/15/2016 F1975 PIN DIAGRAM D0 D1 NC D2 D3 TOP View (looking through the top of the package) 20 19 18 17 16 D5 1 15 D4 *RF1 2 14 *RF2 DATA 3 13 VMODE CLK 4 12 NC LE 5 11 GND 9 10 GND NC 8 NC 7 NC 6 VDD Exposed Pad * Device is RF Bi-Directional Rev O 01/15/2016 15 6-Bit, 75 Ω, Digital Step Attenuator F1975 PIN DESCRIPTION PIN NAME 1 D5 16 dB Attenuation Control Bit. Activated by Logic High (see page 8) 2 RF1 Device RF input or output (bi-directional). 3 DATA Serial interface Data Input 4 CLK Serial interface Clock Input 5 LE 6 VDD 7 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended) 8 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended) 9 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended) 10 GND Connect to Ground. This pin is internally connected to the exposed paddle 11 GND Connect to Ground. This pin is internally connected to the exposed paddle 12 NC 13 VMODE 14 RF2 Device RF input or output (bi-directional). 15 D4 8 dB Attenuation Control Bit. Activated by Logic High (see page 8) 16 D3 4 dB Attenuation Control Bit. Activated by Logic High (see page 8) 17 D2 2 dB Attenuation Control Bit. Activated by Logic High (see page 8) 18 NC No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended). 19 D1 1 dB Attenuation Control Bit. Activated by Logic High (see page 8) 20 D0 0.5 dB Attenuation Control Bit. Activated by Logic High (see page 8) EP Exposed Paddle 6-Bit, 75 Ω, Digital Step Attenuator FUNCTION Serial interface Latch Enable Input. Internal pullup (100 kohm) Power supply pin No internal connection. These pins can be left unconnected, voltage applied, or connected to ground (recommended) Pull high for serial control mode. Ground for parallel control mode. Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the specified RF performance. 16 Rev O 01/15/2016 F1975 EVKIT PICTURE Rev O 01/15/2016 17 6-Bit, 75 Ω, Digital Step Attenuator F1975 EVKIT / APPLICATIONS CIRCUIT 6-Bit, 75 Ω, Digital Step Attenuator 18 Rev O 01/15/2016 F1975 EVKIT BOM (REV 1) Item # QTY DESCRIPTION Mfr. Part # Mfr. C1, C11, C15 3 100nF ±10%, 16V, X7R Ceramic Capacitor (0402) GRM155R71C104K MURATA 2 C2, C10 2 10nF ±5%, 50V, X7R Ceramic Capacitor (0603) GRM188R71H103J MURATA 3 C3, C4, C5, C6, C7, C8, C9, C12, C13, C14 10 100pF ±5%, 50V, C0G Ceramic Capacitor (0402) GRM1555C1H101J MURATA 4 R3, R4, R5, R6, R7, R8, R9 7 100Ω ±1%, 1/10W, Resistor (0402) ERJ-2RKF1000X PANASONIC 5 R10-R13, R15-R18, R24-R27 12 0Ω Resistors (0402) ERJ-2GE0R00X PANASONIC 6 R21, R22, R23 3 3kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF3001X PANASONIC 7 R1 1 100kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF1003X PANASONIC 8 R2 1 267kΩ ±1%, 1/10W, Resistor (0402) ERJ-2RKF2673X PANASONIC 1 Part Reference 9 J2, J3, J5 3 CONN HEADER VERT SGL 2 X 1 POS GOLD 961102-6404-AR 3M 10 J11 1 CONN HEADER VERT DBL 4 X 2 POS GOLD 67997-108HLF FCI 11 J4 1 CONN HEADER VERT SGL 9 X 1 POS GOLD 961109-6404-AR 3M Edge Launch SMA (0.250 inch pitch ground, round) 142-0711-821 Emerson Johnson 12 J1, J8 2 13 J6, J7 2 Edge Launch F TYPE 75 ohm 222181 Amphenol 14 U2 1 SWITCH 8 POSITION DIP SWITCH KAT1108E E-Switch 15 U1 1 DSA F1975 IDT 1 Printed Circuit Board F1975 Evkit Rev 01 IDT 16 TOP MARKINGS Part Number IDTF19 75NCGI ZA515BEG ASM Test Step Rev O 01/15/2016 Assembler Code Date Code [YWW] (Week 5 of 2015) 19 6-Bit, 75 Ω, Digital Step Attenuator F1975 APPLICATIONS INFORMATION F1975 Digital Pin Voltage & Resistance Values (pins not connected) The following table lists the resistance between various pins and ground when no DC power is applied. When the device is powered up with +5 Volts DC, these pins will exhibit a voltage to ground as indicated. Pin Name DC voltage (volts) 13 VMODE 2.5 V 3, 4, 5 DATA, CLK, LE 2.5 V 6-Bit, 75 Ω, Digital Step Attenuator 20 Resistance (ohms) 100 kΩ pullup resistor to internally regulated 2.5 V 100 kΩ pullup resistor to internally regulated 2.5 V Rev O 01/15/2016 F1975 REVISION HISTORY SHEET Rev Date O 2016-01-15 Rev O 01/15/2016 Page Description of Change Initial Release 21 6-Bit, 75 Ω, Digital Step Attenuator F1975 Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.idt.com Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved. 6-Bit, 75 Ω, Digital Step Attenuator 22 Rev O 01/15/2016