ISL54003, ISL54005, ISL54006 ® Data Sheet October 30, 2007 FN6514.2 Integrated Audio Amplifier Systems Features The Intersil ISL54003, ISL54005, ISL54006 family of devices are integrated audio power amplifier systems that combine a mono BTL amplifier and stereo headphone amplifiers in a single device. The devices are designed to operate from a single +2.7V to +5V power supply. Targeted applications include handheld equipment such as cell-phones, MP3 players, and games/toys. • Pb-Free (RoHS Compliant) These parts contain one class AB BTL type power amplifier for driving an 8Ω mono speaker and two class AB headphone amplifiers for driving 16Ω or 32Ω headphone speakers. • Class AB 94mW Headphone Amplifiers and 941mW Mono BTL Speaker Amplifier • THD+N at 1kHz, 800mW into 8Ω BTL. . . . . . . . . . . . . . 0.4% • THD+N at 1kHz, 15mW into 32Ω Headphone . . . . . . 0.07% • THD+N at 1kHz, 50mW into 32Ω Headphone . . . . . . . 0.3% • Single Supply Operation. . . . . . . . . . . . . . . . . +2.7V to +5.5V • Headphone Sense Input and Low Power Shutdown The BTL when using a 5V supply is capable of delivering 800mW (typ) with 0.4% THD+N and 941mW (typ) with 1% THD+N of continuous average power into an 8Ω BTL speaker load. • Thermal Shutdown Protection Each headphone amplifier when using a 5V supply is capable of delivering 50mW (typ) with 0.3% THD+N and 94mW (typ) with 1% THD+N of continuous average power into a 32Ω headphone speaker. • Mixing of Two Stereo Inputs (ISL54006) When in Mono Mode these devices automatically mix the active left and right audio inputs and send the combined signal to the BTL driver. In Headphone Mode the active right channel input is sent to the right headphone speaker and the active left channel is sent to the left headphone speaker. Applications The ISL54005 and ISL54006 feature a 2:1 stereo input multiplexer front-end. This allows selection between two stereo sources. In addition the ISL54006 can mix the four inputs to the BTL driver or the two pairs of inputs to the headphone drivers. These parts feature headphone sense circuitry that detects when a headphone jack has been inserted and automatically switches the active audio inputs from the mono BTL output driver to the headphone drivers. These parts also feature a logic control pin that can override the headphone sense input circuitry. All devices in this family feature low power shutdown, thermal overload protection and click/pop suppression. The click and pop circuitry eliminates audible transients during audio source changes and transitioning in and out of shutdown. • “Click and Pop” Suppression Circuitry • 2:1 Stereo Input Mux (ISL54005, ISL54006) • TTL Logic-Compatible • Available in 20 Ld 4x4 Thin QFN • Battery powered, Handheld, and Portable Equipment - Cellular/mobile Phones - PDA’s, MP3 Players, DVD Players, Cameras - Laptops, Notebooks, Palmtops - Handheld Games and Toys • Desktop Computers Simplified Block Diagram VDD R1 L1 ROUTER/ MIXER R2 L2 CLICK AND POP SD INS MIX HO BIAS LOGIC CONTROL THERMAL SHUTDOWN ISL54006 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL54003, ISL54005, ISL54006 Pinouts Pin Descriptions ISL54003 (20 LD 4X4 TQFN) TOP VIEW PIN GND NC NC INR NC ISL54003 ISL54005 ISL54006 NAME 3, 6, 12 20 19 18 17 16 4, 9, 20 SPK- 1 15 HO SPK+ 2 14 SD VDD 3 13 NC GND 4 12 VDD HpR 5 11 INL 6 7 8 9 10 VDD HpL HD GND REF GND IN2R INS IN1R NC ISL54005 (20 LD 4X4 TQFN) TOP VIEW 20 19 18 17 16 14 SD VDD 3 13 IN2L GND 4 12 VDD HpR 5 11 IN1L 6 7 8 9 10 REF 2 GND SPK+ HD 15 HO HpL 1 VDD SPK- GND IN2R INS IN1R MIX ISL54006 (20 LD 4X4 TQFN) TOP VIEW 20 19 18 17 16 14 SD VDD 3 13 IN2L GND 4 12 VDD HpR 5 11 IN1L 6 7 8 9 10 REF 2 GND SPK+ HD 15 HO HpL 1 VDD SPK- 2 3, 6, 12 3, 6, 12 VDD System Power Supply 4, 9, 20 4, 9, 20 GND Ground Connection INL Left Channel Audio Input 1 11 - FUNCTION 11 11 IN1L Left Channel Audio Input 1 13 13 IN2L Left Channel Audio Input 2 INR Right Channel Audio Input 1 17 17 17 IN1R Right Channel Audio Input 1 - 19 19 IN2R Right Channel Audio Input 2 5 5 5 HpR Headphone Right Ouput 7 7 7 HpL Headphone Left Ouput 2 2 2 SPK+ Positive Speaker Output 1 1 1 SPK- Negative Speaker Output 14 14 14 SD Shutdown, High to disable amplifiers, Low for normal operation. 8 8 8 HD Headphone Detection, Internally pulled up to VDD, Low in Mono Mode, High in Headphone Mode if HO = Low 15 15 15 HO Headphone Override, High in Mono Mode, Low in Headphone Mode if HD = High - 18 18 INS Input Select - - 16 MIX Mixer, High to mix Right and Left Audio Inputs, Low to pass Audio Inputs without mixing 10 10 10 REF Common-mode Bias Voltage, Bypass with a 1µF capacitor to GND. 13, 16, 18, 19 16 NC No Connect FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 Ordering Information PART NUMBER (Note) PART MARKING TEMP. RANGE (°C) ISL54003 Truth Table PACKAGE Tape & Reel (Pb-Free) PKG. DWG. # ISL54003IRTZ* 540 03IRTZ -40 to +85 20 Ld 4x4 TQFN L20.4x4A ISL54005IRTZ* 540 05IRTZ -40 to +85 20 Ld 4x4 TQFN L20.4x4A ISL54006IRTZ* 540 06IRTZ -40 to +85 20 Ld 4x4 TQFN L20.4x4A *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. SD HD HO SPK+/SPK- HpR HpL 1 X X Disabled Disabled Disabled 0 0 X INR + INL - - 0 1 0 - INR INL 0 1 1 INR + INL - - ISL54005 Truth Table SD INS HD HO SPK+/SPK- HpR HpL 1 X X X Disabled Disabled Disabled 0 0 0 X IN1R + IN1L - - 0 0 1 0 - IN1R IN1L 0 0 1 1 IN1R + IN1L - - 0 1 0 X IN2R + IN2L - - 0 1 1 0 - IN2R IN2L 0 1 1 1 IN2R + IN2L - - ISL54006 Truth Table SD 3 MIX INS HD HO SPK+/SPK- HpR HpL 1 X X X X Disabled Disabled Disabled 0 0 0 0 X IN1R + IN1L - - 0 0 0 1 0 - IN1R IN1L 0 0 0 1 1 IN1R + IN1L - - 0 0 1 0 X IN2R + IN2L - - 0 0 1 1 0 - IN2R IN2L 0 0 1 1 1 IN2R + IN2L - - 0 1 X 0 X IN1R + IN2R + IN1L + IN2L - - 0 1 X 1 0 - IN1R + IN2R IN1L + IN2L 0 1 X 1 1 IN1R + IN2R + IN1L + IN2L - - FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 Absolute Maximum Ratings Thermal Information VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5V Input Voltages In_R, In_L, SD, INS, MIX, H_. . . . . . . . . . . . -0.3 to (VDD + 0.3V) Output Voltages SPK+, SPK-, Hp_ . . . . . . . . . . . . . . . . . . . . . -0.3 to (VDD + 0.3V) Continuous Current (VDD, SPK_, Hp_, GND) . . . . . . . . . . . . 750mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) 20 Ld 4x4 TQFN Package . . . . . . . . . . 45 6.5 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications - 5V Supply PARAMETER Test Conditions: VDD = +5V, GND = 0V, VINH = 2.4V, VINL = 0.8V, SD = MIX = INS = HD = VINL, CREF = 1µF, RL is terminated between SPK+ and SPK- for BTL driver and between Hp_ and GND for SE drivers, Unless Otherwise Specified (Note 3). TEST CONDITIONS TEMP (°C) MIN (Notes 4, 5) TYP MAX (Notes 4, 5) UNITS Full 2.7 - 5.5 V 25 - 4.6 12 mA Full - 5.5 - mA GENERAL Power Supply Range, VDD Quiescent Supply Current, IDD HO = VINL or VINH, HD = VINL, INS = VINL or VINH, MIX = VINL or VINH, RL = None, Inputs AC coupled to ground (0.13µF) SD = VINH, HO = VINL or VINH, HD = VINL, INS = VINL or VINH, MIX = VINL or VINH, RL = 8Ω (BTL) and RL = 32Ω (SE), Inputs AC coupled to ground (0.1µF) 25 - 28 50 µA Full - 31 - µA Input Resistance, RIN INS = 0V or VDD 25 - 100 - kΩ Thermal Shutdown, TSD INS = MIX = 0V or VDD 25 - 150 - °C 25 - 10 - °C Full - 1 - ms Shutdown Supply Current, ISD Thermal Shutdown Hysteresis SD to Full Operation, tSD(ON) INS = 0V or 5V, MIX = 0V or 5V BTL AMPLIFIER DRIVER, HD = VINH, HO = VINH, UNLESS OTHERWISE SPECIFIED Output Offset Voltage, VOS Measured between SPK+ and SPK-, Inputs AC coupled to ground (0.1µF) 25 - 38 - mV Full - 49 - mV FRIPPLE = 217Hz 25 - 49 - dB FRIPPLE = 1kHz 25 - 47 - dB Power Supply Rejection Ratio, PSRR VRIPPLE = 200mVP-P, HD = VINL, RL = 8Ω, Ιnputs AC coupled to ground (0.1µF) Output Power, POUT RL = 8Ω, THD+N = 1%, f = 1kHz 25 - 941 - mW RL = 8Ω, THD+N = 10%, f = 1kHz 25 - 1.23 - W Total Harmonic Distortion + Noise, THD + N RL = 8Ω, POUT = 800mW, f = 1kHz 25 - 0.4 - % RL = 8Ω, POUT = 800mW, f = 20Hz to 20kHz 25 - 0.7 - % Max Output Voltage Swing, VOUT RL = 8Ω, VSIGNAL = 5VP-P, f = 1kHz 25 7.2 7.7 - VP-P Signal to Noise Ratio, SNR RL = 8Ω, POUT = 900mW, f = 1kHz 25 - 85 - dB Output Noise, NOUT A - Weight filter, BW = 22Hz to 22kHz 25 - 140 - µVRMS 4 FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 Electrical Specifications - 5V Supply PARAMETER Test Conditions: VDD = +5V, GND = 0V, VINH = 2.4V, VINL = 0.8V, SD = MIX = INS = HD = VINL, CREF = 1µF, RL is terminated between SPK+ and SPK- for BTL driver and between Hp_ and GND for SE drivers, Unless Otherwise Specified (Note 3). (Continued) TEST CONDITIONS TEMP (°C) MIN (Notes 4, 5) TYP MAX (Notes 4, 5) UNITS Crosstalk RCH to LCH, LCH to RCH RL = 8Ω, POUT = 800mW, f = 1kHz, Signal coupled from the input of active amplifier to the output of an adjacent amplifier with its input AC coupled to ground. 25 - 80 - dB Off-Isolation SD = VDD, POUT = 800mW, f = 10kHz, Signal coupled from input to output of a disabled amplifier. 25 - 130 - dB SINGLE ENDED AMPLIFIER DRIVERS, HD = VINH, HO = VINL, UNLESS OTHERWISE SPECIFIED FRIPPLE = 217Hz 25 - 48 - dB FRIPPLE = 1kHz 25 - 47 - dB RL = 16Ω, THD+N = 1%, f = 1kHz 25 - 170 - mW RL = 32Ω, THD+N = 1%, f = 1kHz 25 - 94 - mW RL = 16Ω, THD+N = 10%, f = 1kHz 25 - 215 - mW RL = 32Ω, THD+N = 10%, f = 1kHz 25 - 116 - mW RL = 32Ω, POUT = 15mW, f = 1kHz 25 - 0.07 - % RL = 32Ω, POUT = 15mW, f = 20Hz to 20kHz 25 - 0.09 - % RL = 32Ω, POUT = 50mW, f = 1kHz 25 - 0.3 - % Power Supply Rejection Ratio, PSRR VRIPPLE = 200mVP-P, HD = 0V, RL = 32Ω, Input AC coupled to ground (0.1µF) Output Power, POUT Total Harmonic Distortion + Noise, THD + N RL = 32Ω, POUT = 50mW, f = 20Hz to 20kHz 25 - 0.4 - % Max Output Voltage Swing, VOUT RL = 32Ω, VSIGNAL = 5VP-P, f = 1kHz 25 3.6 4.7 - VP-P Crosstalk RCH to LCH, LCH to RCH RL = 32Ω, POUT = 15mW, f = 1kHz 25 - 75 - dB Off-Isolation SD = VDD, RL = 32Ω, POUT = 15mW, f = 10kHz 25 - 120 - dB Signal to Noise Ratio, SNR RL = 32Ω, POUT = 50mW, f = 1kHz 25 - 85 - dB Channel Gain Matching RCH to LCH RL = 32Ω, VINxR = VINxL = 1.3VRMS (Connect to the same source) 25 - ±0.2 - dB Channel Phase Matching RCH to LCH RL = 32Ω, VINxR = VINxL = 1.3VRMS (Connect to the same source) 25 - 1.3 - ° Input Leakage Current, ISD, IINS, IMIX, IHD, IHO VDD = 5V, SD = 0V, INS = 0V, MIX = 0V, HD = 0V, HO = 0V 25 -3 1.9 3 µA Full - 1.9 - µA Input Leakage Current, ISD, IINS, IMIX, IHD, IHO VDD = 5V, SD = VDD, INS = VDD, MIX = VDD, HD = VDD, HO = VDD 25 -1 0.02 1 µA Full - 0.02 - µA VINH Full 2.4 - - V VINL Full - - 0.8 V LOGIC INPUT 5 FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 Electrical Specifications - 3.6V Supply Test Conditions: VDD = +3.6V, GND = 0V, VINH = 1.4V. VINL = 0.4V, SD = MIX = INS = GSO = GS1 = VINL, CREF = 1µF, RL is terminated between SPK+ and SPK- for BTL driver and between Hp_ and GND for SE drivers, Unless Otherwise Specified (Note 3). PARAMETER TEST CONDITIONS TEMP (°C) MIN (Notes 4, 5) TYP MAX (Notes 4, 5) UNITS 25 - 2.7 12 mA Full - 3 - mA 25 - 13 50 µA Full - 15 - µΑ 25 - 25 - mV Full - 40 - mV GENERAL HO = VINL or VINH, HD = VINL, INS = VINL or VINH, MIX = VINL or VINH, RL = None, Input AC coupled to ground (0.1µF) Quiescent Supply Current, IDD Shutdown Supply Current, ISD SD = VDD, HO = VINL or VINH, HD = Float, INS = VINL or VINH, MIX = VINL or VINH, RL = 8Ω (BTL) and RL = 32Ω (SE), Input AC coupled to ground (0.1µF) BTL AMPLIFIER DRIVER, HD = VINH, HO = VINH, UNLESS OTHERWISE SPECIFIED Measured between SPK+ and SPK-, Input AC coupled to ground (0.1µF) Output Offset Voltage, VOS Power Supply Rejection Ratio, PSRR VRIPPLE = 200mVP-P, HD = 0V, FRIPPLE = 217Hz RL = 8Ω, input AC coupled to FRIPPLE = 1kHz ground (0.1µF) Output Power, POUT 25 - 49 - dB 25 - 47 - dB RL = 8Ω, THD+N = 1%, f = 1kHz 25 - 310 - mW RL = 8Ω, THD+N = 10%, f = 1kHz 25 - 528 - mW Total Harmonic Distortion + Noise, THD + N RL = 8Ω, POUT = 200mW, f = 1kHz 25 - 0.4 - % RL = 8Ω, POUT = 200mW, f = 20Hz to 20kHz 25 - 0.4 - % Max Output Voltage Swing, VOUT RL = 8Ω, VSIGNAL = 3.6VP-P, f = 1kHz 25 - 5.8 - VP-P 25 - 48 - dB 25 - 47 - dB SINGLE ENDED AMPLIFIER DRIVERS, HD = VINH, HO = VINL, UNLESS OTHERWISE SPECIFIED VRIPPLE = 200mVP-P, HD = 0V, FRIPPLE = 217Hz RL = 32Ω, Ιnput AC coupled to FRIPPLE = 1kHz ground (0.1µF) Power Supply Rejection Ratio, PSRR RL = 16Ω, THD+N = 1%, f = 1kHz 25 - 80 - mW RL = 32Ω, THD+N = 1%, f = 1kHz 25 - 47 - mW RL = 16Ω, THD+N = 10%, f = 1kHz 25 - 107 - mW RL = 32Ω, THD+N = 10%, f = 1kHz 25 - 58 - mW Total Harmonic Distortion + Noise, THD + N RL = 32Ω, POUT = 15mW, f = 1kHz 25 - 0.15 - % RL = 32Ω, POUT = 15mW, f = 20Hz to 20kHz 25 - 0.15 - % Max Output Voltage Swing, VOUT RL = 32Ω, VSIGNAL = 3.6VP-P, f = 1kHz 25 - 3.2 - VP-P Output Power, POUT LOGIC INPUT Input Leakage Current, ISD, IINS, IMIX, IHD, IHO VDD = 3.6V, SD = 0V, INS = 0V, MIX = 0V, HD = 0V, HO = 0V Input Leakage Current, ISD, IINS, IMIX, IHD, IHO VDD = 3.6V, SD = VDD, INS = VDD, MIX = VDD, HD = VDD, HO = VDD 25 - 1.9 - µA Full - 1.9 - µA 25 - 0.02 - µA Full - 0.02 - µA VINH Full 1.4 - - V VINL Full - - 0.4 V NOTES: 3. VIN = input voltage to perform proper function. 4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. 6 FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 ISL54003 Typical Application Circuit and Block Diagram 0.1µF VDD SPK+ 0.22µF RIGHT AUDIO BTL INR SPK100kΩ 0.22µF LEFT AUDIO ROUTER/ MIXER INL SE HpR HD SE HpL HEADPHONE JACK 10kΩ VDD CLICK AND POP THERMAL PROTECTION BIAS REF SD MICRO CONTROLLER HO CREF 1µF LOGIC CONTROL GND ISL54005 Typical Application Circuit and Block Diagram 0.1µF 0.22µF RIGHT 1 AUDIO VDD IN1R SPK+ BTL 0.22µF RIGHT 2 AUDIO 0.22µF IN2R SPKMUX/ ROUTER/ MIXER IN1L 100kΩ SE LEFT 1 AUDIO HpR HD 0.22µF LEFT 2 AUDIO IN2L SE HpL HEADPHONE JACK 10kΩ VDD CLICK AND POP THERMAL PROTECTION BIAS REF SD MICRO CONTROLLER INS CREF 1µF LOGIC CONTROL HO GND 7 FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 ISL54006 Typical Application Circuit and Block Diagram 0.1µF 0.22µF RIGHT 1 AUDIO VDD IN1R SPK+ BTL 0.22µF IN2R SPK- RIGHT 2 AUDIO 0.22µF 100kΩ MUX/ ROUTER/ MIXER IN1L SE LEFT 1 AUDIO HpR HD 0.22µF IN2L SE LEFT 2 AUDIO HpL HEADPHONE JACK 10kΩ VDD CLICK AND POP THERMAL PROTECTION BIAS REF CREF SD 1µF INS MICRO CONTROLLER MIX LOGIC CONTROL HO GND Detailed Description The Intersil ISL54003, ISL54005, and ISL54006 family of devices are integrated audio power amplifier systems designed to provide quality audio, while requiring minimal external components. The low 0.4% THD+N ensures clean, low distortion amplification of the audio signals. The devices are designed to operate from a single +2.7V to +5V power supply. All devices are offered in a 20 Ld 4x4 TQFN package. Targeted applications include battery powered equipment such as cell-phones, MP3 players, and games/toys. These parts contain one class AB BTL type power amplifier for driving an 8Ω mono speaker and two class AB single-ended (SE) type amplifiers for driving 16Ω or 32Ω headphones. The BTL when using a 5V supply is capable of delivering 800mW (typ) with 0.4% THD+N and 941mW (typ) with 1% THD+N of continuous average power into an 8Ω BTL speaker load. When the speaker load is connected across the positive and negative terminals of the BTL driver the voltage is doubled across the load and the power is quadrupled. Each SE amplifier when using a 5V supply is capable of delivering 15mW (typ) with 0.07% THD+N and 50mW (typ) with 0.3% THD+N of continuous average power into a 32Ω headphone speaker. 8 When in Mono Mode (BTL driver active) these devices automatically mix the active left and right audio inputs and send the combined signal to the BTL driver. In Headphone Mode the active right channel input is sent to the right headphone speaker and the active left channel is sent to the left headphone speaker. The ISL54005 and ISL54006 feature a 2:1 stereo input multiplexer front-end. This allows selection between two stereo sources. The INS control pin determines which stereo input is active. Applying logic “0” to the INS control pin selects stereo input 1 (R1 and L1). Applying logic “1” to the INS control pin selects stereo input 2 (R2 and L2). The ISL54006 has the capablity of mixing the two stereo inputs. When in MIX Mode and HEADPHONE Mode, the part mixes the R1 input with the R2 input and sends the combined signal to the HpR headphone driver and it mixes the L1 input with the L2 input and sends the combined signal to the HpL headphone driver. When in MIX Mode and MONO Mode, it mixes all four inputs (R1 + R2 + L1 + L2) and sends the combined signal to the BTL mono driver. These parts have headphone sense input circuitry that detects when a headphone jack has been inserted and automatically switches the active audio inputs from the mono BTL output driver to the headphone drivers. These parts also feature a logic control pin (HO) that can override the sense input circuitry. FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 All devices in this family feature low power shutdown, thermal overload protection and click/pop suppression. The click and pop circuitry prohibits switching between input channels until the audio input signals are at there lowest point which eliminates audible transients in the speakers when changing the audio input sources. The click/pop circuitry also keeps speaker transients to an inaudibile level when entering and leaving shutdown. “Typical Application Circuits and Block Diagrams” for each device in the family are provided on page 7 and page 8. Truth tables for each device are provided on page 3. DC Bias Voltage The ISL54003, ISL54005, and ISL54006 have internal DC bias circuitry, which DC offsets the incoming audio signal at VDD/2. When using a 5V supply, the DC offset will be 2.5V. When using a 3.6V supply, the DC offset will be 1.8V. Since the signal gets biased internally at VDD/2 the audio signals need to be AC coupled to the inputs of the device. The value of the AC coupling capacitor depends on the low frequency range required for the application. A capacitor of 0.22µF will pass a signal as low as 7.2Hz. The formula required to calculated the capacitor value is shown in Equation 1: C ≥ 1 ⁄ 6.28 • f • 100kΩ Headphone (Single-Ended) Amplifiers The ISL54003, ISL54005, and ISL54006 contains two single-ended (SE) headphone amplifiers for driving the left and right channels of a 32Ω or 16Ω headphone speaker. One SE amplifier drives the right speaker of the headphone and other SE amplifier drives the left speaker of the headphone. The speaker load gets connected between the output of the amplifier and ground. The audio signal at the output of each SE driver is biased at VDD/2 and unlike the BTL driver that cancels this offset due to its differential connection, a capacitor is required at the output of each SE drivers to remove this DC voltage from the headphone load. This coupling capacitor along with the resistance of the speaker load creates a high pass filter that sets the amplifier’s lower bandpass frequency limit. The value of this AC coupling capacitor depends on the low frequency range required by the application. The formula required to calculate the capacitor value is shown in Equation 2: C ≥ 1 ⁄ 6.28 • f • Rspeaker (EQ. 2) For an application driving a 32Ω headphone with a lower frequency requirement of 150Hz, the required capacitor value would be determined by using Equation 3: (EQ. 1) C ≥ 1 ⁄ 6.28 • 150 • 32 = 33μF (EQ. 3) The 100kΩ is the impedance looking into the input of the ISL54003, ISL54004, ISL54006 devices. Use the closest standard value. BTL Speaker Amplifier Headphone Sense Function The ISL54003, ISL54005, and ISL54006 contain one bridge-tied load (BTL) amplifier designed to drive an 8Ω speaker load differentially. The output to the BTL amplifier are SPK+ and SPK-. The speaker load gets connected across these terminals. With a logic “1” at the HP control pin while the HO control pin is low will activate the headphone drivers and disable the BTL driver. A single BTL driver consists of an inverting and non-inverting power op amps. The AC signal out of each op amp are equal in magnitude but 180° out-of-phase, so the AC signal at SPK+ and SPK- have the same amplitude but are 180° out-of-phase. Driving the load differentially using a BTL configuration doubles the output voltage across the speaker load and quadruples the power to the load. In effect you get a gain of two due to this configuration at the load as compared to driving the load with a single-ended amplifier with its load connected between a single amplifier’s output and ground. The outputs of the BTL are biased at VDD/2. When the load gets connected across the + and - terminal of the BTL the mid supply DC bias voltage at each output gets cancelled out eliminating the need for large bulky output coupling capacitors. 9 The “Typical Application Circuits and Block Diagrams” on page 7 and page 8 show the implementation of the headphone control function using a common headphone jack. The HP pin gets connected to the mechanical wiper blade of the headphone jack. Two external resistors are required for proper operation. A 100kΩ pull-up resistor from the HP pin to VDD and a 10kΩ pull-down resistor from the jack’s audio signal pin to ground of the jack signal pin to which the wiper is connected. See the block diagrams on page 7 and page 8. When no headphone plug is inserted into the jack, the voltage at the HP pin gets set at a low voltage level due to the 10kΩ resistor and 100kΩ resistor divider network connection to VDD. When a headphone is inserted into the jack, the 10kΩ resistor gets disconnected from the HP control pin and the HP pin gets pulled up to VDD. Since the HP pin is now high, the headphone drivers are activated. FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 A microprocessor or a switch can be used to drive the HP pin rather than using the headphone jack contact pin. Note: With a logic “1” at the HO pin, the BTL driver remains active regardless of the voltage level at the HD pin. This allows a headphone to be plugged into the headphone jack without activating the HP drivers. Music will continue to play through the internal 8Ω speaker rather than the headphones. Low Power Shutdown With a logic “1” at the SD control pin the device enters the low power shutdown state. When in shutdown the BTL and headphone amplifiers go into an high impedance state and IDD supply current is reduced to 26µA (typ). In shutdown mode before the amplifiers enter the high impedance/low current drive state, the bias voltage of VDD/2 remains connected at the output of the amplifiers through a 100kΩ resistor. This resistor is not present during active operation of the drivers but gets switched in when the SD pin goes high. It gets removed when the SD pin goes low. Leaving the DC bias voltage connected through a 100kΩ resistor while going into and out of shutdown reduces the transient at the speakers to a small level preventing clicking or popping in the speakers. Note: When the SD pin is High it over-rides all other logic pins. QFN Thermal Pad Considerations The QFN package features an exposed thermal pad on its underside. This pad lowers the package’s thermal resistance by providing a direct heat conduction path from the die to the PCB. Connect the exposed thermal pad to GND by using a large copper pad and multiple vias to the GND plane. The vias should be plugged and tented with plating and solder mask to ensure good thermal conductivity. Best thermal performance is achieved with the largest practical copper ground plane area. PCB Layout Considersations and Power Supply Bypassing To maintain the highest load dissipation and widest output voltage swing, the power supply PCB traces and the traces that connect the output of the drivers to the speaker loads should be made as wide as possible to minimize losses due to parasitic trace resistance. Proper supply bypassing is necessary for high power supply rejection and low noise performance. A filter network consisting of a 10µF capacitor in parallel with a 0.1µF capacitor is recommended at the voltage regulator that is providing the power to the ISL54003, ISL54004, ISL54006 IC. Local bypass capacitors of 0.1µF should be put at each VDD pin of the ISL54003, ISL54004, ISL54006 devices. They should be located as close as possible to the pin, keeping the length of leads and traces as short as possible. A 1µF capacitor from the REF pin (pin 10) to ground is needed for optimum PSRR and internal bias voltage stability. Typical Performance Curves 1.0 0.9 0.8 0.7 0.6 TA = +25°C, Unless Otherwise Specified. 1.0 0.9 0.8 0.7 VDD = 5V BTL RL = 8Ω PO = 800mW 0.6 0.5 THD+N (%) THD+N (%) 0.5 0.4 0.3 0.2 0.1 20 VDD = 3.6V BTL RL = 8Ω PO = 200mW 0.4 0.3 0.2 0.1 50 100 200 500 1k 2k FREQUENCY (Hz) FIGURE 1. THD+N vs FREQUENCY 10 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FIGURE 2. THD+N vs FREQUENCY FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued) 10.0 10.0 VDD = 5V BTL RL = 8Ω f = 1kHz 5.00 2.00 2.00 1.00 THD+N (%) 1.00 THD+N (%) VDD = 3.6V BTL RL = 8Ω f = 1kHz 5.00 0.50 0.20 0.50 0.20 0.10 0.10 0.05 0.05 0.02 0.02 0.01 10m 20m 50m 100m 200m 500m 0.01 10m 600m 20m 40m 70m 100m 200m OUTPUT POWER (W) OUTPUT POWER (W) FIGURE 3. THD+N vs OUTPUT POWER FIGURE 4. THD+N vs OUTPUT POWER 0.20 0.40 VDD = 5V SE RL = 32Ω 0.20 PO = 15mW 0.10 0.09 0.08 0.07 0.06 VDD = 3.6V SE RL = 32Ω 0.30 PO = 15mW 0.10 THD+N (%) THD+N (%) 600m 0.05 0.04 0.03 0.05 0.04 0.03 0.02 0.02 0.01 20 50 100 200 500 1k 2k 5k 0.01 10k 20k 20 50 100 200 FIGURE 5. THD+N vs FREQUENCY 1.0 0.9 0.8 0.7 0.6 1k 2k 5k 10k 20k FIGURE 6. THD+N vs FREQUENCY 1.0 0.9 0.8 0.7 0.6 VDD = 5V SE RL = 32Ω PO = 50mW 0.5 THD+N (%) 0.5 THD+N (%) 500 FREQUENCY (Hz) FREQUENCY (Hz) 0.4 0.3 VDD = 5V SE RL = 16Ω PO = 50mW 0.4 0.3 0.2 0.2 0.1 0.1 20 50 100 200 500 1k 2k FREQUENCY (Hz) 5k FIGURE 7. THD+N vs FREQUENCY 11 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FIGURE 8. THD+N vs FREQUENCY FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued) 1.00 1.00 VDD = 3.6V SE RL = 32Ω 0.50 VDD = 3.6V SE RL = 16Ω 0.50 PO = 60mW 0.20 THD+N (%) THD+N (%) PO = 30mW 0.10 0.20 0.10 0.05 0.05 0.02 0.02 0.01 20 50 100 200 500 1k 2k FREQUENCY (Hz) 5k 0.01 10k 20k 20 50 500 1k 2k 5k 10k 20k FIGURE 10. THD+N vs FREQUENCY 0.20 0.10 0.09 0.08 0.07 0.06 VDD = 5V SE RL = 32Ω f = 1kHz 0.05 THD+N (%) THD+N (%) 200 FREQUENCY (Hz) FIGURE 9. THD+N vs FREQUENCY 0.10 0.09 0.08 0.07 0.06 0.05 100 0.04 0.03 VDD = 5V SE RL = 16Ω f = 1kHz 0.04 0.03 0.02 0.02 0.01 2 3 4 5 6 7 8 9 10 OUTPUT POWER (mW) 0.01 20 0.30 4 5 6 7 8 9 10 OUTPUT POWER (mW) 20 0.10 0.09 0.08 VDD = 3.6V SE RL = 32Ω 0.07 f = 1kHz 0.06 VDD = 3.6V SE RL = 16W 0.05 0.10 0.09 0.08 0.07 0.06 0.05 THD+N (%) THD+N (%) 3 FIGURE 12. THD+N vs OUTPUT POWER FIGURE 11. THD+N vs OUTPUT POWER 0.20 2 0.04 0.03 0.04 f = 1kHz 0.03 0.02 0.02 0.01 2 3 4 5 6 7 8 9 10 OUTPUT POWER (mW) FIGURE 13. THD+N vs OUTPUT POWER 12 20 0.01 2 3 4 5 6 7 8 9 10 OUTPUT POWER (mW) 20 FIGURE 14. THD+N vs OUTPUT POWER FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued) 10.0 10.0 VDD = 5V SE RL = 32Ω 5.00 2.00 5.00 2.00 VDD = 5V SE RL = 16Ω 1.00 f = 1kHz f = 1kHz THD+N (%) THD+N (%) 1.00 0.50 0.20 0.50 0.20 0.10 0.10 0.05 0.05 0.02 0.02 0.01 10m 20m 30m 40m 50m 70m 0.01 10m 100m 20m OUTPUT POWER (W) FIGURE 15. THD+N vs OUTPUT POWER 200m 10.0 5.00 VDD = 3.6V SE RL = 16Ω 5.00 VDD = 3.6V SE RL = 32Ω 2.00 2.00 f = 1kHz f = 1kHz 1.00 1.00 THD+N (%) THD+N (%) 50m 70m 100m FIGURE 16. THD+N vs OUTPUT POWER 1.00 0.50 0.20 0.50 0.20 0.10 0.01 0.05 0.05 0.02 0.02 0.01 10m 12m 15m 20m 25m 35m 45m 0.01 10m 55m 20m OUTPUT POWER (W) VDD = 5V PO = 15mW -60 -65 OFF ISOLATION (dB) INxR TO HPL -70 -75 INxL TO HPR -80 -85 -90 -95 -100 -105 -110 20 50 100 200 500 1k 2k 5k FREQUENCY (Hz) FIGURE 19. CROSSTALK vs FREQUENCY 13 40m 50m 70m 100m FIGURE 18. THD+N vs OUTPUT POWER -50 -55 30m OUTPUT POWER (W) FIGURE 17. THD+N vs OUTPUT POWER CROSSTALK (dB) 30m OUTPUT POWER (W) 10k 20k -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 -155 -160 HPR AND HPL BTL 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) FIGURE 20. OFF ISOLATION vs FREQUENCY FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued) -20 -22 -26 -25 BTL VRIPPLE = 200mVP-P -30 VDD = 5V SE VRIPPLE = 200mVP-P -35 -34 -40 -38 -45 -42 -50 PSRR (dB) PSRR (dB) -30 VDD = 5V -46 -50 HPR -55 -60 -65 -54 HPL -70 -58 -75 -62 -80 -66 -85 -70 -90 10 20 50 100 200 500 1k 2k 5k 10k 20k 10 20 50 400 600 350 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 700 500 400 300 200 VDD = 5V BTL RL = 8W 100 250 500 POUT (mW) 1k 2k 5k 10k 20k 300 250 200 150 100 VDD = 3.6V 750 BTL RL = 8W 50 0 0 500 FIGURE 22. PSRR vs FREQUENCY FIGURE 21. PSRR vs FREQUENCY 0 100 200 FREQUENCY (Hz) FREQUENCY (Hz) 1000 FIGURE 23. POWER DISSIPATION vs OUTPUT POWER 0 100 200 300 400 500 POUT (mW) FIGURE 24. POWER DISSIPATION vs OUTPUT POWER Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND PROCESS: Submicron CMOS 14 FN6514.2 October 30, 2007 ISL54003, ISL54005, ISL54006 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead FramePlastic Package (TMLFP) L20.4x4A 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WGGD-1 ISSUE I) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - 0.02 0.05 - A2 - 0.55 0.80 9 A3 b 0.20 REF 0.18 D 0.30 5, 8 4.00 BSC D1 D2 0.25 9 - 3.75 BSC 1.95 2.10 9 2.25 7, 8 E 4.00 BSC - E1 3.75 BSC 9 E2 1.95 e 2.10 2.25 7, 8 0.50 BSC - k 0.20 - - - L 0.35 0.60 0.75 8 N 20 2 Nd 5 3 Ne 5 3 P - - 0.60 θ - - 12 9 9 Rev. 0 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN6514.2 October 30, 2007