Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 LM5066 10 to 80 V, Hotswap Controller With I/V/P Monitoring and PMBus™ Interface 1 Features 3 Description • • • • • • • • • • LM5066 provides robust protection and precision monitoring for 10- to 80-V systems. Programmable UV, OV, ILIMIT, and fast-short circuit protection allow for customized protection for any application. Programmable FET SOA protection sets the maximum power the FET is allowed to dissipate under any condition. The programmable fault timer (tFAULT) is set to avoid nuisance trips, ensure start-up, and limit the duration of over load events. 1 • • • • 10- to 80-V Operation 100-V Continuous Absolute Max 26 mV (±12%) or 50 mV (±6%) ILIM Threshold Programmable FET SOA Protection Programable UV, OV, tFAULT Thresholds External FET Temperature Sensing Failed FET Detection I2C / SMBus Interface PMBus™ Compliant Command Structure Precision V IN, VOUT, IIN, PIN, VAUX Monitoring – V (±2.7%); I (±3%); P (±4.5%) Programable I/V/P Averaging Interval 12-bit ADC with 1-kHz Sampling Rate –40°C < TJ < 125°C Operation Pin-to-Pin Compatible with LM5066I In addition to circuit protection, the LM5066 supplies real-time power, voltage, current, temperature, and fault data to the system management host through the I2C / SMBus interface. PMBus compliant command structure makes it easy to program the device. Precision telemetry enables intelligent power management functions such as efficiency optimization and early fault detection. LM5066 also supports advanced features such as I/V/P averaging and peak power measurment to improve system diagnostics. 2 Applications • • • • • LM5066I is pin-to-pin compatible with the LM5066 and offers improved telemetry accuracy and supports the Read_Ein command to monitor energy. See Table 1 for a detailed comparison. 48-V Servers Base Station Power Distribution Networking Routers and Switchers PLC Power Management 24- to 28-V Industrial Systems Device Information(1) PART NUMBER LM5066 PACKAGE BODY SIZE (NOM) 9.70 × 4.40 mm2 PWP (28) (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACE Simplified Schematic VOUT RSNS D1 Z1 R1 Q1 R3 SENSE VIN_K VIN GATE OUT DIODE FB SMBus Interface R4 AGND GND LM5066 PGD ADR2 ADR1 ADR0 CL SMBA RETRY SDAO VAUX SDAI SCL VDD VREF PWR TIMER 1 PF R5 VDD R6 UVLO/EN OVLO R2 48-V Bus 1 PF RPWR COUT Card to Card Communication CIN LM5066 in a Plug-in Card Q2 VIN PMBus Hotswap Manages Inrush, Faults, and Monitoring 48 V 12 V DC/DC Load 1 Load 2 I/V/P info via PMBus Regulate Loads to Micro Controller Optimize Efficiency Plug-in Card CTIMER 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 5 7.1 7.2 7.3 7.4 7.5 7.6 Absolute Maximum Ratings ..................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 SMBus Communications Timing Requirements and Definitions ................................................................ 10 7.7 Switching Characteristics ........................................ 11 7.8 Typical Performance Characteristics ...................... 12 8 Detailed Description ............................................ 16 8.1 8.2 8.3 8.4 8.5 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... 16 17 17 20 23 Application and Implementation ........................ 43 9.1 Application Information............................................ 43 9.2 Typical Application ................................................. 43 10 Power Supply Recommendations ..................... 54 11 Layout................................................................... 55 11.1 Layout Guidelines ................................................. 55 11.2 Layout Example .................................................... 55 12 Device and Documentation Support ................. 57 12.1 Trademarks ........................................................... 57 12.2 Electrostatic Discharge Caution ............................ 57 12.3 Glossary ................................................................ 57 13 Mechanical, Packaging, and Orderable Information ........................................................... 57 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (July 2014) to Revision I • Page Changed VGATEZ MIN value in Electrical Characteristics From: 15 V To: 12 V ..................................................................... 7 Changes from Revision G (February 2013) to Revision H Page • Updated data sheet to new TI standards: added new sections and reordered document flow ............................................ 1 • Added link to LM5066 design calculator .............................................................................................................................. 43 Changes from Revision F (February 2013) to Revision G • Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Changes from Revision A (May 2014) to Revision B • 2 Page Page Changed title of Handling Ratings table to ESD Ratings table ............................................................................................. 5 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 5 Device Comparison Table Table 1 summarizes the differences between the LM5066 and the LM5066I. Note that the current monitoring accuracy of the LM5066I is much better at the ILIM = 26 mV setting, but is comparable at the 50-mV setting. For many applications with lower power, using the LM5066 at the 50-mV setting is a great option. However, for higher power applications upgrading to LM5066I and using the ILIM = 26 mV setting will lead to significant power savings (approximately 24 mV × ILOAD). In addition, the higher accuracy and energy monitoring capability can enable further improvements in system efficiency, which is critical in high power applications. Table 1. LM5066 vs LM5066I KEY PARAMETERS LM5066 LM5066I Voltage monitoring ±2.7% ±1.25% Current monitoring (ILIM = 26 mV) ±4.25% ±1.75% Power monitoring (ILIM = 26 mV) ±4.5% ±.2.5% Current monitoring (ILIM = 50 mV) ±3% ±3.5% Power monitoring (ILIM = 50 mV) ±4.5% ±4.5% No Yes Supports Energy Monitoring via Read_EIN command 6 Pin Configuration and Functions PWP Package 28-Pin Top View OUT 1 28 PGD GATE 2 27 NC SENSE 3 26 PWR VIN_K 4 25 TIMER VIN 5 24 RETRY NC 6 23 FB UVLO/EN 7 22 CL OVLO 8 21 VDD AGND 9 20 ADR0 GND 10 19 ADR1 SDAI 11 18 ADR2 SDAO 12 17 VAUX SCL 13 16 DIODE SMBA 14 15 VREF Solder exposed pad to ground. Pin Functions PIN NAME NO. Exposed Pad Pad DESCRIPTION Exposed pad of TSSOP package Solder to the ground plane to reduce thermal resistance OUT 1 Output feedback Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for power limiting and to monitor the output voltage. GATE 2 Gate drive output Connect to the external MOSFET's gate. SENSE 3 Current sense input The voltage across the current sense resistor (RSNS) is measured from VIN_K to this pin. If the voltage across RSNS reaches overcurrent threshold the load current is limited and the fault timer activates. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 3 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Pin Functions (continued) PIN NAME DESCRIPTION NO. VIN_K 4 Positive supply Kelvin pin The input voltage is measured on this pin. VIN 5 Positive supply input This pin is the input supply connection for the device. N/C 6 No connection UVLO/EN 7 Undervoltage lockout An external resistor divider from the system input voltage sets the undervoltage turn-on threshold. An internal 20-µA current source provides hysteresis. The enable threshold at the pin is nominally 2.48 V. This pin can also be used for remote shutdown control. OVLO 8 Overvoltage lockout An external resistor divider from the system input voltage sets the overvoltage turn-off threshold. An internal 21-µA current source provides hysteresis. The disable threshold at the pin is 2.46 V. AGND 9 Circuit ground Analog device ground. Connect to GND at the pin. GND 10 Circuit ground SDAI 11 SMBus data input pin Data input pin for SMBus. Connect to SDAO if the application does not require unidirectional isolation devices. SDAO 12 SMBus data output pin Data output pin for SMBus. Connect to SDAI if the application does not require unidirectional isolation devices. SCL 13 SMBus clock Clock pin for SMBus SMBA 14 SMBus alert line Alert pin for SMBus, active low VREF 15 Internal reference Internally generated precision reference used for analog-to-digital conversion. Connect a 1-µF capacitor on this pin to ground for bypassing. DIODE 16 External diode Connect this to a diode-configured MMBT3904 NPN transistor for temperature monitoring. VAUX 17 Auxiliary voltage input Auxiliary pin allows voltage telemetry from an external source. Full-scale input of 2.97 V. ADR2 18 SMBUS address line 2 Tri-state address line. Should be connected to GND, VDD, or left floating. ADR1 19 SMBUS address line 1 Tri-state address line. Should be connected to GND, VDD, or left floating. ADR0 20 SMBUS address line 0 Tri-state address line. Should be connected to GND, VDD, or left floating. VDD 21 Internal sub-regulator output Internally sub-regulated 4.85-V bias supply. Connect a 1-µF capacitor on this pin to ground for bypassing. CL 22 Current limit range Connect this pin to GND or leave floating to set the nominal over-current threshold at 50 mV. Connecting CL to VDD sets the overcurrent threshold to be 26 mV. FB 23 Power Good feedback An external resistor divider from the output sets the output voltage at which the PGD pin switches. The threshold at the pin is nominally 2.46 V. An internal 20-µA current source provides hysteresis. RETRY 24 Fault retry input This pin configures the power up fault retry behavior. When this pin is connected to GND or left floating, the device will continually try to engage power during a fault. If the pin is connected to VDD, the device will latch off during a fault. TIMER 25 Timing capacitor An external capacitor connected to this pin sets insertion time delay, fault timeout period, and restart timing. PWR 26 Power limit set An external resistor connected to this pin, in conjunction with the current sense resistor (RSNS), sets the maximum power dissipation allowed in the external series pass MOSFET. N/C 27 No connection 4 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Pin Functions (continued) PIN NAME PGD DESCRIPTION NO. 28 Power Good indicator An open-drain output. This output is high when the voltage at the FB pin is above VFBTH (nominally 2.46 V) and the input supply is within its undervoltage and overvoltage thresholds. Connect to the output rail (external MOSFET source) or any other voltage to be monitored. 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature (unless otherwise noted) Input voltage MIN MAX VIN, VIN_K, GATE, UVLO/EN, SENSE, PGD to GND –0.3 100 OVLO, FB, TIMER, PWR to GND –0.3 7 OUT to GND –0.3 100 –1 100 OUT to GND (1-ms transient) SCL, SDAI, SDAO, CL, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND –0.3 6 SENSE to VIN_K, VIN to VIN_K, AGND to GND –0.3 0.3 Junction temperature Storage temperature, Tstg (1) –65 UNIT V 150 °C 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VESD (1) (2) (3) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins except GATE (2) Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3) VALUE UNIT ± 2000 V ±500 V The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 2-kV rating for all pins except GATE which is rated for 1 kV. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN, SENSE, OUT voltage Junction temperature NOM MAX UNIT 10 80 V –40 125 °C Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 5 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 7.4 Thermal Information LM5066 THERMAL METRIC (1) PWP UNIT 28 PINS Junction-to-ambient thermal resistance (2) RθJA 35.6 (3) RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance (4) 16.8 ψJT Junction-to-top characterization parameter (5) 0.5 ψJB Junction-to-board characterization parameter (6) 16.7 RθJC(bot) Junction-to-case (bottom) thermal resistance (7) 2.9 (1) (2) (3) (4) (5) (6) (7) 6 19.9 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 7.5 Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C unless otherwise stated. Minimum and maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 48 V. See (1) and (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT (VIN PIN) IIN-EN Input current, enabled VUVLO = 3 V and VOVLO = 2 V 7.2 9.5 mA PORIT Power-on reset threshold at VIN to trigger insertion timer VIN increasing 7.8 9.0 V POREN Power-on reset threshold at VIN to enable all functions VIN increasing 8.6 9.9 V PORHYS POREN hysteresis VIN decreasing 120 mV VDD REGULATOR (VDD PIN) VDD IVDD = 0 mA 4.60 IVDD = 10 mA VDDILIM VDD current limit VDDPOR VDD voltage reset threshold 4.90 5.15 V 4.85 –25 VDD rising –30 V –42 mA 4.1 V UVLO/EN, OVLO PINS UVLOTH UVLO threshold VUVLO falling 2.41 2.48 2.55 V UVLOHYS UVLO hysteresis current UVLO = 1 V 13 20 26 µA UVLOBIAS UVLO bias current UVLO = 3 V 1 µA OVLOTH OVLO threshold VOVLO rising 2.39 2.46 2.53 V OVLOHYS OVLO hysteresis current OVLO = 1 V –26 –21 –13 µA OVLOBIAS OVLO bias current OVLO = 1 V 1 µA 110 mV 1 µA POWER GOOD (PGD PIN) PGDVOL Output low voltage ISINK = 2 mA PGDIOH Off leakage current VPGD = 80 V FBTH FB threshold VUVLO = 3 V and VOVLO = 2 V FBHYS FB hysteresis current FBLEAK Off leakage current 60 FB PIN 2.41 2.46 2.52 V –25 –20 –15 µA 1 µA 22.5 mV VFB = 2.3 V POWER LIMIT (PWR PIN) PWRLIM Power limit sense voltage (VIN-SENSE) SENSE-OUT = 48 V, RPWR = 121 kΩ 16.5 SENSE-OUT = 24 V, RPWR = 75 kΩ 19.5 23 mV IPWR PWR pin current VPWR = 2.5 V –20 µA RSAT(PWR) PWR pin impedance when disabled UVLO = 2 V 135 Ω GATE CONTROL (GATE PIN) IGATE Source current Normal Operation –26 Fault sink current UVLO = 2 V 3.4 POR circuit breaker sink current VIN – SENSE = 150 mV or VIN < PORIT, VGATE = 5 V 50 VGATEZ Reverse-bias voltage of GATE to OUT zener diode GATE – OUT 12 16.5 VGATECP Peak charge pump voltage in normal operation (VIN = VOUT) GATE – OUT (1) (2) –20 –10 µA 4.2 5.3 mA 115 180 mA 18 V 13.6 V Current out of a pin is indicated as a negative value. All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 7 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C unless otherwise stated. Minimum and maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 48 V. See (1) and (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUT PIN IOUT-EN OUT bias current, enabled IOUT-DIS OUT bias current, disabled OUT = VIN, Normal operation (3) Disabled, OUT = 0 V, SENSE = VIN 78 µA –50 µA CURRENT LIMIT VCL ISENSE Current limit threshold voltage (VIN – VSENSE) CL = VDD 23 26 29 CL = GND 47 50 53 SENSE input current Enabled, SENSE = OUT 25 Disabled, OUT = 0 V 66 Enabled, OUT = 0 V 220 mV µA CIRCUIT BREAKER RTCB Circuit breaker to current limit ratio: (VIN -VSENSE)CB/VCL CB/CL ratio bit = 0, ILim = 50 mV 1.64 1.94 2.23 CB/CL ratio bit = 1, ILim = 50 mV 3.28 3.87 4.45 CB/CL ratio bit = 0, ILim = 26 mV 1.88 CB/CL ratio bit = 1, ILim = 26 mV VCB Circuit breaker threshold voltage: (VIN – VSENSE) V/V 3.75 CB/CL ratio bit = 0, ILim = 50 mV 80 96 110 CB/CL ratio bit = 1, ILim = 50 mV 164 193 222 mV CB/CL ratio bit = 0, ILim = 26 mV 39 48 57 CB/CL ratio bit = 1, ILim = 26 mV 79 96 113 3.74 3.9 4.07 V 0.98 1.1 1.24 V TIMER (TIMER PIN) VTMRH Upper threshold VTMRL Lower threshold ITIMER Insertion time current DCFAULT Restart cycles End of eighth cycle 0.3 V Re-enable threshold 0.3 V –5.9 –4.8 –3.3 µA Sink current, end of insertion time TIMER pin = 2 V 1.0 1.5 2.0 mA Fault detection current –95 –75 –50 µA Fault sink current 1.7 2.5 3.2 µA Fault restart duty cycle 0.5 % INTERNAL REFERENCE VREF Reference voltage 2.93 2.97 3.02 V ADC AND MUX Resolution INL Integral non-linearity ADC only tACQUIRE Acquisition + Conversion time Any channel tRR Acquisition round robin time Cycle all channels (3) 8 12 Bits ±4 LSB 100 µs 1 ms OUT bias current (disabled) due to leakage current through an internal 1 MΩ resistance from SENSE to VOUT. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C unless otherwise stated. Minimum and maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 48 V. See (1) and (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TELEMETRY ACCURACY IINFSR IINLSB Current input full-scale range Current input LSB CL = GND 75.8 mV CL = VDD 38.2 mV CL = GND 18.5 µV CL = VDD 9.3 µV 2.97 V µV VAUXFSR VAUX input full-scale range VAUXLSB VAUX input LSB 725 VINFSR Input voltage full-scale range 89.3 V VINLSB Input voltage LSB 21.8 mV IINACC Input current accuracy VIN – SENSE = 50 mV, CL = GND –3.0 +3.0 % VIN – SENSE = 25 mV, CL = VDD -4.25 4.25 % VACC VAUX, VIN, VOUT VIN, VOUT = 48 V VAUX = 2.8V –2.7 +2.7 % PINACC Input power accuracy VIN = 48 V, VIN – SENSE = 50mV, CL = VDD –4.5 +4.5 % REMOTE DIODE TEMPERATURE SENSOR TACC Temperature accuracy using local diode TA = 25°C to 85°C 2 Remote diode resolution IDIODE External diode current source 10 9 High level 250 Low level 9.4 Diode current ratio °C bits 325 µA µA 25.9 PMBus PIN THRESHOLDS (SMBA, SDA, SCL) VIL Data, clock input low voltage VIH Data, clock input high voltage VOL Data output low voltage ISINK = 3 mA ILEAK Input leakage current SDAI, SMBA,SCL = 5 V 0.9 V 2.1 5.5 V 0 0.4 V 1 µA CONFIGURATION PIN THRESHOLDS (CL, RETRY) VIH Threshold voltage ILEAK Input leakage current 3 CL, RETRY = 5 V V 5 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 µA 9 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 7.6 SMBus Communications Timing Requirements and Definitions MIN MAX UNIT ƒSMB SMBus operating frequency PARAMETER 10 400 kHz tBUF Bus free time between stop and start condition 1.3 µs tHD:STA Hold time after (repeated) start condition. After this period, the first clock is generated. 0.6 µs tSU:STA Repeated start condition setup time 0.6 µs tSU:STO Stop condition setup time 0.6 µs tHD:DAT Data hold time 85 ns tSU:DAT Data setup time 100 tTIMEOUT Clock low time-out (1) 25 tLOW Clock low period 1.5 (2) tHIGH Clock high period tLOW:SEXT Cumulative clock low extend time (slave device) (3) tLOW:MEXT Cumulative low extend time (master device) (4) tF Clock or data fall time (5) tR (1) (2) (3) (4) (5) Clock or data rise time ns 35 µs 0.6 (5) ms µs 25 ms 10 ms 20 300 ns 20 300 ns Devices participating in a transfer will timeout when any clock low exceeds the value of tTIMEOUT,MIN of 25 ms. Devices that have detected a timeout condition must reset the communication no later than tTIMEOUT,MAX of 35 ms. The maximum value must be adhered to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms). tHIGH MAX provides a simple method for devices to detect bus idle conditions. tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a slave exceeds this time, it is expected to release both its clock and data lines and reset itself. tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack, or ack-to-stop. Rise and fall time is defined as follows: tR = ( VILMAX – 0.15) to (VIHMIN + 0.15); tF = 0.9 VDD to (VILMAX – 0.15) tR SCL tF tLOW VIH VIL tHIGH tHD;STA tHD;DAT tSU;STA tSU;STO tSU;DAT SDA VIH VIL tBUF P S S P Figure 1. SMBus Timing Diagram 10 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 7.7 Switching Characteristics Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR= 20 kΩ. PARAMETER CONDITIONS MIN TYP MAX UNIT UVLO/EN, OVLO PINS UVLODEL UVLO delay OVLODEL OVLO delay Delay to GATE high 9 Delay to GATE low 13 Delay to GATE high 13 Delay to GATE low 10 Delay to PGD high 7.6 Delay to PGD low 9.2 VIN-SENSE stepped from 0 to 80 mV; CL = GND 45 VIN-SENSE stepped from 0 to 150 mV, time to GATE low, no load 0.42 µs µs FB PIN FBDEL FB Delay µs CURRENT LIMIT tCL Response time µs CIRCUIT BREAKER tCB Response time 0.83 µs TIMER (TIMER PIN) tFAULT_DELAY Fault to GATE low delay TIMER pin reaches the upper threshold 12 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 µs 11 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 7.8 Typical Performance Characteristics Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature. 30 Sense Pin Current - Enabled (µA) 8.0 VIN Input Current (mA) 7.5 7.0 6.5 6.0 5.5 VIN =10V VIN=48V VIN=80V 5.0 ±50 0 ±25 25 50 75 100 125 29 28 27 26 25 24 23 VIN = 48V 22 150 TJ - Junction Temperature (ƒC) ±50 Figure 2. VIN Pin Current 50 75 100 150 C002 Figure 3. Sense Pin Current (Enabled) 120 90 60 VIN = 10V VIN = 48V VIN = 80V 30 0 ±20 VIN = 10V VIN=48V VIN=80V ±40 ±60 ±80 ±100 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (°C) 150 ±50 0 ±25 25 50 75 100 125 TJ - Junction Temperature (°C) C003 Figure 4. Out Pin Current (Enabled) 150 C004 Figure 5. Out Pin Current (Disabled) 17.0 Gate Pin Source Current (µA) ±18 16.8 16.6 16.4 16.2 ±19 ±19 ±20 VIN = 10V to 80V VIN = 48V 16.0 ±20 ±50 ±25 0 25 50 75 100 TJ - Junction Temperature (ƒC) 125 150 ±50 C005 Figure 6. Gate Zener Reverse Bias Voltage (VGATE – VOUT) 12 125 0 Output Pin Current - Disabled (µA) Output Pin Current - Enabled (µA) 25 TJ - Junction Temperature (ƒC) 150 Gate Pin Voltage (V) 0 ±25 C001 Submit Documentation Feedback ±25 0 25 50 75 100 TJ - Junction Temperature (ƒC) 125 150 C006 Figure 7. Gate Pin Source Current Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature. 30 VSNS at Power Limit Threshold (mV) Gate Pin Sink Current (mA) 5 5 4 4 VIN = 48V 3 20 15 10 5 VIN = 24V VIN = 48V VIN = 80V 0 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) 150 ±50 ±25 0 25 50 75 100 125 150 TJ - Junction Temperature (ƒC) C007 Figure 8. Gate Pin Sink Current C008 Figure 9. VSNS At Power Limit Threshold RPWR = 75 kΩ 20.8 UVLO Hystersis Current (µA) 2.50 UVLO Threshold (V) 25 2.48 2.46 2.44 VIN = 10V 20.7 20.6 20.5 VIN = 10V to 80V VIN = 48V , 80V 20.4 2.42 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) 150 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) C009 Figure 10. UVLO Threshold 150 C010 Figure 11. UVLO Hysteresis Current 2.48 ±23 FB Hysteresis (µA) FB Threshold (V) ±24 2.46 2.44 ±24 ±25 ±25 ±26 9,1 « 2.42 ±50 ±25 0 25 50 75 100 TJ - Junction Temperature (ƒC) 125 150 Vin = 48V ±26 ±50 C011 Figure 12. FB Threshold ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) 150 C012 Figure 13. FB Hysteresis Current Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 13 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Typical Performance Characteristics (continued) 2.48 ±18 2.47 ±20 OVLO Hystersis (µA) OVLO THRESHOLD (V) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature. 2.46 2.45 ±22 ±24 VIN = 10V to 80V Vin = 10V to 80V 2.44 ±26 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) 150 ±50 CIRCUIT BREAKER THRESHOLD (mV) CURRENT LIMIT THRESHOLD (mV) 45 40 CL = VDD CL = GND 30 25 20 ±25 0 25 50 75 25 50 75 100 125 150 C014 Figure 15. OVLO Hysteresis Current 50 ±50 0 TJ - Junction Temperature (ƒC) Figure 14. OVLO Threshold 55 35 ±25 C013 100 125 TJ - Junction Temperature (ƒC) 220 200 180 CL = VDD, CB/CL BIT = LOW 160 CL = GND, CB/CL BIT = LOW 140 CL = GND, CB/CL BIT = HIGH 120 100 80 60 40 150 ±50 ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) C015 Figure 16. Current Limit Threshold 150 C016 Figure 17. Circuit Breaker Threshold 2.965 0.5 IIN ERROR ( % of FSR) 0.4 VREF (V) 2.960 2.955 2.950 VIN = 48V 2.945 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 VIN = 48V -0.5 ±50 ±25 0 25 50 75 100 TJ - Junction Temperature (ƒC) 125 150 ±50 C017 Figure 18. Reference Voltage 14 ±25 0 25 50 75 100 125 TJ - Junction Temperature (ƒC) 150 C018 Figure 19. IIN Measurement Accuracy (VIN – Sense = 50 mV) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature. 300 1.0 Rs = 3mŸ 250 0.6 0.4 PMOSFETILIM) (W) PIN ERROR (% of FSR) 0.8 0.2 0.0 -0.2 -0.4 -0.6 Rs = 5mŸ Rs = 10mŸ 200 Rs = 20mŸ 150 100 50 -0.8 VIN = 48V 0 -1.0 ±50 ±25 0 25 50 75 100 TJ - Junction Temperature (ƒC) 125 150 0 Figure 20. Pin Measurement Accuracy (VIN – Sense = 50 mV) 25 50 75 100 125 RPWR (kŸ) C019 150 C020 Figure 21. MOSFET Power Dissipation Limit vs RPWR And RS (VIN = 48 V) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 15 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 8 Detailed Description 8.1 Overview The inline protection functionality of the LM5066 is designed to control the in-rush current to the load after insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag on the backplane’s supply voltage and the dV/dt of the voltage applied to the load. The effects on other circuits in the system are minimized by preventing possible unintended resets. When the circuit card is removed, a controlled shutdown can be implemented using the LM5066. In addition to a programmable current limit, the LM5066 monitors and limits the maximum power dissipation in the series-pass device to maintain operation within the device safe operating area (SOA). Either current limiting or power limiting for an extended period of time results in the shutdown of the series-pass device. In this event, the LM5066 can latch off or repetitively retry based on the hardware setting of the RETRY pin. When started, the number of retries can be set to none, 1, 2, 4, 8, 16, or infinite. The circuit breaker function quickly switches off the series-pass device upon detection of a severe overcurrent condition. Programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits shut down the LM5066 when the system input voltage is outside the desired operating range. The telemetry capability of the LM5066 provides intelligent monitoring of the input voltage, output voltage, input current, input power, temperature, and an auxiliary input. The LM5066 also provides a peak capture of the input power and programmable hardware averaging of the input voltage, current, power, and output voltage. Warning thresholds which trigger the SMBA pin may be programmed for input and output voltage, current, power, and temperature through the PMBus interface. Additionally, the LM5066 is capable of detecting damage to the external MOSFET, Q1. 16 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 PGD FB OUT VIN VIN_K SENSE 8.2 Functional Block Diagram LM5066 20 PA VDD REG VDD 2.46 V CB UV OV 12 bit ADC S/ H Current Limit Sense VAUX Diode Temp Sense SDAO 20 PA VDS GATE CONTROL GATE 4.2 mA 115 mA 16.5 V OUT Current Limit / Power Limit Control Power Limit Threshold 48/96/193 mV Snapshot Circuit Breaker Threshold MEASUREMENT/ FAULT REGISTORS SCL SDAI IDS CHARGE PUMP 26/50 mV Current Limit Threshold 2.97 VRef DIODE 1/30 1 M: VREF AMUX 1/30 4.8 PA Insertion Timer 75 PA Fault Timer 20 PA TIMER 21PA SMBUS INTERFACE TELEMETRY STATE MACHINE ov 2.46 V TIMER AND GATE LOGIC CONTROL uv SMBA 1.5 mA End Insertion Time 2.5 PA Fault Discharge 3.9 V 2.48 V 1.1 V ADDRESS DECODER 0.3 V 20 PA ADR0 UVLO/EN OVLO PWR Insertion Timer POR AGND 7.8V VIN GND RETRY 8.6 V VIN ADR2 Enable POR CL ADR1 8.3 Feature Description 8.3.1 Current Limit The current limit threshold is reached when the voltage across the sense resistor RSNS (VIN_K to SENSE) exceeds the ILIM threshold (26 mV if CL = VDD and 50 mV if CL = GND). In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault timer is active as described in the Fault Timer and Restart section. If the load current falls below the current limit threshold before the end of the Fault Timeout Period, the LM5066 resumes usual operation. If the current limit condition persists for longer than the Fault Timeout Period set by CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted. SMBA toggling can be disabled using the ALERT_MASK (D8h) register. For proper operation, the RSNS resistor value should be no higher than 200 mΩ. Higher values may create instability in the current limit control loop. The current limit threshold pin value may be overridden by setting appropriate bits in the DEVICE_SETUP register (D9h). Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 17 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) 8.3.2 Circuit Breaker If the load current increases rapidly (for example, the load is short circuited), the current in the sense resistor (RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds 1.94x or 3.87x (CL = GND) the current limit threshold, Q1 is quickly switched off by the 160-mA pulldown current at the GATE pin and a Fault Timeout Period begins. When the voltage across RSNS falls below the circuit breaker (CB) threshold, the 115-mA pulldown current at the GATE pin is switched off, and the gate voltage of Q1 is then determined by the current limit or the power limit functions. If the TIMER pin reaches 3.9 V before the current limiting or power limiting condition ceases, Q1 is switched off by the 4.2-mA pulldown current at the GATE pin as described in the Fault Timer and Restart section. A circuit breaker event causes the CIRCUIT BREAKER FAULT bit in the STATUS_OTHER (7Fh), STATUS_MFR_SPECIFIC (80h), and DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin are asserted unless this feature is disabled using the ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by setting appropriate bits in the DEVICE_SETUP (D9h) register. 8.3.3 Power Limit An important feature of the LM5066 is the MOSFET power limiting. The Power Limit function can be used to maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5066 determines the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current through the RSNS (VIN_K to SENSE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to regulate the current in Q1. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer and Restart section. If the power limit condition persists for longer than the Fault Timeout Period set by the timer capacitor, CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted unless this feature is disabled using the ALERT_MASK (D8h) register. 8.3.4 UVLO The series-pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range defined by the programmable UVLO and OVLO levels. Typically the UVLO level at VIN is set with a resistor divider. Referring to the Functional Block Diagram when VIN is below the UVLO level, the internal 20-µA current source at UVLO is enabled, the current source at OVLO is off, and Q1 is held off by the 4.2-mA pulldown current at the GATE pin. As VIN is increased, raising the voltage at UVLO above its threshold the 20 µA current source at UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for this threshold. With the UVLO/EN pin above its threshold, Q1 is switched on by the 20-µA current source at the GATE pin if the insertion time delay has expired. See the Application and Implementation section for a procedure to calculate the values of the threshold setting resistors. The minimum possible UVLO level at VIN can be set by connecting the UVLO/EN pin to VIN. In this case, Q1 is enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power-up, an UVLO condition causes the INPUT bit in the STATUS_WORD (79h) register, the VIN_UV_FAULT bit in the STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin is pulled low unless this feature is disabled using the ALERT_MASK (D8h) register. 8.3.5 OVLO The series-pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range defined by the programmable UVLO and OVLO levels. If VIN raises the OVLO pin voltage above its threshold, Q1 is switched off by the 4.2-mA pulldown current at the GATE pin, denying power to the load. When the OVLO pin is above its threshold, the internal 21-µA current source at OVLO is switched on, raising the voltage at OVLO to provide threshold hysteresis. When VIN is reduced below the OVLO level Q1 is re-enabled. An OVLO condition toggles the VIN_OV_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register and the VIN_OVERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA pin is pulled low unless this feature is disabled using the ALERT_MASK (D8h) register. See the Application and Implementation section for a procedure to calculate the threshold setting resistor values. 18 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Feature Description (continued) 8.3.6 Power Good Pin The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of sustaining 80 V in the off-state, and transients up to 100 V. An external pullup resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers. 8.3.7 VDD Sub-Regulator The LM5066 contains an internal linear sub-regulator, which steps down the input voltage to generate a 4.9-V rail used for powering low voltage circuitry. The VDD sub-regulator should be used as the pullup supply for the CL, RETRY, ADR2, ADR1, and ADR0 pins if they are to be tied high. It may also be used as the pullup supply for the PGD and the SMBus signals (SDA, SCL, and SMBA). The VDD sub-regulator is not designed to drive high currents and should not be loaded with other integrated circuits. The VDD pin is current limited to 30 mA in order to protect the LM5066 in the event of a short. The sub-regulator requires a ceramic bypass capacitance having a value of 1 µF or greater to be placed as close to the VDD pin as the PCB layout allows. 8.3.8 Remote Temperature Sensing The LM5066 is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base and collector of the MMBT3904 should be connected to the DIODE pin and the emitter to the LM5066 ground. Place the MMBT3904 near the device that requires temperature sensing. If the temperature of the hot swap pass MOSFET, Q1, is to be measured, the MMBT3904 should be placed as close to Q1 as the layout allows. The temperature is measured by means of a change in the diode voltage in response to a step in current supplied by the DIODE pin. The DIODE pin sources a constant 9.4 µA, but pulses 250 µA once every millisecond to measure the diode temperature. Take care in the PCB layout to keep the parasitic resistance between the DIODE pin and the MMBT3904 low so as not to degrade the measurement. In addition it is recommended to make a Kelvin connection from the emitter of the MMBT3904 to the GND of the part to ensure an accurate measurement. Additionally, a small 1000-pF bypass capacitor should be placed in parallel with the MMBT3904 to reduce the effects of noise. The temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). The default limits of the LM5066 causes SMBA pin to be pulled low if the measured temperature exceeds 125°C and disables Q1 if the temperature exceeds 150°C. These thresholds can be reprogrammed through the PMBus interface using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature measurement and protection capability of the LM5066 are not used, the DIODE pin should be grounded. Erroneous temperature measurements may result when the device input voltage is below the minimum operating voltage (10 V), due to VREF dropping out below the nominal voltage (2.97 V). At higher ambient temperatures, this measurement could read a value higher than the OT_FAULT_LIMIT, and trigger a fault, disabling Q1. In this case, the faults should be removed and the device reset by writing a 0h, followed by an 80h to the OPERATION (03h) register. 8.3.9 Damaged MOSFET Detection The LM5066 is able to detect whether the external MOSFET, Q1, is damaged under certain conditions. If the voltage across the sense resistor exceeds 4 mV while the GATE voltage is low or the internal logic indicates that the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h) registers are toggled high and the SMBA pin is asserted unless this feature is disabled using the ALERT_MASK register (D8h). This method effectively determines whether Q1 is shorted because of damage present between the drain and gate and/or drain and source. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 19 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 8.4 Device Functional Modes 8.4.1 Power-Up Sequence The VIN operating range of the LM5066 is 10 to 80 V, with a transient capability to 100 V. Referring to the and Figure 22, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held off by an internal 115-mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin prevents an inadvertent turn-on as the gate-to-drain (Miller) capacitance of the MOSFET is charged. Additionally, the TIMER pin is initially held at ground. When the VIN voltage reaches the POR threshold the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 4.8-µA current source, and Q1 is held off by a 4.2-mA pulldown current at the GATE pin regardless of the input voltage. The insertion time delay allows ringing and transients at VIN to settle before Q1 is enabled. The insertion time ends when the TIMER pin voltage reaches 3.9 V. CT is then quickly discharged by an internal 1.5-mA pulldown current. The GATE pin then switches on Q1 when VIN exceeds the UVLO threshold. If VIN is above the UVLO threshold at the end of the insertion time, Q1 the GATE pin charge pump sources 20 µA to charge the gate capacitance of Q1. The maximum voltage from the gate to source of the Q1 is limited by an internal 16.5-V Zener diode. As the voltage at the OUT pin increases, the LM5066 monitors the drain current and power dissipation of MOSFET Q1. In-rush current limiting or power limiting circuits, or both, actively control the current delivered to the load. During the in-rush limiting interval (t2 in Figure 22), an internal 75-µA fault timer current source charges CT. If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER pin reaches 3.9 V, the 75-µA current source is switched off, and CT is discharged by the internal 2.5-µA current sink (t3 in Figure 22). The in-rush limiting no longer engages unless a current-limit condition occurs. If the TIMER pin voltage reaches 3.9 V before in-rush current limiting or power limiting ceases during t2, a fault is declared and Q1 is turned off. See the Fault Timer and Restart section for a complete description of the fault mode. The LM5066 asserts the SMBA pin after the input voltage has exceeded its POR threshold to indicate that the volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the STATUS_MFR_SPECIFIC register (80h) indicates default configuration of warning thresholds and device operation and remains high until a CLEAR_FAULTS command is received. VIN UVLO VIN POR 3.9 V 4.8 PA 75 PA 2.5 PA TIMER GATE 115 mA pull-down 4.2 mA pull-down 20 PA source ILIMIT Load Current 2.46V FB PGD t1 Insertion Time t2 In rush Limiting t3 Normal Operation Figure 22. Power-Up Sequence (Current Limit Only) 20 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Device Functional Modes (continued) 8.4.2 Gate Control A charge pump provides the voltage at the GATE pin to enhance the N-channel MOSFET’s gate (Q1). During normal operating conditions (t3 in Figure 22), the gate of Q1 is held charged by an internal 20-µA current source. The charge pump peak voltage is roughly 13.5 V, which forces a VGS across Q1 of 13.5 V under normal operation. When the system voltage is initially applied, the GATE pin is held low by a 115-mA pulldown current. This helps prevent an inadvertent turn-on of Q1 through its drain-gate capacitance as the applied system voltage increases. During the insertion time (t1 in Figure 22) the GATE pin is held low by a 4.2-mA pulldown current. This maintains Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO. Following the insertion time, during t2 in Figure 22 the gate voltage of Q1 is modulated to keep the current or power dissipation level from exceeding the programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 3.9 V, the TIMER pin capacitor then discharges, and the circuit begins normal operation. If the in-rush limiting condition persists such that the TIMER pin reached 3.9 V during t2, the GATE pin is then pulled low by the 4.2-mA pulldown current. The GATE pin is then held low until either a power-up sequence is initiated (RETRY pin to VDD), or an automatic retry is attempted (RETRY pin to GROUND or floating). See the Fault Timer and Restart section. If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the 4.2-mA pulldown current to switch off Q1. 8.4.3 Fault Timer and Restart When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either limiting function is active, a 75-µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 22 (fault timeout period). If the fault condition subsides during the fault timeout period before the TIMER pin reaches 3.9 V, the LM5066 returns to the normal operating mode and CT is discharged by the 1.5mA current sink. If the TIMER pin reaches 3.9 V during the fault timeout period, Q1 is switched off by a 4.2-mA pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry configuration. If the RETRY pin is high, the LM5066 latches the GATE pin low at the end of the fault timeout period. CT is then discharged to ground by the 2.5-µA fault current sink. The GATE pin is held low by the 4.2-mA pulldown current until a power-up sequence is externally initiated by cycling the input voltage (VIN), or momentarily pulling the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 23. The voltage at the TIMER pin must be <0.3 V for the restart procedure to be effective. The TIMER_LATCHED_OFF bit in the DIAGNOSTIC_WORD (E1h) register remains high while the latched off condition persists. VIN R1 VIN UVLO/EN Restart Control R2 OVLO R3 GND Figure 23. Latched Fault Restart Control The LM5066 provides an automatic restart sequence which consists of the TIMER pin cycling between 3.9 and 1.2 V seven times after the fault timeout period, as shown in Figure 24. The period of each cycle is determined by the 75-µA charging current, the 2.5-µA discharge current, and the value of the capacitor, CT. When the TIMER pin reaches 0.3 V during the eighth high-to-low ramp, the 20-µA current source at the GATE pin turns on Q1. If the fault condition is still present, the fault timeout period and the restart sequence repeat. The RETRY pin allows selecting no retries or infinite retries. Finer control of the retry behavior can be achieved through the DEVICE_SETUP (D9h) register. Retry counts of 0, 1, 2, 4, 8, 16, or infinite may be selected by setting the appropriate bits in the DEVICE_SETUP (D9h) register. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 21 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Device Functional Modes (continued) Fault Detection ILIMIT Load Current 20 PA Gate Charge 4.2 mA pulldown GATE Pin 2.5 PA 3.9 V 75 PA TIMER Pin 1.1 V 1 2 3 7 8 0.3V t RESTART Fault Timeout Period Figure 24. Restart Sequence 8.4.4 Shutdown Control The load current can be remotely switched off by taking the UVLO/EN pin below its threshold with an open collector or open-drain device, as shown in Figure 25. When UVLO/EN pin is released, the LM5066 switches on the FET with in-rush current and power limiting. VIN R1 VIN UVLO/EN Shutdown Control R2 OVLO R3 GND Figure 25. Shutdown Control 8.4.5 Enabling/Disabling and Resetting The output can be disabled at during normal operation by either pulling the UVLO/EN pin to below its threshold or the OVLO pin above its threshold. This will cause the GATE voltage to be forced low with a pulldown strength of 4.2 mA. Toggling the UVLO/EN pin also resets the LM5066 from a latched-off state due to an overcurrent or over-power limit condition that caused the maximum allowed number of retries to be exceeded. While the UVLO/EN or OVLO pins can be used to disable the output, they have no effect on the volatile memory or address location of the LM5066. User-stored values for address, device operation, and warning and fault levels programmed through the SMBus are preserved while the LM5066 is powered regardless of the state of the UVLO/EN and OVLO pins. The output may also be enabled or disabled by writing 80h or 0h to the OPERATION (03h) register. To re-enable after a fault, the fault condition should be cleared by programing the OPERATION (03h) register with 0h and then 80h. The SMBus address of the LM5066 is captured based-on the states of the ADR0, ADR1, and ADR2 pins (GND, NC, and VDD) during turn on and is latched into a volatile register after VDD has exceeded its POR threshold of 4.1 V. Reassigning or postponing the address capture is accomplished by holding the VREF pin to ground. Pulling the VREF pin low also resets the logic and erases the volatile memory of the LM5066. When released, the VREF pin charges up to its final value and the address is latched into a volatile register when the voltage at the VREF exceeds 2.55 V. 22 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 8.5 Programming 8.5.1 PMBus Command Support The device features an SMBus interface that allows the use of PMBus commands to set warn levels, error masks, and get telemetry on VIN, VOUT, IIN, VAUX, and PIN. The supported PMBus commands are shown in Table 2. Table 2. Supported PMBus Commands CODE NAME 01h OPERATION 03h CLEAR_FAULTS 19h CAPABILITY 43h VOUT_UV_WARN_LIMIT 4Fh FUNCTION R/W NUMBER OF DATA BYTES DEFAULT VALUE Retrieves or stores the operation status R/W 1 80h Send byte 0 Clears the status registers and re-arms the black box registers for updating Retrieves the device capability R 1 B0h Retrieves or stores output undervoltage warn limit threshold R/W 2 0000h OT_FAULT_LIMIT Retrieves or stores over temperature fault limit threshold R/W 2 0960h (150°C) 51h OT_WARN_LIMIT Retrieves or stores over temperature warn limit threshold R/W 2 07D0h (125°C) 57h VIN_OV_WARN_LIMIT Retrieves or stores input overvoltage warn limit threshold R/W 2 0FFFh 58h VIN_UV_WARN_LIMIT Retrieves or stores input undervoltage warn limit threshold R/W 2 0000h 78h STATUS_BYTE Retrieves information about the parts operating status R 1 49h 79h STATUS_WORD Retrieves information about the parts operating status R 2 3849h 7Ah STATUS_VOUT Retrieves information about output voltage status R 1 00h 7Ch STATUS_INPUT Retrieves information about input status R 1 10h 7Dh STATUS_TEMPERATURE Retrieves information about temperature status R 1 00h 7Eh STATUS_CML Retrieves information about communications status R 1 00h Retrieves information about circuit breaker and MOSFET shorted status R 1 10h Retrieves input voltage measurement R 2 0000h Retrieves output voltage measurement R 2 0000h Retrieves temperature measurement R 2 0190h Retrieves manufacturer ID in ASCII characters (NSC) R 3 4Eh 53h 43h 80h STATUS_MFR_SPECIFIC 88h READ_VIN 8Bh READ_VOUT 8Dh READ_TEMPERATURE_1 99h MFR_ID Retrieves part number in ASCII characters. (LM5066) R 8 4Ch 4Dh 35h 30h 36h 36h 0h 0h Retrieves part revision letter or number in ASCII (for example, AA) R 2 41h 41h MFR_SPECIFIC_00 READ_VAUX Retrieves auxiliary voltage measurement R 2 0000h D1h MFR_SPECIFIC_01 MFR_READ_IIN Retrieves input current measurement R 2 0000h D2h MFR_SPECIFIC_02 MFR_READ_PIN Retrieves input power measurement R 2 0000h D3h MFR_SPECIFIC_03 MFR_IIN_OC_WARN_LIMIT Retrieves or stores input current limit warn threshold R/W 2 0FFFh D4h MFR_SPECIFIC_04 MFR_PIN_OP_WARN_LIMIT Retrieves or stores input power limit warn threshold R/W 2 0FFFh D5h MFR_SPECIFIC_05 READ_PIN_PEAK Retrieves measured peak input power measurement R 2 0000h D6h MFR_SPECIFIC_06 CLEAR_PIN_PEAK Resets the contents of the peak input power register to 0 Send byte 0 D7h MFR_SPECIFIC_07 GATE_MASK Allows the user to disable MOSFET gate shutdown for various fault conditions R/W 1 9Ah MFR_MODEL 9Bh MFR_REVISION D0h Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 0000h 23 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Programming (continued) Table 2. Supported PMBus Commands (continued) FUNCTION R/W NUMBER OF DATA BYTES DEFAULT VALUE MFR_SPECIFIC_08 ALERT_MASK Retrieves or stores user SMBA fault mask R/W 2 0820h MFR_SPECIFIC_09 DEVICE_SETUP Retrieves or stores information about number of retry attempts R/W 1 0000h R 12 08E0h 0000h 0000h 0000h 0000h 0000h R/W 1 00h CODE NAME D8h D9h DAh MFR_SPECIFIC_10 BLOCK_READ Retrieves most recent diagnostic and telemetry information in a single transaction DBh MFR_SPECIFIC_11 SAMPLES_FOR_AVG DCh MFR_SPECIFIC_12 READ_AVG_VIN Retrieves averaged input voltage measurement R 2 0000h DDh MFR_SPECIFIC_13 READ_AVG_VOUT Retrieves averaged output voltage measurement R 2 0000h DEh MFR_SPECIFIC_14 READ_AVG_IIN Retrieves averaged input current measurement R 2 0000h DFh MFR_SPECIFIC_15 READ_AVG_PIN Retrieves averaged input power measurement R 2 0000h Exponent value AVGN for number of samples to be averaged (N = 2AVGN), range = 00h to 0Ch E0h MFR_SPECIFIC_16 BLACK_BOX_READ E1h MFR_SPECIFIC_17 DIAGNOSTIC_WORD_READ MFR_SPECIFIC_18 AVG_BLOCK_READ E2h Captures diagnostic and telemetry information, which are latched when the first SMBA event occurs after faults are cleared R 12 08E0h 0000h 0000h 0000h 0000h 0000h Manufacturer-specific parallel of the STATUS_WORD to convey all FAULT/WARN data in a single transaction R 2 08E0h 12 08E0h 0000h 0000h 0000h 0000h 0000h Retrieves most recent average telemetry and diagnostic information in a single transaction R 8.5.2 Standard PMBus Commands 8.5.2.1 OPERATION (01h) The OPERATION command is a standard PMBus command that controls the MOSFET switch. This command can be used to switch the MOSFET on and off under host control. It is also used to re-enable the MOSFET after a fault triggered shutdown. Writing an OFF command, followed by an ON command, clears all faults and reenables the device. Writing only an ON after a fault-triggered shutdown does not clear the fault registers or reenable the device. The OPERATION command is issued with the write byte protocol. Table 3. Recognized OPERATION Command Values VALUE MEANING DEFAULT 80h Switch ON 80h 00h Switch OFF N/A 8.5.2.2 CLEAR_FAULTS (03h) The CLEAR_FAULTS command is a standard PMBus command that resets all stored warning and fault flags and the SMBA signal. If a fault or warning condition still exists when the CLEAR_FAULTS command is issued, the SMBA signal may not clear or re-asserts almost immediately. Issuing a CLEAR_FAULTS command does not cause the MOSFET to switch back on in the event of a fault turnoff; that must be done by issuing an OPERATION command after the fault condition is cleared. This command uses the PMBus send byte protocol. 24 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 8.5.2.3 CAPABILITY (19h) The CAPABILITY command is a standard PMBus command that returns information about the PMBus functions supported by the LM5066 This command is read with the PMBus read byte protocol. Table 4. CAPABILITY Register VALUE MEANING DEFAULT B0h Supports packet error check, 400 Kb/s, supports SMBus alert B0h 8.5.2.4 VOUT_UV_WARN_LIMIT (43h) The VOUT_UV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the VOUT undervoltage warning detection. Reading and writing to this register should use the coefficients shown in Table 42. Accesses to this command should use the PMBus read or write word protocol. If the measured value of VOUT falls below the value in this register, VOUT UV warn flags are set and the SMBA signal is asserted. Table 5. VOUT_UV_WARN_LIMIT Register VALUE MEANING DEFAULT 0001h to 0FFFh VOUT undervoltage warning detection threshold 0000h (disabled) 0000h VOUT undervoltage warning disabled N/A 8.5.2.5 OT_FAULT_LIMIT (4Fh) The OT_FAULT_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the overtemperature fault detection. Reading and writing to this register should use the coefficients shown in Table 42. Accesses to this command should use the PMBus read or write word protocol. If the measured temperature exceeds this value, an overtemperature fault is triggered and the MOSFET is switched off, OT FAULT flags set, and the SMBA signal asserted. After the measured temperature falls below the value in this register, the MOSFET may be switched back on with the OPERATION command. A single temperature measurement is an average of 16 round-robin cycles; therefore, the minimum temperature fault detection time is 16 ms. Table 6. OT_FAULT_LIMIT Register VALUE MEANING DEFAULT 0000h to 0FFEh Over-temperature fault threshold value 0960h (150°C) 0FFFh Over-temperature fault detection disabled N/A 8.5.2.6 OT_WARN_LIMIT (51h) The OT_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the over-temperature warning detection. Reading and writing to this register should use the coefficients shown in Table 42. Accesses to this command should use the PMBus read or write word protocol. If the measured temperature exceeds this value, an over-temperature warning is triggered and the OT WARN flags set in the respective registers and the SMBA signal asserted. A single temperature measurement is an average of 16 round-robin cycles; therefore, the minimum temperature warn detection time is 16 ms. Table 7. OT_WARN_LIMIT Register VALUE MEANING DEFAULT 0000h to 0FFEh Over-temperature warn threshold value 07D0h (125°C) 0FFFh Over-temperature warn detection disabled N/A Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 25 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 8.5.2.7 VIN_OV_WARN_LIMIT (57h) The VIN_OV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the VIN overvoltage warning detection. Reading and writing to this register should use the coefficients shown in Table 42. Accesses to this command should use the PMBus read or write word protocol. If the measured value of VIN rises above the value in this register, VIN OV warn flags are set in the respective registers and the SMBA signal is asserted. Table 8. VIN_OV_WARN_LIMIT Register VALUE MEANING DEFAULT 0h to 0FFEh VIN overvoltage warning detection threshold 0FFFh (disabled) 0FFFh VIN overvoltage warning disabled N/A 8.5.2.8 VIN_UV_WARN_LIMIT (58h) The VIN_UV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the VIN undervoltage warning detection. Reading and writing to this register should use the coefficients shown in Table 42. Accesses to this command should use the PMBus read or write word protocol. If the measured value of VIN falls below the value in this register, VIN UV warn flags are set in the respective register, and the SMBA signal is asserted. Table 9. VIN_UV_WARN_LIMIT Register VALUE MEANING DEFAULT 1h to 0FFFh VIN undervoltage warning detection threshold 0000h (disabled) 0000h VIN undervoltage warning disabled N/A 8.5.2.9 STATUS_BYTE (78h) The STATUS BYTE is a standard PMBus command that returns the value of a number of flags indicating the state of the LM5066. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be removed on the system and a CLEAR_FAULTS command issued. Table 10. STATUS_BYTE Definitions BIT NAME 7 BUSY 6 OFF 5 4 MEANING DEFAULT Not supported, always 0 0 This bit is asserted if the MOSFET is not switched on for any reason. 1 VOUT OV Not supported, always 0 0 IOUT OC Not supported, always 0 0 A VIN undervoltage fault has occurred 1 A temperature fault or warning has occurred 0 A communication fault has occurred 0 A fault or warning not listed in bits [7:1] has occurred 1 3 VIN UV fault 2 TEMPERATURE 1 CML 0 None of the above 8.5.2.10 STATUS_WORD (79h) The STATUS_WORD command is a standard PMBus command that returns the value of a number of flags indicating the state of the LM5066. Accesses to this command should use the PMBus read word protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR _FAULTS command issued. The INPUT and VIN UV flags default to 1 on startup; however, they are cleared to 0 after the first time the input voltage exceeds the resistor-programmed UVLO threshold. 26 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Table 11. STATUS_WORD Definitions BIT NAME 15 VOUT 14 IOUT/POUT 13 INPUT 12 FET FAIL 11 POWER GOOD MEANING DEFAULT An output voltage fault or warning has occurred 0 Not supported, always 0 0 An input voltage or current fault has occurred 1 FET is shorted 1 The Power Good signal has been negated 1 Not supported, always 0 0 Circuit breaker fault triggered 0 10 FANS 9 CB_Fault 8 UNKNOWN Not supported, always 0 0 7 BUSY Not supported, always 0 0 6 OFF This bit is asserted if the MOSFET is not switched on for any reason. 1 5 VOUT OV Not supported, always 0 0 4 IOUT OC Not supported, always 0 0 3 VIN UV A VIN undervoltage fault has occurred 1 2 TEMPERATURE A temperature fault or warning has occurred 0 1 CML A communication fault has occurred 0 0 None of the above A fault or warning not listed in bits [7:1] has occurred 1 8.5.2.11 STATUS_VOUT (7Ah) The STATUS_VOUT command is a standard PMBus command that returns the value of the VOUT UV warn flag. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued. Table 12. STATUS_VOUT Definitions BIT NAME 7 VOUT OV fault Not supported, always 0 MEANING DEFAULT 0 6 VOUT OV warn Not supported, always 0 0 5 VOUT UV warn A VOUT undervoltage warning has occurred 0 4 VOUT UV fault Not supported, always 0 0 3 VOUT max Not supported, always 0 0 2 TON max fault Not supported, always 0 0 1 TOFF max fault Not supported, always 0 0 0 VOUT tracking error Not supported, always 0 0 8.5.2.12 STATUS_INPUT (7Ch) The STATUS_INPUT command is a standard PMBus command that returns the value of a number of flags related to input voltage, current, and power. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued. The VIN UV warn flag defaults to 1 on startup; however, it is cleared to 0 after the first time the input voltage increases above the resistor-programmed UVLO threshold. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 27 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table 13. STATUS_INPUT Definitions BIT NAME 7 VIN OV fault A VIN overvoltage fault has occurred MEANING DEFAULT 0 6 VIN OV warn A VIN overvoltage warning has occurred 0 5 VIN UV warn A VIN undervoltage warning has occurred 1 4 VIN UV fault A VIN undervoltage fault has occurred 0 3 Insufficient voltage Not supported, always 0 0 2 IIN OC fault An IIN overcurrent fault has occurred 0 1 IIN OC warn An IIN overcurrent warning has occurred 0 0 PIN OP warn A PIN overpower warning has occurred 0 8.5.2.13 STATUS_TEMPERATURE (7dh) The STATUS_TEMPERATURE is a standard PMBus command that returns the value of the of a number of flags related to the temperature telemetry value. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued. Table 14. STATUS_TEMPERATURE Definitions BIT NAME 7 Overtemp fault An overtemperature fault has occurred MEANING DEFAULT 0 6 Overtemp warn An overtemperature warning has occurred 0 5 Undertemp warn Not supported, always 0 0 4 Undertemp fault Not supported, always 0 0 3 Reserved Not supported, always 0 0 2 Reserved Not supported, always 0 0 1 Reserved Not supported, always 0 0 0 Reserved Not supported, always 0 0 8.5.2.14 STATUS_CML (7Eh) The STATUS_CML is a standard PMBus command that returns the value of a number of flags related to communication faults. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, a CLEAR_FAULTS command should be issued. Table 15. STATUS_CML Definitions BIT NAME DEFAULT 7 Invalid or unsupported command received 0 6 Invalid or unsupported data received 0 5 Packet error check failed 0 4 Not supported, always 0 0 3 Not supported, always 0 0 2 Not supported, always 0 0 1 Miscellaneous communications fault has occurred 0 0 Not supported, always 0 0 8.5.2.15 STATUS_MFR_SPECIFIC (80h) The STATUS_MFR_SPECIFIC command is a standard PMBus command that contains manufacturer specific status information. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command should be issued. 28 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Table 16. STATUS_MFR_SPECIFIC Definitions BIT MEANING DEFAULT 7 Circuit breaker fault 0 6 External MOSFET shorted fault 0 5 Not supported, always 0 0 4 Defaults loaded 1 3 Not supported, always 0 0 2 Not supported, always 0 0 1 Not supported, always 0 0 0 Not supported, always 0 0 8.5.2.16 READ_VIN (88h) The READ_VIN command is a standard PMBus command that returns the 12-bit measured value of the input voltage. Reading this register should use the coefficients shown in Table 42. Accesses to this command should use the PMBus read word protocol. This value is also used internally for the VIN overvoltage and undervoltage warning detection. Table 17. READ_VIN Register VALUE MEANING DEFAULT 0000h to 0FFFh Measured value for VIN 0000h 8.5.2.17 READ_VOUT (8Bh) The READ_VOUT command is a standard PMBus command that returns the 12-bit measured value of the output voltage. Reading this register should use the coefficients shown in Table 42. Accesses to this command should use the PMBus read word protocol. This value is also used internally for the VOUT undervoltage warning detection. Table 18. READ_VOUT Register VALUE MEANING DEFAULT 0000h to 0FFFh Measured value for VOUT 0000h 8.5.2.18 READ_TEMPERATURE_1 (8Dh) The READ_TEMPERATURE_1 command is a standard PMBus command that returns the signed value of the temperature measured by the external temperature sense diode. Reading this register should use the coefficients shown in Table 42. Accesses to this command should use the PMBus read word protocol. This value is also used internally for the overtemperature fault and warning detection. This data has a range of –256°C to 255°C after the coefficients are applied. Table 19. READ_TEMPERATURE_1 Register VALUE MEANING DEFAULT 0000h to 0FFFh Measured value for TEMPERATURE 0000h 8.5.2.19 MFR_ID (99h) The MFR_ID command is a standard PMBus command that returns the identification of the manufacturer. To read the MFR_ID, use the PMBus block read protocol. Table 20. MFR_ID Register BYTE NAME 0 Number of bytes VALUE 03h 1 MFR ID-1 4Eh ‘N’ 2 MFR ID-2 53h ‘S' Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 29 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table 20. MFR_ID Register (continued) BYTE NAME VALUE 3 MFR ID-3 43h ‘C' 8.5.2.20 MFR_MODEL (9Ah) The MFR_MODEL command is a standard PMBus command that returns the part number of the chip. To read the MFR_MODEL, use the PMBus block read protocol. Table 21. MFR_MODEL Register BYTE NAME VALUE 0 Number of bytes 08h 1 MFR ID-1 4Ch ‘L’ 2 MFR ID-2 4Dh ‘M’ 3 MFR ID-3 35h ‘5’ 4 MFR ID-4 30h ‘0’ 5 MFR ID-5 36h ‘6’ 6 MFR ID-6 36h ‘6’ 7 MFR ID-7 00h 8 MFR ID-8 00h 8.5.2.21 MFR_REVISION (9Bh) The MFR_REVISION command is a standard PMBus command that returns the revision level of the part. To read the MFR_REVISION, use the PMBus block read protocol. Table 22. MFR_REVISION Register BYTE NAME 0 Number of bytes VALUE 02h 1 MFR ID-1 41h ‘A’ 2 MFR ID-2 41h ‘A’ 8.5.3 Manufacturer Specific PMBus Commands 8.5.3.1 MFR_SPECIFIC_00: READ_VAUX (D0h) The READ_VAUX command reports the 12-bit ADC measured auxiliary voltage. Voltages greater than or equal to 2.97 V to ground are reported at plus full scale (0FFFh). Voltages less than or equal to 0 V referenced to ground are reported as 0 (0000h). To read data from the READ_VAUX command, use the PMBus read word protocol. Table 23. READ_VAUX Register VALUE MEANING DEFAULT 0000h to 0FFFh Measured value for VAUX input 0000h 8.5.3.2 MFR_SPECIFIC_01: MFR_READ_IIN (D1h) The MFR_READ_IIN command reports the 12-bit ADC measured current sense voltage. To read data from the MFR_READ_IIN command, use the PMBus read word protocol. Reading this register should use the coefficients shown in Table 42. See the section Reading and Writing Telemetry Data and Warning Thresholds to calculate the values to use. Table 24. MFR_READ_IIN Register VALUE MEANING DEFAULT 0000h to 0FFFh Measured value for input current sense voltage 0000h 30 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 8.5.3.3 MFR_SPECIFIC_02: MFR_READ_PIN (D2h) The MFR_READ_PIN command reports the upper 12 bits of the VIN × IIN product as measured by the 12-bit ADC. To read data from the MFR_READ_PIN command, use the PMBus read word protocol. Reading this register should use the coefficients shown in Table 42. See the section Reading and Writing Telemetry Data and Warning Thresholds to calculate the values to use. Table 25. MFR_READ_PIN Register VALUE MEANING DEFAULT 0000h to 0FFFh VALUE for input current x input voltage 0000h 8.5.3.4 MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h) The MFR_IIN_OC_WARN_LIMIT PMBus command sets the input overcurrent warning threshold. In the event that the input current rises above the value set in this register, the IIN overcurrent flags are set in the respective registers and the SMBA is asserted. To access the MFR_IIN_OC_WARN_LIMIT register, use the PMBus read/write word protocol. Reading and writing to this register should use the coefficients shown in Table 42. Table 26. MFR_IIN_OC_WARN_LIMIT Register VALUE MEANING DEFAULT 0000h to 0FFEh Value for input overcurrent warn limit 0FFFh 0FFFh Input overcurrent warning disabled N/A 8.5.3.5 MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h) The MFR_PIN_OP_WARN_LIMIT PMBus command sets the input over-power warning threshold. In the event that the input power rises above the value set in this register, the PIN over-power flags are set in the respective registers and the SMBA is asserted. To access the MFR_PIN_OP_WARN_LIMIT register, use the PMBus read/write word protocol. Reading and writing to this register should use the coefficients shown in Table 42. Table 27. MFR_PIN_OPWARN_LIMIT Register VALUE MEANING DEFAULT 0000h to 0FFEh Value for input over power warn limit 0FFFh 0FFFh Input over power warning disabled N/A 8.5.3.6 MFR_SPECIFIC_05: READ_PIN_PEAK (D5h) The READ_PIN_PEAK command reports the maximum input power measured since a power-on reset or the last CLEAR_PIN_PEAK command. To access the READ_PIN_PEAK command, use the PMBus read word protocol. Use the coefficients shown in Table 42. Table 28. READ_PIN_PEAK Register VALUE MEANING DEFAULT 0000h to 0FFFh Maximum value for input current × input voltage since reset or last clear 0000h 8.5.3.7 MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h) The CLEAR_PIN_PEAK command clears the PIN PEAK register. This command uses the PMBus send byte protocol. 8.5.3.8 MFR_SPECIFIC_07: GATE_MASK (D7h) The GATE_MASK register allows the hardware to prevent fault conditions from switching off the MOSFET. When the bit is high, the corresponding FAULT has no control over the MOSFET gate. All status registers are still updated (STATUS, DIAGNOSTIC) and SMBA is still asserted. This register is accessed with the PMBus read/write byte protocol. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 31 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com CAUTION Inhibiting the MOSFET switch off in response to overcurrent or circuit breaker fault conditions will likely result in the destruction of the MOSFET. This functionality must be used with great care and supervision. Table 29. MFR_SPECIFIC_07 Gate Mask Definitions BIT NAME DEFAULT 7 Not used, always 0 0 6 Not used, always 0 0 5 VIN UV FAULT 0 4 VIN OV FAULT 0 3 IIN/PFET FAULT 0 2 OVERTEMP FAULT 0 1 Not used, always 0 0 0 CIRCUIT BREAKER FAULT 0 The IIN/PFET fault refers to the input current fault and the MOSFET power dissipation fault. There is no input power fault detection, only input power warning detection. 8.5.3.9 MFR_SPECIFIC_08: ALERT_MASK (D8h) The ALERT_MASK command is used to mask the SMBA when a specific fault or warning has occurred. Each bit corresponds to one of the 14 different analog and digital faults or warnings that would normally result in an SMBA being asserted. When the corresponding bit is high, that condition does not cause the SMBA to be asserted. If that condition occurs, the registers where that condition is captured is still updated (STATUS registers, DIAGNOSTIC_WORD) and the external MOSFET gate control is still active (VIN_OV_FAULT, VIN_UV_FAULT, IIN/PFET_FAULT, CB_FAULT, OT_FAULT). This register is accessed with the PMBus read/write word protocol. The VIN UNDERVOLTAGE FAULT flag defaults to 1 on startup; however, it clears to 0 after the first time the input voltage increases above the resistor-programmed UVLO threshold. Table 30. ALERT_MASK Definitions BIT 32 NAME DEFAULT 15 VOUT UNDERVOLTAGE WARN 0 14 IIN LIMIT warn 0 13 VIN UNDERVOLTAGE WARN 0 12 VIN OVERVOLTAGE WARN 0 11 POWER GOOD 1 10 OVERTEMP WARN 0 9 Not used 0 8 OVERPOWER LIMIT WARN 0 7 Not used 0 6 EXT_MOSFET_SHORTED 0 5 VIN UNDERVOLTAGE FAULT 1 4 VIN OVERVOLTAGE FAULT 0 3 IIN/PFET FAULT 0 2 OVERTEMPERATURE FAULT 0 1 CML FAULT (communications fault) 0 0 CIRCUIT BREAKER FAULT 0 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 8.5.3.10 MFR_SPECIFIC_09: DEVICE_SETUP (D9h) The DEVICE_SETUP command can be used to override pin settings to define operation of the LM5066 under host control. This command is accessed with the PMBus read/write byte protocol. Table 31. DEVICE_SETUP Byte Format BIT NAME MEANING 111 = Unlimited retries 110 = Retry 16 times 101 = Retry 8 times 100 = Retry 4 times 011 = Retry 2 times 010 = Retry 1 time 001 = No retries 000 = Pin configured retries 7:5 Retry setting 4 Current limit setting 3 CB/CL ratio 2 Current limit configuration 1 Unused 0 Unused 0 = High setting (50 mV) 1 = Low setting (26 mV) 0 = Low setting (1.9x) 1 = High setting (3.9x) 0 = Use pin settings 1 = Use SMBus settings To configure the current limit setting with this register, it is necessary to set the current limit configuration bit (2) to 1 to enable the register to control the current limit function and the current limit setting bit (4) to select the desired setting. If the current limit configuration bit is not set, the pin setting is used. The circuit breaker to current limit ratio value is set by the CB / CL ratio bit (3). Note that if the current limit configuration is changed, the samples for the telemetry averaging function are not reset. TI recommends to allow a full averaging update period with the new current limit configuration before processing the averaged data. Note that the current limit configuration affects the coefficients used for the current and power measurements and warning registers. 8.5.3.11 MFR_SPECIFIC_10: BLOCK_READ (DAh) The BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output telemetry information (IIN, VOUT, VIN, PIN) as well as TEMPERATURE to capture all of the operating information of the LM5066 in a single SMBus transaction. The block is 12-bytes long with telemetry information being sent out in the same manner as if an individual READ_XXX command had been issued (shown in Table 32). The contents of the block read register are updated every clock cycle (85 ns) as long as the SMBus interface is idle. BLOCK_READ also specifies that the VIN, VOUT, IIN and PIN measurements are all time-aligned. If separate commands are used, individual samples may not be time-aligned because of the delay necessary for the communication protocol. The block read command is read through the PMBus block read protocol. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 33 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table 32. BLOCK_READ Register Format Byte Count (Always 12) (1 Byte) DIAGNOSTIC_WORD (1 word) IIN_BLOCK (1 word) VOUT_BLOCK (1 word) VIN_BLOCK (1 word) PIN_BLOCK (1 word) TEMP_BLOCK (1 word) 8.5.3.12 MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh) The SAMPLES_FOR_AVG command is a manufacturer-specific command for setting the number of samples used in computing the average values for IIN, VIN, VOUT, and PIN. The decimal equivalent of the AVGN nibble is the power of 2 samples, (for example, AVGN = 12 equates to N = 4096 samples used in computing the average). The LM5066 supports average numbers of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, and 4096. The SAMPLES_FOR_AVG number applies to average values of IIN, VIN, VOUT, and PIN simultaneously. The LM5066 uses simple averaging. This is accomplished by summing consecutive results up to the number programmed, then dividing by the number of samples. Averaging is calculated according to the following sequence: Y = (X(N) + X(N-1) + ... + X(0)) / N (1) When the averaging has reached the end of a sequence (for example, 4096 samples are averaged), then a whole new sequence begins that requires the same number of samples (in this example, 4096) to be taken before the new average is ready. 34 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Table 33. SAMPLES_FOR_AVG Register AVGN (b) N = 2AVGN Averaging / Register Update Period (ms) 0000b 1 1 0001b 2 2 0010b 4 4 0011b 8 8 0100b 16 16 0101b 32 32 0110b 64 64 0111b 128 128 1000b 256 256 1001b 512 512 1010b 1024 1024 1011b 2048 2048 1100b 4096 4096 Note that a change in the SAMPLES_FOR_AVG register is not reflected in the average telemetry measurements until the present averaging interval has completed. The default setting for AVGN is 1000b, or 08h. The SAMPLES_FOR_AVG register is accessed with the PMBus read/write byte protocol. Table 34. SAMPLES_FOR_AVG Register VALUE MEANING DEFAULT 00h to 0Ch Exponent (AVGN) for number of samples to average over 00h 8.5.3.13 MFR_SPECIFIC_12: READ_AVG_VIN (DCh) The READ_AVG_VIN command reports the 12-bit ADC measured input average voltage. If the data is not ready, the returned value is the previous averaged data. However, if there is no previously averaged data, the default value (0000h) is returned. This data is read with the PMBus read word protocol. This register should use the coefficients shown in Table 42. Table 35. READ_AVG_VIN Register VALUE MEANING DEFAULT 0000h to 0FFFh Average of measured values for input voltage 0000h 8.5.3.14 MFR_SPECIFIC_13: READ_AVG_VOUT (DDh) The READ_AVG_VOUT command reports the 12-bit ADC measured current sense average voltage. The returned value is the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus read word protocol. This register should use the coefficients shown in Table 42. Table 36. READ_AVG_VOUT Register VALUE MEANING DEFAULT 0000h to 0FFFh Average of measured values for output voltage 0000h 8.5.3.15 MFR_SPECIFIC_14: READ_AVG_IIN (DEh) The READ_AVG_IIN command reports the 12-bit ADC measured current sense average voltage. The returned value is the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus read word protocol. This register should use the coefficients shown in Table 42. Table 37. READ_AVG_IIN Register VALUE MEANING DEFAULT 0000h to 0FFFh Average of measured values for current sense voltage 0000h Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 35 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 8.5.3.16 MFR_SPECIFIC_15: READ_AVG_PIN The READ_AVG_PIN command reports the upper 12-bits of the average VIN × IIN product as measured by the 12-bit ADC. The user can read the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus read word protocol. This register should use the coefficients shown in Table 42. Table 38. READ_AVG_PIN Register VALUE MEANING DEFAULT 0000h to 0FFFh Average of measured value for input voltage x input current sense voltage 0000h 8.5.3.17 MFR_SPECIFIC_16: BLACK_BOX_READ (E0h) The BLACK BOX READ command retrieves the BLOCK READ data which was latched in at the first assertion of SMBA by the LM5066. It is re-armed with the CLEAR_FAULTS command. It is the same format as the BLOCK_READ registers, the only difference is that its contents are updated with the SMBA edge rather than the internal clock edge. This command is read with the PMBus block read protocol. 8.5.3.18 MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) The READ_DIAGNOSTIC_WORD PMBus command reports all of the LM5066 faults and warnings in a single read operation. The standard response to the assertion of the SMBA signal of issuing multiple read requests to various status registers can be replaced by a single word read to the DIAGNOSTIC_WORD register. The READ_DIAGNOSTIC_WORD command should be read with the PMBus read word protocol. The READ_DIAGNOSTIC_WORD is also returned in the BLOCK_READ, BLACK_BOX_READ, and AVG_BLOCK_READ operations. Table 39. DIAGNOSTIC_WORD Format BIT MEANING DEFAULT 15 VOUT_UNDERVOLTAGE_WARN 0 14 IIN_OP_WARN 0 13 VIN_UNDERVOLTAGE_WARN 0 12 VIN_OVERVOLTAGE_WARN 0 11 POWER GOOD 1 10 OVER_TEMPERATURE_WARN 0 9 TIMER_LATCHED_OFF 0 8 EXT_MOSFET_SHORTED 0 7 CONFIG_PRESET 1 6 DEVICE_OFF 1 5 VIN_UNDERVOLTAGE_FAULT 1 4 VIN_OVERVOLTAGE_FAULT 0 3 IIN_OC/PFET_OP_FAULT 0 2 OVER_TEMPERATURE_FAULT 0 1 CML_FAULT 0 0 CIRCUIT_BREAKER_FAULT 0 8.5.3.19 MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h) The AVG_BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output average telemetry information (IIN, VOUT, VIN, and PIN) and temperature to capture all of the operating information of the part in a single PMBus transaction. The block is 12-bytes long with telemetry information sent out in the same manner as if an individual READ_AVG_XXX command had been issued (shown in Table 40). AVG_BLOCK_READ also specifies that the VIN, VOUT, and IIN measurements are all time-aligned whereas there is a chance they may not be if read with individual PMBus commands. To read data from the AVG_BLOCK_READ command, use the SMBus block read protocol. 36 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Table 40. AVG_BLOCK_READ Register Format Byte Count (Always 12) (1 Byte) DIAGNOSTIC_WORD (1 word) AVG_IIN (1 word) AVG_VOUT (1 word) AVG_VIN (1 word) AVG_PIN (1 word) TEMPERATURE (1 word) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 37 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com To load +48 GATE DIODE VAUX VIN_K SENSE UVLO/EN OUT OVLO GATE MASK CURRENT LIMIT CMP 2.48 2.46 MOSFET DISSIPATION LIMIT VIN OV FAULT STATUS_INPUT 7Ch CMP VIN UV FAULT STATUS_INPUT 7Ch STATUS_WORD 79h STATUS_BYTE 78h CMP CMP + IIN OC FAULT STATUS_INPUT 7Ch CIRCUIT BREAKER CMP IIN Circuit Breaker FAULT STATUS_MFR_SPECIFIC 80h MOSFET STATUS S/H MUX ADC FET Shorted FAULT STATUS_MFR_SPECIFIC 80h VIN_OV_WARN_LIMIT 57h DATA OUTPUT VIN_UV_WARN_LIMIT 58h CMP VIN_OV WARNING STATUS_INPUT 7Ch CMP VIN_UV WARNING STATUS_INPUT 7Ch CMP IIN_OC WARNING STATUS_INPUT 7Ch CMP PIN_OP WARNING STATUS_INPUT 7Ch CMP VOUT_UV WARNING STATUS_VOUT 7Ah CMP OT_WARNING_LIMIT STATUS_TEMPERATURE 7Dh SAMPLES_FOR_AVG DBh READ_VIN 88h READ_AVG_VIN DCh READ_IIN D1h READ_AVG_IIN DEh READ_PIN D2h READ_AVG_PIN DFh READ_VOUT 8Bh READ_AVG_VOUT DDh IIN_OC_WARN_LIMIT D3h PIN_OP_WARN_LIMIT D4h VOUT_UV_WARN_LIMIT 43h TEMPERATURE 8Dh VAUX D0h AVERAGED DATA FAULT SYSTEM OT_FAULT_LIMIT 57h CMP OT_WARNING_LIMIT 51h OT_FAULT_LIMIT STATUS_TEMPERATURE 7Dh STATUS_WORD 79h STATUS_BYTE 78h READ_PIN_PEAK D5h CLEAR_PIN_PEAK D6h PEAK-HOLD WARNING LIMITS WARNING SYSTEM PMBus Interface Figure 26. Command / Register and Alert Flow Diagram 38 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 8.5.4 Reading and Writing Telemetry Data and Warning Thresholds All measured telemetry data and user-programmed warning thresholds are communicated in 12-bit two’s complement binary numbers read or written in 2-byte increments conforming to the direct format as described in section 8.3.3 of the PMBus Power System Management Protocol Specification 1.1 (Part II). The organization of the bits in the telemetry or warning word is shown in Table 41, where Bit_11 is the most significant bit (MSB) and Bit_0 is the least significant bit (LSB). The decimal equivalent of all warning and telemetry words are constrained to be within the range of 0 to 4095, with the exception of temperature. The decimal equivalent value of the temperature word ranges from 0 to 65535. Table 41. Telemetry and Warning Word Format Byte B7 B6 B5 B4 B3 B2 B1 B0 1 Bit_7 Bit_6 Bit_5 Bit_4 Bit_3 Bit_2 Bit_1 Bit_0 2 0 0 0 0 Bit_11 Bit_10 Bit_9 Bit_8 Conversion from direct format to real-world dimensions of current, voltage, power, and temperature is accomplished by determining appropriate coefficients as described in section 7.2.1 of the PMBus Power System Management Protocol Specification 1.1 (Part II). According to this specification, the host system converts the values received into a reading of volts, amperes, watts, or other units using the following relationship: 1 x= Y ´ 10-R - b m ( ) where • • • • • X = The calculated real-world value (volts, amps, watt, and so forth) m = The slope coefficient Y = A 2-byte two's complement integer received from device b = The offset, a 2-byte two's complement integer R = The exponent, a 1-byte two's complement integer (2) R is only necessary in systems where m is required to be an integer (for example, where m may be stored in a register in an integrated circuit). In those cases, R only needs to be large enough to yield the desired accuracy. Table 42. Telemetry and Warning Conversion Coefficients Format Number of Data Bytes m b R Unit READ_VIN, READ_AVG_VIN VIN_OV_WARN_LIMIT VIN_UV_WARN_LIMIT Commands Condition DIRECT 2 4587 –1200 –2 V READ_VOUT, READ_AVG_VOUT VOUT_UV_WARN_LIMIT DIRECT 2 4587 -2400 –2 V READ_VAUX DIRECT 2 13793 0 –1 V READ_IIN, READ_AVG_IIN (1) MFR_IIN_OC_WARN_LIMIT CL = VDD DIRECT 2 10753 –1200 –2 A READ_IN, READ_AVG_IN (1) MFR_IIN_OC_WARN_LIMIT CL = GND DIRECT 2 5405 -600 –2 A CL = VDD DIRECT 2 1204 –6000 –3 W CL = GND DIRECT 2 605 –8000 –3 W DIRECT 2 16000 0 –3 °C READ_PIN, READ_AVG_PIN READ_PIN_PEAK MFR_PIN_OP_WARN_LIMIT (1) , READ_PIN, READ_AVG_PIN (1), READ_PIN_PEAK MFR_PIN_OP_WARN_LIMIT READ_TEMPERATURE_1 OT_WARN_LIMIT OT_FAULT_LIMIT (1) The coefficients relating to current/power measurements and warning thresholds shown are normalized to a sense resistor (RS) value of 1 mΩ. In general, the current or power coefficients can be calculated using the relationships shown in Table 43. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 39 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table 43. Current and Power Telemetry and Warning Conversion Coefficients (RS in mΩ) Condition Format Number of Data Bytes m b R Unit READ_IIN, READ_AVG_IIN (1) MFR_IIN_OC_WARN_LIMIT Commands CL = VDD DIRECT 2 10753 × RS –1200 –2 A READ_IIN, READ_AVG_IIN (1) MFR_IIN_OC_WARN_LIMIT CL = GND DIRECT 2 5405 × RS -600 –2 A READ_PIN, READ_AVG_PIN (1), READ_PIN_PEAK MFR_PIN_OP_WARN_LIMIT CL = VDD DIRECT 2 1204 × RS –6000 –3 W READ_PIN, READ_AVG_PIN (1), READ_PIN_PEAK MFR_PIN_OP_WARN_LIMIT CL = GND DIRECT 2 605 × RS –8000 –3 W (1) The coefficients relating to current/power measurements and warning thresholds shown are normalized to a sense resistor (RS) value of 1 mΩ. In general, the current or power coefficients can be calculated using the relationships shown in Table 43. Take care to adjust the exponent coefficient, R, such that the value of m remains within the range of –32768 to 32767. For example, if a 5-mΩ sense resistor is used, the correct coefficients for the READ_IIN command with CL = VDD would be m = 5359, b = –120, R = –1. 8.5.5 Determining Telemetry Coefficients Empirically With Linear Fit The coefficients for telemetry measurements and warning thresholds presented in Table 42 are adequate for the majority of applications. Current and power coefficients are dependent on RSNS and must be calculated per application. Table 43 provides the equations necessary for calculating the current and power coefficients for the general case. These were obtained by characterizing multiple units over temperature and are considered optimal. The small signal nature of the current and power measurement makes it more susceptible to PCB parasitics than other telemetry channels. In addition there is some variation in RSNS and the LM5066 itself. This may cause slight variations in the optimum coefficients (m, b, and R) for converting from digital values to real world values (for example, amps and watts). To maximize telemetry accuracy, the coefficients can be calibrated for a given board using empirical methods. This would determine optimum coefficients to cancel out the error from PCB parasitics, RSNS variation, and the variation of LM5066. It is not considered good practice to take measurements on one board and use the computed coefficients for all units in production, because the RSNS and the LM5066 on a given board are randomly chosen and do not represent a statistical mean. It is recommended to either calibrate all boards individually or to use the recommended coefficients from Table 43. The optimal current coefficients for a given board can be determined using the following method: 1. While the LM5066 is in normal operation, measure the voltage across the sense resistor using Kelvin test points and a high accuracy DVM while controlling the load current. Record the integer value returned by the READ_AVG_IIN command (with the SAMPLES_FOR_AVG set to a value greater than 0) for two or more voltages across the sense resistor. For best results, the individual READ_AVG_IIN measurements should span nearly the full-scale range of the current (for example, voltage across RSNS of 5 and 20 mV). 2. Convert the measured voltages to currents by dividing them by the value of RSNS. For best accuracy, the value of RSNS should be measured. Table 44 assumes a sense resistor value of 5 mΩ. Table 44. Measurements for Linear Fit Determination of Current Coefficients Measured Voltage Across RS (V) Measured Current (A) READ_AVG_IIN (Integer Value) 0.005 1 568 0.01 2 1108 0.02 4 2185 3. Using the spreadsheet (or a math program) determine the slope and the y-intercept of the data returned by the READ_AVG_IIN command versus the measured current. For the data shown in Table 42: – READ_AVG_IN value = slope × (Measured Current) + (y-intercept) – Slope = 538.9 – Y-intercept = 29.5 4. To determine the m coefficient, simply shift the decimal point of the calculated slope to arrive at integer with a suitable number of significant digits for accuracy (typically 4) while staying with the range of –32768 to 32767. This shift in the decimal point equates to the R coefficient. For the slope value shown in the previous 40 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 step, the decimal point would be shifted to the right once hence R = –1. 5. After the R coefficient has been determined, the b coefficient is found by multiplying the y-intercept by 10 In this case the value of b = 295. – Calculated current coefficients: – m = 5389 – b = 295 – R = –1 1 x= Y ´ 10-R - b m ( –R . ) where • • • • • X = The calculated real-world value (volts, amps, watts, temperature) m = The slope coefficient, is the 2-byte, two's complement integer Y = A 2-byte two's complement integer received from device b = The offset, a 2-byte two's complement integer R = The exponent, a 1-byte two's complement integer (3) This procedure can be repeated to determine the coefficients of any telemetry channel simply by substituting measured current for some other parameter (for example, power or voltage). 8.5.6 Writing Telemetry Data There are several locations that require writing data if their optional usage is desired. Use the same coefficients previously calculated for your application, and apply them using this method as prescribed by the PMBus revision section 7.2.2 Sending a Value Y = (mX + b )´ 10R where • • • • • X = The calculated real-world value (volts, amps, watts, temperature) m = The slope coefficient is the 2-byte, two's complement integer Y = A 2-byte two's complement integer received from device b = The offset, a 2-byte two's complement integer R = The exponent, a 1-byte two's complement integer (4) 8.5.7 PMBus Address Lines (ADR0, ADR1, ADR2) The three address lines are to be set high (connect to VDD), low (connect to GND), or open to select one of 27 addresses for communicating with the LM5066. Table 45 depicts 7-bit addresses (eighth bit is read/write bit). Table 45. Device Addressing ADR2 ADR1 ADR0 DECODED ADDRESS Z Z Z 40h Z Z 0 41h Z Z 1 42h Z 0 Z 43h Z 0 0 44h Z 0 1 45h Z 1 Z 46h Z 1 0 47h Z 1 1 10h 0 Z Z 11h 0 Z 0 12h 0 Z 1 13h 0 0 Z 14h Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 41 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Table 45. Device Addressing (continued) ADR2 ADR1 ADR0 DECODED ADDRESS 0 0 0 15h 0 0 1 16h 0 1 Z 17h 0 1 0 50h 0 1 1 51h 1 Z Z 52h 1 Z 0 53h 1 Z 1 54h 1 0 Z 55h 1 0 0 56h 1 0 1 57h 1 1 Z 58h 1 1 0 59h 1 1 1 5Ah 8.5.8 SMBA Response The SMBA effectively has two masks: • The alert mask register at D8h • The ARA automatic mask. The ARA automatic mask is a mask that is set in response to a successful ARA read. An ARA read operation returns the PMBus address of the lowest addressed part on the bus that has its SMBA asserted. A successful ARA read means that this part was the one that returned its address. When a part responds to the ARA read, it releases the SMBA signal. When the last part on the bus that has an SMBA set has successfully reported its address, the SMBA signal de-asserts. The way that the LM5066 releases the SMBA signal is by setting the ARA automatic mask bit for all fault conditions present at the time of the ARA read. All status registers will still the fault condition, but it does not generate a SMBA on that fault again until the ARA automatic mask is cleared by the host issuing a CLEAR_FAULTS command to this part. This should be done as a routine part of servicing an SMBA condition on a part, even if the ARA read is not done. Figure 27 depicts a schematic version of this flow. From other fault inputs SMBA Fault Condition Alert Mask D8h From PMBus Set ARA Operation Flag Succeeded ARA Auto Mask Clear Clear_Fault Command Received Figure 27. Typical Flow Schematic for SMBA Fault 42 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 9 Application and Implementation 9.1 Application Information The LM5066 is a hotswap with a PMBus interface that provides current, voltage, power, and status information to the host. As a hotswap, it is used to manage inrush current and protect in case of faults. When designing a hotswap, three key scenarios should be considered: • Start-up • Output of a hotswap is shorted to ground when the hotswap is on. This is often referred to as a hot-short. • Powering-up a board when the output and ground are shorted. This is usually called a start-into-short. All of these scenarios place a lot of stress on the hotswap MOSFET and take special care when designing the hotswap circuit to keep the MOSFET within its SOA. Detailed design examples are provided in the following sections. Solving all of the equations by hand is cumbersome and can result in errors. Instead, TI recommends to use the LM5066 Design Calculator provided on the product page. 9.2 Typical Application 9.2.1 48-V, 10-A PMBus Hotswap Design This section describes the design procedure for a 48-V, 10-A PMBUS hotswap design. Q2 VIN VOUT RSNS Q1 CIN D1 Z1 GATE SENSE R1 FB VIN Only required when using dv/dt start-up R5 OUT DIODE VIN_K R3 COUT D2 VDD R6 UVLO/EN 100 kŸ 1kŸ OVLO R2 R4 PGD LM5066 AGND ADR2 ADR1 ADR0 GND Cdv/dt VDD Q3 N/C N/C CL SMBus Interface SMBA SDAO SDAI SCL VDD 1 PF RETRY VAUX VREF 1 PF PWR Auxiliary ADC Input (0 to 2.97 V) TIMER RPWR CTIMER Figure 28. Typical Application Circuit 9.2.1.1 Design Requirements Table 46 summarizes the design parameters that must be known before designing a hotswap circuit. When charging the output capacitor through the hotswap MOSFET, the FET’s total energy dissipation equals the total energy stored in the output capacitor (1 / 2CV2). Thus, both the input voltage and output capacitance determine the stress experienced by the MOSFET. The maximum load current drives the current limit and sense resistor selection. In addition, the maximum load current, maximum ambient temperature, and thermal properties of the PCB (RθCA) drive the selection of the MOSFET RDSON and the number of MOSFETs used. RθCA is a strong function of the layout and the amount of copper that is connected to the drain of the MOSFET. Note that the drain is not electrically connected to the ground plane, and thus the ground plane cannot be used to help with heat dissipation. This design example uses RθCA = 30°C/W, which is similar to the LM5066 EVM. It is a good practice to measure the RθCA of a given design after the physical PCBs are available. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 43 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Typical Application (continued) Finally, it is important to understand what test conditions the hotswap needs to pass. In general, a hotswap is designed to pass both a hot-short and a start into a short, which are described in the previous section. Also, TI recommends to keep the load OFF until the hotswap is fully powered-up. Starting the load early causes unnecessary stress on the MOSFET and could lead to MOSFET failures or a failure to start-up. Table 46. Design Parameters PARAMETER EXAMPLE VALUE Input voltage range 40 to 60 V Maximum load current 10 A Maximum output capacitance of the hotswap 220 µF Maximum ambient temperature 85°C MOSFET RθCA (function of layout) 30°C/W Pass hot-short on output? Yes Pass a start into short? Yes Is the load off until PG asserted? Yes Can a hot board be plugged back in? Yes 9.2.1.2 Detailed Design-In Procedure 9.2.1.2.1 Select RSNS and CL Setting LM5066 can be used with a VCL of 26 or 50 mV. Using the 26-mV threshold results in a lower RSNS and lower I2R losses, but using the 50-mV threshold would result in better current and power monitoring accuracy along with a lower minimum power limit . The 26-mV option is selected for this design by connecting the CL pin directly to VDD. TI recommends to target a current limit that is at least 10% above the maximum load current to account for the tolerance of the LM5066 current limit. Targeting a current limit of 11 A, the sense resistor can be computed as follows: I 26mV RSNS,CLC = LIM = = 2.36mW VCL 11A (5) Typically, sense resistors are only available in discrete values. If a precise current limit is desired, a sense resistor along with a resistor divider can be used as shown in Figure 29. RSNS VIN_K R2 R1 SENSE Figure 29. SENSE Resistor Divider The next larger available sense resistor should be chosen (3 mΩ in this case). The ratio of R1 and R2 can be computed as follows: RSNS,CLC R1 2.36mW = = = 3.69 R2 RSNS - RSNS,CLC 3mW - 2.36mW (6) 44 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Note that the SENSE pin pulls 25 μA of current, which creates an offset across R2. TI recommends to keep R2 below 10 Ω to reduce the offset that this introduces. In addition, the 1% resistors add to the current monitoring error. Finally, if the resistor divider approach is used, the user should compute the effective sense resistance (RSNS,EFF) using Equation 7 and use that in all equations instead of RSNS. R ´ R1 RSNS,EFF = SNS R1 + R2 (7) Note that for many applications, a precise current limit may not be required. In that case, it is simpler to pick the next smaller available sense resistor. For this application, a 2-mΩ resistor can be used for a 13-A current limit. 9.2.1.2.2 Selecting the Hotswap FETs It is critical to select the correct MOSFET for a hotswap design. The device must meet the following requirements: • The VDS rating should be sufficient to handle the maximum system voltage along with any ringing caused by transients. For most 48-V systems, a 100-V FET is a good choice. • The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, and start into short. • RDSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of the FET. In fact, TI recommends to keep the steady-state FET temperature below 125°C to allow margin to handle transients. • Maximum continuous current rating should be above the maximum load current and the pulsed-drain current must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three requirements also pass these two. • A VGS rating of ±20 V is required because the LM5066 can pull up the gate as high as 16 V above source. For this design, the PSMN4R8-100BSE was selected for its low RDSON and superior SOA. After selecting the MOSFET, the maximum steady-state case temperature can be computed as follows: 2 TC,MAX = TA,MAX + RqCA ´ ILOAD,MAX ´ RDSON (TJ ) (8) Note that the RDSON is a strong function of junction temperature, which for most D2PACK MOSFETs is very close to the case temperature. A few iterations of the previous equations may be necessary to converge on the final RDSON and TC,MAX value. According to the PSMN4R8-100BSE data sheet, it's RDSON doubles at 110°C. Equation 9 uses this RDSON value to compute the TC,MAX. Note that the computed TC,MAX is close to the junction temperature assumed for RDSON. Thus, no further iterations are necessary. C 2 TC,MAX = 85°C + 30° ´ (10A ) ´ (2 ´ 4.8mW ) = 114°C (9) W 9.2.1.2.3 Select Power Limit In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the LM5066 is set to a very-low power limit setting, it has to regulate the FET current and hence the voltage across the sense resistor (VSNS) to a very-low value. VSNS can be computed as shown in Equation 10. P ´ RSNS VSNS = LIM VDS (10) To avoid significant degradation of the power limiting, TI does not recommend a VSNS of less than 4 mV. Based on this requirement, the minimum allowed power limit can be computed as follows: VSNS,MIN ´ VIN,MAX 4mV ´ 60V PLIM,MIN = = = 120W RSNS 2mW (11) In most applications, the power limit can be set to PLIM,MIN using Equation 12. Note that the PLIM of the LM5066 will have some variations vs VDS of the MOSFET due to a 1.5-mV systematic offset. Equation 12 sets RPWR to make the actual power limit equal the programmed power limit at VIN = VIN,MAX and VOUT = 0 V. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 45 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 5PWR www.ti.com 1.4 u 105 P9 u 9IN,MAX 5SNS u 5SNS u 3LIM ± W 1.4 u 105 u P: u :± P9 u 9 P: W N: (12) The closest available resistor should be selected. In this case, a 21-kΩ resistor was chosen. 9.2.1.2.4 Set Fault Timer The fault timer runs when the hotswap is in power limit or current limit, which is the case during start-up. Thus, the timer has to be sized large enough to prevent a time-out during start-up. If the part starts directly into current limit (ILIM × VDS < PLIM), the maximum start time can be computed with Equation 13. COUT ´ VIN,MAX t start,max = ILIM (13) For most designs (including this example), ILIM × VDS > PLIM, so the hotswap starts in power limit and transitions into current limit. In that case, the maximum start time can be computed as in Equation 14. t start,max = 2 COUT é VIN,MAX PLIM ù 220mF é (60V)2 120W ù ´ê + 2 ú= ´ê + ú = 3.38ms 2 2 2 êë PLIM ILIM úû ëê 120W (13A) ûú (14) Note that the above start-time is based on typical current limit and power limit values. To ensure that the timer never times out during start-up, TI recommends to set the fault time (tflt) to be 2 × tstart,max or 6.76 ms. This accounts for the variation in power limit, timer current, and timer capacitance. Thus, CTIMER can be computed as follows: t flt u itimer 6.76 ms u 75 PA CTIMER 130 nF v timer 3.9 V (15) The next largest standards capacitor value for CTIMER is chosen as 150 nF. After CTIMER is chosen, the actual programmed fault time can be computed as follows: CTIMER u v timer 150 nF u 3.9 V t flt 7.8 ms itimer 75 PA (16) 9.2.1.2.5 Check MOSFET SOA When the power limit and fault timer are chosen, it is critical to check that the FET stays within its SOA during all test conditions. During a hot-short the circuit breaker trips and the LM5066 restarts into power limit until the timer runs out. In the worst case, the MOSFET’s VDS equals VIN,MAX, IDS equals PLIM / VIN,MAX and the stress event lasts for tflt. For this design example, the MOSFET has 60 V, 2 A across it for 7.8 ms. Based on the SOA of the PSMN4R8-100BSE, it can handle 60 V, 30 A for 1 ms and it can handle 60 V, 6 A for 10 ms. For 7.8 ms, the SOA can be extrapolated by approximating SOA versus time as a power function as shown below: a u tm ISOA t m a § 30 A · ln ¨ ¸ © 6A ¹ § 1 ms · ln ¨ ¸ © 10 ms ¹ ln ISOA t1 / ISOA t 2 ln t1 / t 2 ISOA t1 t1m ISOA 7.8 ms 30 A (1 ms) 0.7 0.7 30 A u (ms)0.7 30 A u (ms)0.7 u (7.8 ms) 0.7 7.12 A (17) Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be much hotter during a hot-short. The SOA should be de-rated based on TC,MAX using Equation 18: 46 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 ISOA 7.8 ms, TC,MAX ISOA 7.8 ms, 25qC u TJ,ABSMAX TJ,ABSMAX TC,MAX 25qC 7.12 A u 175qC 114qC 175qC 25qC 2.85 A (18) Based on this calculation, the MOSFET can handle 2.85 A, 60 V for 7.8 ms at elevated case temperature, but is only required to handle 2 A during a hot-short. Thus, there is good margin and the design is robust. In general, TI recommends that the MOSFET can handle 1.3× more than what is required during a hot-short. This provides margin to account for the variance of the power limit and fault time. 9.2.1.2.6 Set UVLO and OVLO Thresholds By programming the UVLO and OVLO thresholds, the LM5066 enables the series-pass device (Q1) when the input supply voltage (VIN) is within the desired operational range. If VIN is below the UVLO threshold or above the OVLO threshold, Q1 is switched off, denying power to the load. Hysteresis is provided for each threshold. 9.2.1.2.6.1 Option A The configuration shown in Figure 30 requires three resistors (R1 to R3) to set the thresholds. VIN VIN 20 PA R1 UVLO/EN 2.48 V R2 2.46 V TIMER AND GATE LOGIC CONTROL OVLO R3 GND 21 PA Figure 30. UVLO And OVLO Thresholds Set By R1-R3 The procedure to calculate the resistor values is as follows: • Choose the upper UVLO threshold (VUVH) and the lower UVLO threshold (VUVL). • Choose the upper OVLO threshold (VOVH). • The lower OVLO threshold (VOVL) cannot be chosen in advance in this case, but is determined after the values for R1 to R3 are determined. If VOVL must be accurately defined in addition to the other three thresholds, see Option B. The resistors are calculated as follows: - VUVL VUV(HYS) V = R1 = UVH 20mA 20mA (19) R3 = R1´ VUVL ´ 2.46V VOVH ´ (VUVL - 2.48V ) (20) 2.48V ´ R1 R2 = - R3 VUVL - 2.48V (21) The lower OVLO threshold is calculated from: é æ æ 2.46V ö öù VOVL = ê(R1 + R2 )´ ç ç - 21 mA ÷ ú + 2.46V ÷ è è R3 ø ø ûú ëê (22) When the R1 to R3 resistor values are known, the threshold voltages and hysteresis are calculated from the following: æ 2.48V ö VUVH = 2.48V + R1´ ç + 20 mA ÷ R2 R3 + è ø (23) VUVL = 2.48V ´ (R1 + R2 + R3 ) R2 + R3 (24) Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 47 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com VUV(HYS) = R1´ 20 mA VOVH = VOVL (25) 2.46V ´ (R1 + R2 + R3 ) R3 æ 2.46V ö =ç - 21 mA ÷ ´ (R1 + R2 ) + 2.46V è R3 ø (26) (27) VOV(HYS) = (R1 + R2 )´ 21 mA (28) 9.2.1.2.6.2 Option B If all four thresholds must be accurately defined, the configuration in Figure 31 can be used. VIN VIN 20 PA R1 UVLO/EN 2.48 V R2 R3 OVLO 2.46 V TIMER AND GATE LOGIC CONTROL R4 GND 21 PA Figure 31. Programming the Four Thresholds The four resistor values are calculated as follows: • Choose the upper and lower UVLO thresholds (VUVH) and (VUVL). - VUVL VUV(HYS) V = R1 = UVH 20 mA 20 mA 2.48V ´ R1 R2 = VUVL - 2.48V • • (30) Choose the upper and lower OVLO threshold (VOVH) and (VOVL). V - VOVL R3 = OVH 21 mA R4 = 2.46V ´ R3 V ( OVH - 2.46V ) (31) (32) When the R1 to R4 resistor values are known, the threshold voltages and hysteresis are calculated from the following: é æ 2.48V öù VUVH = 2.48V + êR1´ ç + 20 mA ÷ ú è R2 øû ë (33) VUVL = 2.48V ´ (R1 + R2 ) R2 VUV(HYS) = R1´ 20 mA VOVH = VOVL 48 (29) (34) (35) 2.46V ´ (R3 + R4 ) R4 é æ 2.46V öù = 2.46V + êR3 ´ ç - 21 mA ÷ ú è R4 øû ë Submit Documentation Feedback (36) (37) Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 9.2.1.2.6.3 Option C The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 32. Q1 is switched on when the VIN voltage reaches the POREN threshold (≊8.6 V). The OVLO thresholds are set using R3, R4. Their values are calculated using the procedure in Option B. VIN VIN 20 PA 10 k UVLO/EN 2.48 V R3 2.46 V R4 TIMER AND GATE LOGIC CONTROL OVLO GND 21 PA Figure 32. UVLO = POREN 9.2.1.2.6.4 Option D The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as described in Option B or Option C. For this design example, option B was used and the following options were targeted: VUVH = 38 V, VUVL = 35 V, VOVH = 65 V, and VOVL = 63 V. The VUVH and VOVL were chosen to be 5% below or above the input voltage range of 40 to 60 V to allow for some tolerance in the thresholds of the part. R1, R2, R3, and R4 are computed using the following equations: - VUVL 38 V - 35 V V = = 150kW R1 = UVH 20µA 20µA 2.48 V ´ R1 2.48 V ´ 150kW = = 11.44kW R2 = V 2.48 V ( UVL ) (35V - 2.48 V ) VOVH - VOVL 65 V - 63 V = = 95.24kW 21µA 21µA 2.46 V ´ R3 2.46 V ´ 95.24kW = = 3.75kW R4 = (VOVH - 2.46 V ) (65V - 2.46 V ) R3 = (38) Nearest available 1% resistors should be chosen. Set R1 = 150 kΩ, R2 = 11.5 kΩ, R3 = 95.3 kΩ, and R4 = 3.74 kΩ. 9.2.1.2.7 Power Good Pin The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of sustaining 80 V in the off-state and transients up to 100 V. An external pullup resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 49 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com When the voltage at the FB pin increases above its threshold, the internal pulldown acting on the PGD pin is disabled allowing PGD to rise to VPGD through the pullup resistor, RPG, as shown in Figure 34. The pullup voltage (VPGD) can be as high as 80 V, and can be higher or lower than the voltages at VIN and OUT. VDD is a convenient choice for VPGD as it allows interface to low voltage logic and avoids glitching on PGD during powerup. If a delay is required at PGD, suggested circuits are shown in Figure 35. In Figure 35(A), capacitor CPG adds delay to the rising edge, but not to the falling edge. In Figure 35(B), the rising edge is delayed by RPG1 + RPG2 and CPG, while the falling edge is delayed a lesser amount by RPG2 and CPG. Adding a diode across RPG2 (Figure 35(C)) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge. Q1 VPGD VOUT OUT GATE RPG R5 2.46 V PGD FB Power Good R6 GND 20 PA PGD UV OV GND Figure 33. Programming the PGD Threshold VPGD Figure 34. Power Good Output VPGD VPGD RPG1 RPG1 RPG1 PGD PGD Power Good RPG2 RPG2 CPG CPG GND GND A) Delay at Rising Edge Only PGD Power Good B) Long Delay at Rising Edge, Short Delay at Falling Edge Power Good CPG GND C) Short Delay at Rising Edge and Long Delay at Falling Edge or Equal Delays Figure 35. Adding Delay to the Power Good Output Pin TI recommends to set the PG threshold 5% below the minimum input voltage to ensure that the PG is asserted under all input voltage conditions. For this example, PGDH of 38 V and PGDL of 35 V is targeted. R5 and R6 are computed using the following equations: V - VPGDL 38 V - 35 V R5 = PGDH = = 150kW 20µA 20µA (39) R6 = 2.46 V ´ R5 2.46 V ´ 150kW = = 10.38kW (VPGDH - 2.46 V ) (38V - 2.46 V ) (40) Nearest available 1% resistors should be chosen. Set R5 = 150 kΩ and R6 = 10.5 kΩ. 9.2.1.2.8 Input and Output Protection Proper operation of the LM5066 hot swap circuit requires a voltage clamping element present on the supply side of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in . The TVS is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current. This effect is the most severe during a hot-short when a large current is suddenly interrupted when the FET shutts off. The TVS should be chosen to have minimal leakage current at VIN,MAX and to clamp the voltage to under 100V during hot-short events. For many high power applications 5.0SMDJ60A is a good choice. 50 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 If the load powered by the LM5066 hot swap circuit has inductive characteristics, a Schottky diode is required across the LM5066’s output, along with some load capacitance. The capacitance and the diode are necessary to limit the negative excursion at the OUT pin when the load current is shut off. RSNS VIN Q1 +48 V LIVE POWER SOURCE VIN VIN_K SENSE VOUT OUT D1 CL Inductive Load LM5066 Z1 AGND GND GND PLUG-IN BOARD Figure 36. Output Diode Required for Inductive Loads 9.2.1.2.9 Final Schematic and Component Values Figure 28 shows the schematic used to implement the requirements described in the previous section. In addition, Table 47 provides the final component values that were used to meet the design requirements for a 48V, 10-A hotswap design. The application curves in the next section are based on these component values. Table 47. Final Component Values (48-V, 10-A Design) COMPONENT VALUE RSNS 2 mΩ R1 150 kΩ R2 11.5 kΩ R3 95.3 kΩ R4 3.74 kΩ R5 150 kΩ R6 10.5 kΩ RPWR 21 kΩ Q1 PSMN4R8-100BSEJ Q2 MMBT3904 D1 B380-13-F Z1 5.0SMDJ60A CTIMER 150 nF Optional dv/dt circuit DNP Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 51 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 9.2.1.3 Application Curves VIN = 48V Figure 37. Insertion Delay Figure 38. Start-Up VIN = 40V 52 VIN = 60V Figure 39. Start-Up Figure 40. Start-Up Figure 41. Start-Up into Short Circuit Figure 42. Under-Voltage Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 Figure 43. Over-Voltage Figure 44. Gradual Over-Current Figure 45. Loadstep Figure 46. Hotshort on Output (Zoomed Out) Figure 47. Hotshort on Output (Zoomed In) Figure 48. Auto-retry Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 53 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com 10 Power Supply Recommendations In general, the LM5066 behavior is more reliable if it is supplied from a very regulated power supply. However, high-frequency transients on a backplane are not uncommon due to adjacent card insertions or faults. If this is expected in the end system, TI recommends to place a 1-µF ceramic capacitor to ground close to the source of the hotswap MOSFET. This reduces the common mode seen by VIN_K and SENSE. Additional filtering may be necessary to avoid nuisance trips. 54 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 11 Layout 11.1 Layout Guidelines The following guidelines should be followed when designing the PC board for the LM5066: 1. Place the LM5066 close to the board’s input connector to minimize trace inductance from the connector to the MOSFET. 2. Place a TVS, Z1, directly adjacent to the VIN and GND pins of the LM5066 to help minimize voltage transients which may occur on the input supply line. The TVS should be chosen such that the peak VIN is just lower the TVS reverse-bias voltage. Transients of 20 V or greater over the nominal input voltage can easily occur when the load current is shut off. A small capacitor may be sufficient for low current sense applications (I < 2 A). TI recommends to test the VIN input voltage transient performance of the circuit by current limiting or shorting the load and measuring the peak input voltage transient. 3. Place a 1-µF ceramic capacitor as close as possible to VREF pin. 4. Place a 1-µF ceramic capacitor as close as possible to VDD pin. 5. The sense resistor (RSNS) should be placed close to the LM5066. A trace should connect the VIN pad and Q1 pad of the sense resistor to VIN_K and SENSE pins, respectively. Connect RSNS using the Kelvin techniques as shown in Figure 50. 6. The high current path from the board’s input to the load (through Q1), and the return path, should be parallel and close to each other to minimize loop inductance. 7. The AGND and GND connections should be connected at the pins of the device. The ground connections for the various components around the LM5066 should be connected directly to each other, and to the LM5066’s GND and AGND pin connection, and then connected to the system ground at one point. Do not connect the various component grounds to each other through the high current ground line. 8. Provide adequate thermal sinking for the series pass device (Q1) to help reduce stresses during turn-on and turn-off. 9. The board’s edge connector can be designed such that the LM5066 detects through the UVLO/EN pin that the board is being removed, and responds by turning off the load before the supply voltage is disconnected. For example, in , the voltage at the UVLO/EN pin goes to ground before VIN is removed from the LM5066 as a result of the shorter edge connector pin. When the board is inserted into the edge connector, the system voltage is applied to the LM5066’s VIN pin before the UVLO voltage is taken high, thereby allowing the LM5066 to turn on the output in a controlled fashion. 11.2 Layout Example GND VIN To Load RS Q1 Z1/C1 R1 R2 R3 OUT GATE SENSE VIN_K VIN UVLO/EN OVLO AGND GND SDAI SDAO SCL SMBA PGD PWR TIMER RETRY FB CL VDD ADR0 ADR1 ADR2 VAUX DIODE VREF LM5066 CARD EDGE CONNECTOR MMBT3904 PLUG-IN CARD Figure 49. Recommended Board Connector Design Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 55 LM5066 SNVS655I – JUNE 2011 – REVISED JANUARY 2016 www.ti.com Layout Example (continued) HIGH CURRENT PATH FROM SYSTEM INPUT VOLTAGE TO DRAIN OF SENSE RESISTOR MOSFET Q1 RS VIN VIN_K SENSE Figure 50. Sense Resistor Connections 56 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 LM5066 www.ti.com SNVS655I – JUNE 2011 – REVISED JANUARY 2016 12 Device and Documentation Support 12.1 Trademarks PMBus is a trademark of SMIF, Inc. 12.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Product Folder Links: LM5066 57 PACKAGE OPTION ADDENDUM www.ti.com 5-Jan-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM5066PMH/NOPB ACTIVE HTSSOP PWP 28 48 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM5066PMH LM5066PMHE/NOPB ACTIVE HTSSOP PWP 28 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM5066PMH LM5066PMHX/NOPB ACTIVE HTSSOP PWP 28 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 LM5066PMH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 5-Jan-2016 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM5066PMHE/NOPB HTSSOP PWP 28 250 178.0 16.4 LM5066PMHX/NOPB HTSSOP PWP 28 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.8 10.2 1.6 8.0 16.0 Q1 6.8 10.2 1.6 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jan-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5066PMHE/NOPB HTSSOP PWP LM5066PMHX/NOPB HTSSOP PWP 28 250 213.0 191.0 55.0 28 2500 367.0 367.0 38.0 Pack Materials-Page 2 PACKAGE OUTLINE PWP0028A PowerPAD TM - 1.1 mm max height SCALE 1.800 PLASTIC SMALL OUTLINE C 6.6 TYP 6.2 A SEATING PLANE PIN 1 ID AREA 28 1 9.8 9.6 NOTE 3 0.1 C 26X 0.65 2X 8.45 14 B 15 4.5 4.3 NOTE 4 0.30 0.19 0.1 C A 28X 1.1 MAX B 0.20 TYP 0.09 SEE DETAIL A 3.15 2.75 0.25 GAGE PLANE 5.65 5.25 THERMAL PAD 0 -8 0.10 0.02 0.7 0.5 (1) DETAIL A TYPICAL 4214870/A 10/2014 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MO-153, variation AET. www.ti.com EXAMPLE BOARD LAYOUT PWP0028A PowerPAD TM - 1.1 mm max height PLASTIC SMALL OUTLINE (3.4) NOTE 9 (3) SOLDER MASK OPENING 28X (1.5) 28X (0.45) SOLDER MASK DEFINED PAD 1 28X (0.45) 28X (1.3) 28 26X (0.65) SYMM (5.5) (9.7) SOLDER MASK OPENING (1.3) TYP 14 15 ( 0.2) TYP VIA (1.3) SEE DETAILS SYMM (0.9) TYP METAL COVERED BY SOLDER MASK (0.65) TYP (5.8) (6.1) HV / ISOLATION OPTION 0.9 CLEARANCE CREEPAGE OTHER DIMENSIONS IDENTICAL TO IPC-7351 IPC-7351 NOMINAL 0.65 CLEARANCE CREEPAGE LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214870/A 10/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. www.ti.com EXAMPLE STENCIL DESIGN PWP0028A PowerPAD TM - 1.1 mm max height PLASTIC SMALL OUTLINE (3) BASED ON 0.127 THICK STENCIL 28X (1.5) 28X (0.45) METAL COVERED BY SOLDER MASK 1 28X (1.3) 28 26X (0.65) 28X (0.45) (5.5) BASED ON 0.127 THICK STENCIL SYMM 14 15 SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SYMM (5.8) (6.1) HV / ISOLATION OPTION 0.9 CLEARANCE CREEPAGE OTHER DIMENSIONS IDENTICAL TO IPC-7351 IPC-7351 NOMINAL 0.65 CLEARANCE CREEPAGE SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE AREA SCALE:6X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.127 0.152 0.178 3.55 X 6.37 3.0 X 5.5 (SHOWN) 2.88 X 5.16 2.66 X 4.77 4214870/A 10/2014 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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