NCP5183, NCV5183
High Voltage High Current
High and Low Side Driver
The NCP5183 is a High Voltage High Current Power MOSFET
Driver providing two outputs for direct drive of 2 N−channel power
MOSFETs arranged in a half−bridge (or any other high−side +
low−side) configuration.
It uses the bootstrap technique to insure a proper drive of the
High−side power switch. The driver works with 2 independent inputs
to accommodate any topology (including half−bridge, asymmetrical
half−bridge, active clamp and full−bridge…).
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8
1
SOIC−8 NB
CASE 751−07
Features
•
•
•
•
•
•
•
•
•
Automotive Qualified to AEC Q100
Voltage Range: up to 600 V
dV/dt Immunity ±50 V/ns
Gate Drive Supply Range from 9 V to 18 V
Output Source / Sink Current Capability 4.3 A / 4.3 A
3.3 V and 5 V Input Logic Compatible
Extended Allowable Negative Bridge Pin Voltage Swing to –10 V
♦ Matched Propagation Delays between Both Channels
♦ Propagation Delay 120 ns typically
♦ Under VCC LockOut (UVLO) for Both Channels
Pin to Pin Compatible with Industry Standards
These are Pb−free Devices
Typical Application
•
•
•
•
•
•
•
MARKING DIAGRAM
8
NCx5183
ALYW G
G
1
x
A
L
Y
W
G
= P or V
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Power Supplies for Telecom and Datacom
Half−Bridge and Full−Bridge Converters
Push−Pull Converters
High Voltage Synchronous−Buck Converters
Motor Controls
Electric Power Steering
Class−D Audio Amplifiers
PIN CONNECTIONS
HIN
VB
LIN
DRVH
GND
HB
DRVL
VCC
ORDERING INFORMATION
Package
Shipping†
NCP5183DR2G
SOIC−8
(Pb−Free)
2500 / Tape
& Reel
NCV5183DR2G
SOIC−8
(Pb−Free)
2500 / Tape
& Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
December, 2017 − Rev. 1
1
Publication Order Number:
NCP5183/D
NCP5183, NCV5183
V HV
Vcc
M1
RBOOT
DBOOT
1
HIN
VB
8
2
LIN
DRVH
7
3
GND
HB
6
4
DRVL
VCC
5
CONTROLLER
CBOOT
LOAD
M2
CVcc
Figure 1. Application Schematic
VCC
VB
UV
Detect
Pulse
Trigger
HIN
Level
Shifter
S
Q
R
Q
DRVH
UV
Detect
HB
V CC
DELAY
LIN
GND
Figure 2. Simplified Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin No. (SOIC8)
Pin Name
Description
1
HIN
High Side Logic Input
2
LIN
Low Side Logic Input
3
GND
Ground
4
DRVL
Low Side Gate Drive Output
5
VCC
Main Power Supply
6
HB
Bootstrap Return or High Side Floating Supply Return
7
DRVH
8
VB
High Side Gate Drive Output
Bootstrap Power Supply
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2
DRVL
NCP5183, NCV5183
Table 2. ABSOLUTE MAXIMUM RATINGS
All voltages are referenced to GND pin
Symbol
Value
Units
VCC
−0.3 to 18
V
VLIN, VHIN
−0.3 to 18
V
High Side Boot pin Voltage
VB
(higher of {−0.3 ; VCC – 1.5}) to 618
V
High Side Bridge pin Voltage
VHB
VB − 18 to VB + 0.3
V
Rating
Input Voltage Range
Input Voltage on LIN and HIN pins
High Side Floating Voltage
VB – VHB
−0.3 to 18
V
High Side Output Voltage
VDRVH
VHB – 0.3 to VB + 0.3
V
Low Side Output Voltage
VDRVL
−0.3 to VCC + 0.3
V
Allowable output slew rate
dVHB/dt
50
V/ns
Maximum Operating Junction Temperature
TJ(max)
150
°C
Storage Temperature Range
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 1)
ESDHBM
3
kV
ESD Capability, Charged Device Model (Note 1)
ESDCDM
1
kV
TSLD
260
°C
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 2)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−11 (EIA/JESD22−C101E)
Latchup Current Maximum Rating: ≤ 150 mA per JEDEC standard: JESD78
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 3. THERMAL CHARACTERISTICS
Rating
Thermal Characteristics SO8 (Note 3)
Thermal Resistance, Junction−to−Air (Note 4)
Symbol
Value
RqJA
183
Units
°C/W
3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
4. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.
Table 4. RECOMMENDED OPERATING CONDITIONS (Note 5)
All voltages are referenced to GND pin
Rating
Symbol
Min
Max
Units
Input Voltage Range
VCC
10
17
V
VB – VHB
10
17
V
VHB
−1
580
V
High Side Output Voltage
VDRVH
VHB
VB
V
Low Side Output Voltage
VDRVL
GND
VCC
V
VLIN, VHIN
GND
VCC − 2
V
TJ
−40
125
°C
High Side Floating Voltage
High Side Bridge pin Voltage
Input Voltage on LIN and HIN pins
Operating Junction Temperature Range
5. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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NCP5183, NCV5183
Table 5. ELECTRICAL CHARACTERISTICS
−40°C ≤ TJ ≤ 125°C, VCC = VB = 15 V, VHB = GND, outputs are not loaded, all voltages are referenced to GND; unless otherwise noted.
Typical values are at TJ = +25°C. (Notes 6, 7)
Test Conditions
Parameter
Symbol
Min
Typ
Max
Units
VCCon
7.8
8.8
9.8
V
VCCoff
7.2
8.3
9.1
V
Supply Section
VCC UVLO
VCC rising
VCC falling
VCC hysteresis
VB UVLO
VCChyst
0.5
V
VB rising
VBon
7.8
8.8
9.8
V
VB falling
VBoff
7.2
8.3
9.1
V
VB hysteresis
VBhyst
0.5
V
ICC1
520
700
mA
VCC pin operating current
f = 20 kHz, CL = 1 nF
VB pin operating current
f = 20 kHz, CL = 1 nF
IB1
700
800
mA
VCC pin quiescent current
VLIN = VHIN = 0 V
ICC2
95
160
mA
VB pin quiescent current
VLIN = VHIN = 0 V
IB2
65
100
mA
VB to GND quiescent current
VB = VHB = 600 V
IHSleak
50
mA
Input Section
VINH
Logic High Input Voltage
Logic Low Input Voltage
2.5
V
VINL
25
1.2
V
50
mA
1
mA
Logic High Input Current
VxIN = 5 V
IxIN+
Logic Low Input Current
VxIN = 0 V
IxIN−
Input Pull Down Resistance
VxIN = 5 V
RxIN
Low Level Output Voltage
IDRVL = 0 A
VDRVLL
35
mV
Low Level Output Voltage (HS Driver)
IDRVH = 0 A
VDRVHL
35
mV
High Level Output Voltage
IDRVL = 0 A, VDRVLH = VCC − VDRVL
VDRVLH
35
mV
High Level Output Voltage (HS Driver)
IDRVH = 0 A, VDRVHH = VB – VDRVH
VDRVHH
35
mV
Output Positive Peak current
VDRVL = 0 V, PW = 10 ms
IDRVLH
4.3
A
Output Negative Peak current
VDRVL = 15 V, PW = 10 ms
IDRVLL
4.3
A
Output Positive Peak current (HS Driver)
VDRVH = 0 V, PW = 10 ms
IDRVHH
4.3
A
Output Negative Peak current (HS Driver)
VDRVH = 15 V, PW = 10 ms
100
250
kW
Output Section
IDRVHL
4.3
A
Output Resistance
ROH
1.7
W
Output Resistance
ROL
1.1
W
Turn On Propagation Delay
tON
120
200
ns
Turn Off Propagation Delay
tOFF
120
200
ns
tMT
0
Dynamic Section
Delay Matching
Pulse width = 1 ms
50
ns
Minimum Positive Pulse Width
VxIN = 0 V to 5 V
tminH
150
ns
Minimum Negative Pulse Width
VxIN = 5 V to 0 V
tminL
100
ns
6. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible
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NCP5183, NCV5183
Table 5. ELECTRICAL CHARACTERISTICS
−40°C ≤ TJ ≤ 125°C, VCC = VB = 15 V, VHB = GND, outputs are not loaded, all voltages are referenced to GND; unless otherwise noted.
Typical values are at TJ = +25°C. (Notes 6, 7)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Units
tr
12
40
ns
tf
12
40
ns
VHBneg
−8
−7
V
Switching Parameters
Output Voltage Rise Time
10% to 90%, CL = 1 nF
Output Voltage Fall Time
90% to 10%, CL = 1 nF
Negative HB pin Voltage
PW ≤ tON, VCC = VB = 10 V
6. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible
50%
LIN, HIN
90%
10%
DRVL, DRVH
t ON
tOFF
tr
tf
Figure 3. Propagation Delay, Rise Time and Fall Time Timing
HIN (LIN)
HIN, LIN
LIN (HIN)
90%
DRVx
90%
DRVx
10%
10%
90%
90%
DRVx
DRVx
10%
t MT
t MT
t MT
t MT
10%
t MT
Figure 4. Delay Matching
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5
t MT
t MT
t MT
NCP5183, NCV5183
Figure 5. VCCon vs. Temperature
Figure 6. VCCoff vs. Temperature
Figure 7. VCCUVLOHYS vs. Temperature
Figure 8. VBon vs. Temperature
Figure 9. VBoff vs. Temperature
Figure 10. VBhyst vs. Temperature
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NCP5183, NCV5183
Figure 11. ICC1 vs. Temperature
Figure 12. ICC2 vs. Temperature
Figure 13. IB1 vs. Temperature
Figure 14. IB2 vs. Temperature
Figure 15. IHSleak vs. Temperature
Figure 16. RIN vs. Temperature
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NCP5183, NCV5183
Figure 18. tOFF vs. Temperature
Figure 17. tON vs. Temperature
Figure 19. tr vs. Temperature
Figure 20. tf vs. Temperature
Figure 21. tr for 10 nF Load vs. Temperature
Figure 22. tf for 10 nF Load vs. Temperature
Figure 23. ROH vs. Temperature
Figure 24. ROL vs. Temperature
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NCP5183, NCV5183
Figure 25. tMT vs. Temperature
Figure 26. ICC and IB Current Consumption vs.
Frequency
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NCP5183, NCV5183
MOSFET Turn On and Turn Off Current Path
and after a short dead time Qsink is turned on. Then CVCC
(Cboot) is not a source any more, the source of energy
became the CGS (and all capacitance connected to this
terminal, like Muller capacitance). Now the current flows
from gate terminal, through Rg resistor and Qsink back to the
MOSFET (depictured by blue line). In both cases (charging
and discharging external MOSFET) there are several
parasitic inductances in the path. All of them play a role
during switching. In Figure 27 an influence of the
inductances in some places is showed. On VCC (VB) pin a
drop during turn on and turn off is observed. If too long an
UVLO protection can be triggered and the driver can be
turned off subsequently, which result in improper operation
of the application.
A capacitor connected from VCC (VB) to GND (HB)
terminal is source of energy for charging the gate terminal
of an external MOSFET(s). For better understanding of this
process see Figure 27 (all voltages are related to GND (HB)
pin). When there is a request from internal logic to turn on
the external MOSFET, then the Qsource is turned on. The
current starts to flow from CVCC (Cboot), through Qsource,
gate resistor Rg to the gate terminal of the external MOSFET
(depictured by red line). The current loop is closed from
external MOSFET source terminal back to the CVCC (Cboot)
capacitor. After a while the CGS capacitance is fully charged
so no current flows this path. When the external MOSFET
going to be turned off, the internal Qsource is turned off first
turn on
turn off
Voltage probes
NCP5183
Ltrace
Lbond
Qsource
VCC(VB)
turn on
turn off
turn on
Iturn on
RDSon
RDSon
MOSFET
CVCC(Cboot)
turn off
CGD
Ltrace
Lbond
Rg
DRVL(DRVH)
turn on
turn off
CGS
Iturn off
Ltrace
Qsink
Lbond
Ltrace
GND(HB)
All voltages are refered to GND (HB) pin
Figure 27. Equivalent Circuit of Power Switch Driver
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NCP5183, NCV5183
Layout Recommendation
The NCP5183 is high speed, high current (sink/source
4.3 A/4.3 A) driver suitable for high power application. To
avoid any damage and/or malfunction during switching
(and/or during transients, overloads, shorts etc.) it is very
important to avoid a high parasitic inductances in high
current paths (see “MOSFET turn on and turn off current
path” section). It is recommended to fulfill some rules in
layout. One of a possible layout for the IC is depictured in
Figure 28.
• Keep loop HB_pin – GND_pin – Q_LO as small as
possible. This loop (parasitic inductance) has potential
to increase negative spike on HB pin which can cause
of malfunction or damage of HB driver. The negative
voltage presented on HB pin is added to VCC−Vf
voltage so VCboot is increased. In extreme case the
Cboot voltage can be so high it will reach maximum
rating value which can lead to device damage.
• Keep loop VDD_pin – GND_pin – CVCC as small as
possible. The IC featured high current capability driver.
•
•
•
Any parasitic inductance in this path will result in slow
Q_LO turn on and voltage drop on VCC pin which can
result in UVLO activation.
Keep loop VB_pin – HB_pin – Cboot as small as
possible. The IC featured high current capability driver.
Any parasitic inductance in this path will result in slow
Q_HI turn on and voltage drop on VB pin which can
result in UVLO activation.
Do not let high current flow through trace between
GND_pin and CVCC even a small parasitic inductance
here will create high voltage drop if high current flows
through this path. This voltage is added or subtracted
from HIN and LIN signal, which results in incorrect
thresholds or device damaging.
Keep loops DRVL_pin – Q_LO – GND_pin and
DRVH_pin – Q_HI – HB_pin as small as possible. A
high parasitic inductance in these paths will result in
slow MOSFET switching and undesired resonance on
gate terminal.
Figure 28. Recommended Layout
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11
NCP5183, NCV5183
Cboot Capacitor Value Calculation
favorable. Under the hard switch conditions the energy to
charge Qg (from zero voltage to Vth of the MOSFET) is
taken from VCC capacitor (through an external boot strap
diode) so the voltage drop on Cboot is smaller. For the
calculation of Cboot value the ZVS conditions are taken
account.
The switching cycle is divided into two parts, the charging
(tcharge) and the discharging (tdischarge) of the Cboot
capacitor. The discharging can be divided even more to
discharging by floating driver current consumption IB2
(tdsIb) and to discharging by transfering energy from Cboot
to gate terminal of the MOSFET (tdsQm). Discharging by IB2
becoming more dominant when driver runs at lower
frequencies and/or during skip mode operation. To calculate
Cboot value, follow these steps:
The device featured two independent 4.3 A sink and
source drivers. The low side driver (DRVL) supplies a
MOSFET whose source is connected to ground. The driver
is powered from VCC line. The high side driver (DRVH)
supplies a MOSFET whose source is floating from GND to
bulk voltage. The floating driver is powered from Cboot
capacitor. The capacitor is charged only when HB pin is
pulled to GND (by inductance or the low side MOSFET
when turned on). If too small Cboot capacitor is used the high
side UVLO protection can disable the high side driver which
leads to improper switching.
Expected voltage on Cboot is depictured in Figure 29. The
curves are valid for ZVS (Zero Voltage Switching) observed
in LLC applications. For hard switch the curves are slightly
different, but from charge on Cboot point of view more
Figure 29. Boot Strap Capacitor Charging Principle
(81 mA typ) for 5 ms, so the charge consumed by
floating driver is:
1. For example, let’s have a MOSFET with
Qg = 30 nC, VDD = 15 V.
2. Charge stored in Cboot necessary to cover the
period the Cboot is not supplied from VCC line
(which is basically the period the high side
MOSFET is turned on). Let’s say the application is
switching at 100 kHz, 50% duty cycle, which
means the upper MOSFET is conductive for 5 ms.
It means the Cboot is discharged by IB2 current
Q b + I B2 @ t discharge + 81m @ 5m + 405 pC
(eq. 1)
3. Total charge loss during one switching cycle is
sum of charge to supply the high side driver and
MOSFET’s gate charge:
Q tot + Q g ) Q b + 30n ) 405p + 30.4 nC
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12
(eq. 2)
NCP5183, NCV5183
4. Let’s determine acceptable voltage ripple on Cboot
to 1% of nominal value, which is 150 mV. To
cover charge losses from eq. 2
C boot +
Q tot
+ 30.4n + 203 nF
0.15
V ripple
Rboot value can be recalculated to eliminate this additional
drop.
The resistor Rboot calculated in eq. 4 is valid under steady
state conditions. During start and/or skip operation the
starting point voltage value is different (lower) and it takes
more time to charge the boot strap capacitor. More over it is
not counted with temperature and voltage variability during
normal operation or the dynamic resistance of the boot strap
diode (approximately 0.34 W for MURA160). From these
reasons the resistor value should be decreased especially
with respect to skip operation.
Boot strap resistor losses calculation.
(eq. 3)
It is recommended to increase the value as consumption
and gate charge are temperature and voltage dependent, so
let’s choose a capacitor 330 nF in this case.
Rboot Resistor Value Calculation
To keep the application running properly, it is necessary
to charge the Cboot again. This is done by external diode
from VCC line to VB pin. In serial with the diode a resistor
is placed to reduce the current peaks from VCC line. The
resistor value selection is critical for proper function of the
high side driver. If too small high current peaks are drown
from VCC line, if too high the capacitor will not be charged
to appropriate level and the high side driver can be disabled
by internal UVLO protection.
First of all keep in mind the capacitor is charged through
the external boot strap diode, so it can be charged to a
maximum voltage level of VCC – Vf. The resistor value is
calculated using this equation:
R boot +
t charge
ǒ
C boot @ ln
V max*V
V max*V
Cmin
Cmax
Ǔ
+
5m
14.4*14.2 Ǔ
330n @ lnǒ14.4*14.35
^ 11 W
P Rboot ^ Q tot @ V Cmax @ f + 30.4n @ 14.4 @ 100k ^ 44 mW
(eq. 6)
Boot strap diode losses calculation.
P Dboot ^ Q tot @ V f @ f + 30.4n @ 0.6 @ 100k ^ 1.8 mW
(eq. 7)
Please keep in mind the value is temperature and voltage
dependent. Especially Cboot voltage can be higher than
calculated value. See “Layout recommendation” section for
more details.
Total Power Dissipation
The NCP5183 is suitable to drive high input capacitance
MOSFET, from this reason it is equipped with high current
capability drivers. Power dissipation on the die, especially
at high frequencies can be limiting factor for using this
driver. It is important to not exceed maximum junction
temperature (listed in absolute maximum ratings table) in
any cases. To calculate approximate power losses follow
these steps:
1. Power loss of device (except drivers) while
switching at appropriate frequency (see Figure 26)
is equal to
^
(eq. 4)
Where:
tcharge – time period the Cboot is being charged, usually the
period the low side MOSFET is turned on
Cboot – boot strap capacitor value
Vmax – maximum voltage the Cboot capacitor can be
theoretically charged to. Usually the VCC – Vf . The Vf is
forward voltage of used diode.
VCmin –the voltage level the capacitor is charged from
VCmax –the voltage level the capacitor is charged to. It is
necessary to determine the target voltage for charging,
because in theory, when a capacitor is charged from a
voltage source through a resistor, the capacitor can never
reach the voltage of the source. In this particular case a
50 mV difference (between the voltage behind the diode and
VCmax) is used.
P logic + P HS ) P LS + (V boot @ I B2) ) (V CC @ I CC2) +
+ (14.4 @ 1.6m) ) (15 @ 0.6m) ^ 32.1 mW
P drivers + ǒ(Q g @ V boot) ) (Q g @ V CC)Ǔ @ f +
+ ((30n @ 14.4) ) (30n @ 15)) @ 100k ^ 88 mW
(eq. 9)
3. Total power losses
P total + P logic ) P drivers + 32.1m ) 88m ^ 120 mW
The resistor value obtained from eq. 4 does not count with
the quiescent current IB2 of the high side driver. This current
will create another voltage drop of:
V IB2_drop + R boot @ I B2 + 11 @ 81m ^ 0.9 mV
(eq. 8)
2. Power loss of drivers
(eq. 10)
4. Junction temperature increase for calculated power
loss
(eq. 5)
t J + R tJa @ P total + 183 @ 0.12 ^ 22 K
The current consumed by high side driver will be higher,
because the IB2 is valid when the device is not switching.
While switching, losses by charging and discharging
internal transistors as well as the level shifters will be added.
This current will increase with frequency.
The additional 0.9 mV drop will be added to VCmax value.
The additional 0.9 mV drop can be either accepted or the
(eq. 11)
The temperature calculated in eq. 11 is the value which has
to be added to ambient temperature. In case the ambient
temperature is 30°C, the junction temperature will be 52°C.
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NCP5183, NCV5183
PACKAGE OUTLINE
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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14
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP5183, NCV5183
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