NJW4128 Switching Regulator IC for Buck Converter Current Mode Control w/ 40V/2.5A MOSFET GENERAL DESCRIPTION ■ PACKAGE OUTLINE The NJW4128 is a buck converter with 40V/2.5A MOSFET. It corresponds to high oscillating frequency, and Low ESR Output Capacitor (MLCC) within wide input range from 4.5V to 40V. Therefore, the NJW4128 can realize downsizing of applications with a few external parts so that adopts current mode control. Also, it has a soft start function, external clock synchronization, over current protection and thermal shutdown circuit. It is suitable for supplying power to a Car Accessory, Office Automation Equipment, Industrial Instrument and so on. NJW4128GM1 FEATURES Current Mode Control External Clock Synchronization Wide Operating Voltage Range 4.5V to 40V Switching Current 3.6A min. PWM Control Built-in Compensation Circuit Correspond to Ceramic Capacitor (MLCC) Oscillating Frequency 450kHz typ. (A ver.) 300kHz typ. (B ver.) Soft Start Function 4ms typ. UVLO (Under Voltage Lockout) Over Current Protection (Hiccup type) Thermal Shutdown Protection Power Good Function Standby Function Package Outline NJW4128GM1 : HSOP8 PRODUCT CLASSFICATION Part Number NJW4128GM1-A NJW4128GM1-B Ver.2012-12-04 Version Oscillation Frequency Power Good Package A B 450kHz typ. 300kHz typ. √ √ HSOP8 HSOP8 Operating Temperature Range -40°C to +85°C -40°C to +85°C -1- NJW4128 PIN CONFIGURATION 1 8 2 7 3 6 4 5 PIN FUNCTION 1. SW 2. SW 3. GND 4. PG 5. IN6. EN/SYNC 7. V+ 8. V+ Exposed PAD on backside connect to GND NJW4128GM1-A NJW4128GM1-B BLOCK DIAGRAM V+ SLOPE COMP. CURRENT SENSE UVLO OCP EN/SYNC High: ON Low : OFF(Standby) Enable (Standby) 100kΩ SYNC S Q OSC Buffer R PWM SW TSD INER⋅AMP Soft Start Vref 0.8V PG GND Pow er Good Control Logic -2- Ver.2012-12-04 NJW4128 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Supply Voltage V+ + V - SW pin Voltage VV-SW EN/SYNC pin Voltage VEN/SYNC IN- pin Voltage VINPower Good pin Voltage (*1) VPG (Ta=25°C) MAXIMUM RATINGS UNIT +45 V +45 V +45 V -0.3 to +6 V -0.3 to +6 V HSOP8 790 (*1) Power Dissipation PD mW 2,500 (*2) Junction Temperature Range Tj -40 to +150 °C Operating Temperature Range Topr -40 to +85 °C Storage Temperature Range Tstg -40 to +150 °C (*1): Mounted on glass epoxy board. (76.2×114.3×1.6mm:based on EIA/JDEC standard, 2Layers) (*2): Mounted on glass epoxy board. (76.2×114.3×1.6mm:based on EIA/JDEC standard, 4Layers) (For 4Layers: Applying 74.2×74.2mm inner Cu area and a thermal via hall to a board based on JEDEC standard JESD51-5) RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL Supply Voltage V+ Power Good pin Voltage VPG External Clock Input Range A version fSYNC B version Ver.2012-12-04 MIN. 4.5 0 TYP. – – MAX. 40 5.5 UNIT V V 440 280 – – 600 500 kHz -3- NJW4128 (Unless otherwise noted, V+=VEN./SYNC=12V, Ta=25°C) ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Under Voltage Lockout Block ON Threshold Voltage OFF Threshold Voltage Hysteresis Voltage VT_ON VT_OFF VHYS Soft Start Block Soft Start Time TEST CONDITION MIN. TYP. MAX. UNIT V+= L → H V+= H → L 4.2 4.1 70 4.4 4.3 90 4.5 4.4 – V V mV TSS VB=0.75V 2 4 8 ms fOSC A version, VIN-=0.7V B version, VIN-=0.7V 405 270 450 300 495 330 kHz kHz fDV V+=4.5V to 40V – 1 – % fDT Ta=-40°C to +85°C – 5 – % -1.0% -0.1 0.8 – +1.0% +0.1 V µA 88 – – – – 92 220 250 150 170 – 300 340 220 250 % ns ns ns ns – 25 – ms – 3.6 – 0.15 4.6 – 0.3 5.5 4 Ω A µA Oscillator Block Oscillation Frequency Oscillation Frequency deviation (Supply voltage) Oscillation Frequency deviation (Temperature) Error Amplifier Block Reference Voltage Input Bias Current PWM Comparate Block Maximum Duty Cycle Minimum ON Time1 (Use Built-in Oscillator) Minimum ON Time2 (Use Ext CLK) VB IB MAXDUTY tON-min1 tON-min2 OCP Block COOL DOWN Time tCOOL Output Block Output ON Resistance Switching Current Limit SW Leak Current RON ILIM ILEAK -4- VIN-=0.7V A version B version A version, fSYNC=500kHz B version, fSYNC=400kHz ISW=2.5A VEN/SYNC=0V, V+=45V, VSW=0V Ver.2012-12-04 NJW4128 (Unless otherwise noted, V+=VEN/SYNC=12V, Ta=25°C) ELECTRICAL CHARACTERISTICS PARAMETER Standby Control / Sync Block EN/SYNC pin High Threshold Voltage EN/SYNC pin Low Threshold Voltage Input Bias Current (EN/SYNC pin) Power Good Block High Level Detection Voltage High Level Detection Voltage Hysterisis Region Power Good ON Resistance Leak Current at OFF State SYMBOL VTHH_EN/SYNC TEST CONDITION VEN/SYNC= L → H VTHL_EN/SYNC VEN/SYNC= H → L IEN VTHH_PG VTHL_PG VHYS_PG RON_PG ILEAK_PG VEN/SYNC=12V Measured at IN- pin Measured at IN- pin IPG=10mA VPG=6V MIN. TYP. MAX. UNIT 1.6 – V+ V 0 – 0.5 V – 170 250 µA 105 85 – – – 110 90 2 37 – 115 95 – 50 0.1 % % % Ω µA – 4 4.7 mA – 3.5 4.2 mA – – 3 µA General Characteristics Quiescent Current Standby Current Ver.2012-12-04 IDD IDD_STB A version, RL=no load, VIN-=0.7V B version, RL=no load, VIN-=0.7V VEN/SYNC=0V -5- NJW4128 TYPICAL APPLICATIONS V IN CIN2 CIN1 L EN/SYNC EN/SYNC High: ON Low: OFF (Standby) Pow er Good V+ V OUT SW CFB NJW4128 PG IN- R2 RFB GND SBD COUT R1 -6- Ver.2012-12-04 NJW4128 TYPICAL CHARACTERISTICS (A, B version) 0.810 Reference Voltage VB (V) 0.81 Reference Voltage VB (V) Reference Voltage vs. Temperature + (V =12V) Reference Voltage vs. Supply Voltage (Ta=25°C) 0.805 0.8 0.795 0.79 0.805 0.800 0.795 0.790 0 10 20 30 + Supply Voltage V (V) 40 -50 Output ON Resistance vs. Temperature (ISW=3A) Switching Current Limit vs. Temperature 0.3 5.5 + V =12V 5 + V =40V + V =5V 4.5 4 3.5 Output ON Resistance RON (Ω) 6 Switching Current Limit I LIM (A) -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) 0.25 + V =40V 0.2 + V =12V 0.15 + 0.1 V =5V 0.05 0 3 -50 Ver.2012-12-04 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -7- NJW4128 TYPICAL CHARACTERISTICS (A, B version) Under Voltage Lockout Voltage vs. Temperature 4.5 8 VT_ON 4.35 4.3 4.25 4.2 VT_OFF 4.15 Soft Start Time Tss (ms) Threshold Voltage (V) 4.45 4.4 6 5 4 2 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 Switching Leak Current vs. Temperature + (V =45V , VEN/SYNC=0V , VSW=0V) 10 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) Standby Current vs. Temperature (VEN/SYNC=0V) 10 9 9 Standby Current IDD_STB (µA) Switching Leak Current ILEAK (µA) 7 3 4.1 8 7 6 5 4 3 2 8 7 6 + V =40V 5 4 3 + V =12V + V =4.5V 2 1 1 0 0 -50 -8- Soft Start Time vs. Temperature + (V =12V, VB=0.75V) -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) Ver.2012-12-04 NJW4128 TYPICAL CHARACTERISTICS (A version) Oscillation Frequency vs. Supply Voltage (A ver., VIN-=0.7V, Ta=25°C) Quiescent Current vs. Supply Voltage (A ver., RL=no load, VIN-=0.7V, Ta=25°C) 5 465 Quiescent Current IDD (mA) Oscillation Frequnecny fOSC (kHz) 470 460 455 450 445 440 3 2 1 435 430 0 0 10 20 30 + Supply Voltage V (V) 40 0 Oscillation Frequency vs Temperature + (A ver., V =12V, VIN-=0.7V) 490 480 470 460 450 440 430 420 410 400 40 99 98 97 96 95 94 93 92 91 90 89 88 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 Minimum ON Time1 vs. Temperature + (A ver., V =12V) 4.5 Quiescent Current IDD (mA) 280 260 240 220 200 180 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) Quiescent Current vs. Temperature (A ver., RL=no load, VIN-=0.7V) 5 300 Minimum ON Time1 tON-min1 (ns) 10 20 30 + Supply Voltage V (V) Maximum Duty Cycle vs. Temperature + (A ver., V =12V, VIN-=0.7V) 100 Maximum Duty Cycle MAXDUTY (%) 500 Oscillation Frequency fosc (kHz) 4 + V =12V 4 3.5 + 3 V =4.5V + V =40V 2.5 2 1.5 1 0.5 0 160 -50 Ver.2012-12-04 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -9- NJW4128 TYPICAL CHARACTERISTICS (B version) Oscillation Frequency vs. Supply Voltage (B ver., VIN-=0.7V, Ta=25°C) 5 308 Quiescent Current IDD (mA) Oscillation Frequnecny fOSC (kHz) 310 306 304 302 300 298 296 294 4 3 2 1 292 290 0 0 10 20 30 + Supply Voltage V (V) 40 0 Oscillation Frequency vs Temperature + (B ver., V =12V, VIN-=0.7V) 320 310 300 290 280 270 99 98 97 96 95 94 93 92 91 -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) Minimum ON Time1 vs. Temperature + (B ver., V =12V) 340 5 320 4.5 300 4 280 260 240 220 200 180 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) Quiescent Current vs. Temperature (B ver., RL=no load, VIN-=0.7V) Quiescent Current IDD (mA) Minimum ON Time1 tON-min1 (ns) 40 90 -50 + V =12V 3.5 3 + V =4.5V 2.5 + V =40V 2 1.5 1 0.5 0 160 -50 - 10 - 10 20 30 + Supply Voltage V (V) Maximum Duty Cycle vs. Temperature + (B ver., V =12V, VIN-=0.7V) 100 Maximum Duty Cycle MAXDUTY (%) 330 Oscillation Frequency fosc (kHz) Quiescent Current vs. Supply Voltage (B ver., RL=no load, VIN-=0.7V, Ta=25°C) -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) -50 -25 0 25 50 75 100 125 150 Ambient Temperature Ta (°C) Ver.2012-12-04 NJW4128 Application Manual NJW4128 Technical Information PIN DESCRIPTIONS GND PIN NUMBER 1 2 3 PG 4 IN- 5 EN/SYNC 6 V+ 7 8 Power Supply pin for Power Line Exposed PAD – Connect to GND PIN NAME SW Ver.2012-12-04 FUNCTION Switch Output pin of Power MOSFET GND pin Power Good pin. An open drain output that goes high impedance when the IN- pin voltage is stable around ±10%. Output Voltage Detecting pin Connects output voltage through the resistor divider tap to this pin in order to voltage of the IN- pin become 0.8V. Standby Control pin The EN/SYNC pin internally pulls down with 100kΩ. Normal Operation at the time of High Level. Standby Mode at the time of Low Level or OPEN. Moreover, it operates by inputting clock signal at the oscillatory frequency that synchronized with the input signal. - 11 - NJW4128 NJW4128Application Manual Technical Information Description of Block Features 1. Basic Functions / Features Error Amplifier Section (ER⋅AMP) 0.8V±1% precise reference voltage is connected to the non-inverted input of this section. To set the output voltage, connects converter's output to inverted input of this section (IN- pin). If requires output voltage over 0.8V, inserts resistor divider. Because the optimized compensation circuit is built-in, the application circuit can be composed of minimum external parts. PWM Comparator Section (PWM), Oscillation Circuit Section (OSC) The NJW4128 uses a constant frequency, current mode step down architecture. The oscillation frequency is 450kHz (typ.) at A version and 300kHz (typ.) at B version. The PWM signal is output by feedback of output voltage and slope compensation switching current at the PWM comparator block. The maximum duty ratio is 92% (typ.). Table 1. Minimum ON time of NJW4128 A version (fOSC =450kHz) Use Built-in 220ns typ. Oscillator Use External 150ns typ. Clock (@ fSYNC=500kHz) B version (fOSC =300kHz) 250ns typ. 170ns typ. (@ fSYNC=400kHz) The buck converter of ON time is decided the following formula. ton = VOUT [s] VIN × fOSC VIN shows input voltage and VOUT shows output voltage. When the ON time becomes below in tON-min, in order to maintain output voltage at a stable state, change of duty or pulse skip operation may be performed. Power MOSFET (SW Output Section) The power is stored in the inductor by the switch operation of built-in power MOSFET. The output current is limited to 3.6A(min.) the overcurrent protection function. In case of step-down converter, the forward direction bias voltage is generated with inductance current that flows into the external regenerative diode when MOSFET is turned off. The SW pin allows voltage between the PV+ pin and the SW pin up to +45V. However, you should use an Schottky diode that has low saturation voltage. Power Supply, GND pin (V+ and GND) In line with switching element drive, current flows into the IC according to frequency. If the power supply impedance provided to the power supply circuit is high, it will not be possible to take advantage of IC performance due to input voltage fluctuation. Therefore insert a bypass capacitor close to the V+ pin – the GND pin connection in order to lower high frequency impedance. - 12 - Ver.2012-12-04 NJW4128 Application Manual NJW4128 Technical Information Description of Block Features (Continued) 2. Additional and Protection Functions / Features Under Voltage Lockout (UVLO) The UVLO circuit operating is released above V+=4.4V(typ.) and IC operation starts. When power supply voltage is low, IC does not operate because the UVLO circuit operates. There is 90mV(typ.) width hysteresis voltage at rise and decay of power supply voltage. Hysteresis prevents the malfunction at the time of UVLO operating and releasing. Soft Start Function (Soft Start) The output voltage of the converter gradually rises to a set value by the soft start function. The soft start time is 4ms (typ.). It is defined with the time of the error amplifier reference voltage becoming from 0V to 0.75V. The soft start circuit operates after the release UVLO and/or recovery from thermal shutdown. 0.8V Vref, IN- pin Voltage OSC Waveform ON SW pin OFF UVLO(4.4V typ.) Release, Standby, Recover from Thermal Shutdow n Soft Start time: Tss=4ms(typ.) to V B=0.75V Steady Operaton Soft Start effective period to V B=0.8V Fig. 1. Startup Timing Chart Ver.2012-12-04 - 13 - NJW4128 NJW4128Application Manual Technical Information Description of Block Features (Continued) Over Current Protection Circuit (OCP) NJW4128 contains overcurrent protection circuit of hiccup architecture. The overcurrent protection circuit of hiccup architecture is able to decrease heat generation at the overload. The NJW4128 output returns automatically along with release from the over current condition. At when the switching current becomes ILIM or more, the overcurrent protection circuit is stopped the MOSFET output. The switching output holds low level down to next pulse output at OCP operating. At the same time starts pulse counting, and stops the switching operation when the overcurrent detection continues approx 1ms. After NJW4128 switching operation was stopped, it restarts by soft start function after the cool down time of approx 25ms (typ.). IN- pin Voltage 0.8V 0.5V 0V Oscillation Frequency A ver.=450kHz typ. B ver.=300kHz typ. ON SW pin OFF Sw itching Current ILIM 0 Pulse Count :about 1ms Cool Dow n time :25ms typ. Pulse by Pulse Static Status Detect Overcurrent Soft Start Fig. 2. Timing Chart at Over Current Detection Thermal Shutdown Function (TSD) When Junction temperature of the NJW4128 exceeds the 160°C*, internal thermal shutdown circuit function stops SW function. When junction temperature decreases to 145°C* or less, SW operation returns with soft start operation. The purpose of this function is to prevent malfunctioning of IC at the high junction temperature. Therefore it is not something that urges positive use. You should make sure to operate within the junction temperature range rated (150°C). (* Design value) Standby Function The NJW4128 stops the operating and becomes standby status when the EN/SYNC pin becomes less than 0.5V. The EN/SYNC pin internally pulls down with 100kΩ, therefore the NJW4128 becomes standby mode when the EN/SYNC pin is OPEN. You should connect this pin to V+ when you do not use standby function. - 14 - Ver.2012-12-04 NJW4128 Application Manual NJW4128 Technical Information Description of Block Features (Continued) External Clock Synchronization By inputting a square wave to EN/SYNC pin, can be synchronized to an external frequency. You should fulfill the following specification about a square wave. (Table 2.) Table 2. The input square wave to an EN/SYNC pin. A version B version (fOSC =450kHz) (fOSC =300kHz) 440kHz to 280kHz to Input Frequency 600kHz 500kHz Duty Cycle 25% to 75% 20% to 80% Voltage 1.6V or more at High level magnitude 0.5V or less at Low level The trigger of the switching operating at the external synchronized mode is detected to the rising edge of the input signal. At the time of switching operation from standby or asynchronous to synchronous operation, it has set a delay time approx 20µs to 30µs in order to prevent malfunctions. (Fig. 3.) High EN/SYNC pin Low ON SW pin OFF Standby Delay Time External Clock Synchronization Fig. 3. Switching Operation by External Synchronized Clock Power Good Function It monitors the output status and outputs a signal from PG pin that internally connected to open drain MOSFET. The Power Good pin goes high impedance when the IN- pin voltage is stable around ±10%(typ.) of error amplifier reference voltage. A low on the pin indicates that the IN- pin voltage is out of the setting voltage. To prevent malfunction of the Power Good output, it has hysterisis 2%(typ.) and the delay time approx 20µs to 30µs against the IN- pin voltage changes. Ver.2012-12-04 - 15 - NJW4128 NJW4128Application Manual Technical Information Application Information Inductors Because a large current flows to the inductor, you should select the inductor with the large current capacity not to saturate. Optimized inductor value is determined by the input voltage and output voltage. The Inductor setting example is shown in Table 3. Table 3. Inductor Setting Example (A ver.) Input Voltage Output Voltage VIN VOUT 3.3V 12V 5.0V 8.0V 3.3V 24V 5.0V 8.0V Inductor L ≤ 6.8µH ≤ 10µH ≤ 10µH ≤ 10µH ≤ 12µH ≤ 12µH When increasing inductor value, it is necessary to increasing capacity of an output capacitor and to secure the stability of application. The minimum of inductor value is restricted from the following formula, when ON duty exceeds 50%. L≥ VIN × (2 × D ON − 1) [µH] 2. 3 Reducing L decreases the size of the inductor. However a peak current increases and adversely affects the efficiency. (Fig. 4.) Moreover, you should be aware that the output current is limited because it becomes easy to operating to the overcurrent limit. The peak current is decided the following formula. ∆IL = (VIN − VOUT ) × VOUT L × VIN × fOSC Ipk = IOUT + [A] ∆I L [A] 2 Current Peak Current IPK Indunctor Ripple Current ∆IL Peak Current IPK Output Current IOUT Indunctor Ripple Current ∆IL 0 tON tOFF Reducing L Value tON tOFF Increasing L value Fig. 4. Inductor Current State Transition (Continuous Conduction Mode) - 16 - Ver.2012-12-04 NJW4128 Application Manual NJW4128 Technical Information Application Information (Continued) Input Capacitor Transient current flows into the input section of a switching regulator responsive to frequency. If the power supply impedance provided to the power supply circuit is large, it will not be possible to take advantage of the NJW4128 performance due to input voltage fluctuation. Therefore insert an input capacitor as close to the MOSFET as possible. A ceramic capacitor is the optimal for input capacitor. The effective input current can be expressed by the following formula. IRMS = IOUT × VOUT × (VIN − VOUT ) VIN [A] In the above formula, the maximum current is obtained when VIN = 2 × VOUT, and the result in this case is IRMS = IOUT (MAX) ÷ 2. When selecting the input capacitor, carry out an evaluation based on the application, and use a capacitor that has adequate margin. Output Capacitor An output capacitor stores power from the inductor, and stabilizes voltage provided to the output. Because NJW4128 corresponds to the output capacitor of low ESR, the ceramic capacitor is the optimal for compensation. The output capacitor setting example is shown in Table 4. Table 4. Output Capacitor Setting Example (A ver.) Input Voltage Output Voltage Output Capacitor VIN VOUT COUT 3.3V ≥ 47µF×2 / 6.3V 12V, 24V 5.0V ≥ 22µF×2 / 6.3V 8.0V ≥ 22µF×2 / 16V Part Number GRM31CB30J476KE18: Murata GRM31CB30J226ME18: Murata GRM32EB31E226KE15: Murata The output capacitor uses capacity bigger than Table 4. In addition, you should consider varied characteristics of capacitor (a frequency characteristic, a temperature characteristic, a DC bias characteristic and so on) and unevenness peculiar to a capacitor supplier enough. Therefore when selecting a capacitors, you should confirm the characteristics with supplier datasheets. When selecting an output capacitor, you must consider Equivalent Series Resistance (ESR) characteristics, ripple current, and breakdown voltage. The output ripple noise can be expressed by the following formula. Vripple(p −p ) = ESR × ∆IL [ V ] The effective ripple current that flows in a capacitor (Irms) is obtained by the following equation. Irms = Ver.2012-12-04 ∆IL [ Arms] 2 3 - 17 - NJW4128 NJW4128Application Manual Technical Information Application Information (Continued) Catch Diode When the switch element is in OFF cycle, power stored in the inductor flows via the catch diode to the output capacitor. Therefore during each cycle current flows to the diode in response to load current. Because diode's forward saturation voltage and current accumulation cause power loss, a Schottky Barrier Diode (SBD), which has a low forward saturation voltage, is ideal. An SBD also has a short reverse recovery time. If the reverse recovery time is long, through current flows when the switching transistor transitions from OFF cycle to ON cycle. This current may lower efficiency and affect such factors as noise generation. Setting Output Voltage, Compensation Capacitor The output voltage VOUT is determined by the relative resistances of R1, R2. The current that flows in R1, R2 must be a value that can ignore the bias current that flows in ER AMP. ⎛ R2 ⎞ VOUT = ⎜ + 1⎟ × VB [ V ] ⎝ R1 ⎠ The zero points are formed with R2 and CFB, and it makes for the phase compensation of NJW4128. The zero point is shown the following formula. f Z1 = 1 [Hz] 2 × π × R2 × C FB You should set the zero point as a guide from 50kHz to 70kHz. Output voltage setting Resistor and compensation capacitor setting example is shown in Table 5. Table 5. Output Voltage Setting Resistor and Compensation Capacitor Setting Example Input Voltage Output Voltage R1 R2 CFB VIN VOUT 3.3V 180pF 4.7kΩ 15kΩ 12V, 24V 5.0V 180pF 3kΩ 16kΩ 8.0V 82pF 3.9kΩ 36kΩ - 18 - Ver.2012-12-04 NJW4128 Application Manual NJW4128 Technical Information Application Information (Continued) Board Layout In the switching regulator application, because the current flow corresponds to the oscillation frequency, the substrate (PCB) layout becomes an important. You should attempt the transition voltage decrease by making a current loop area minimize as much as possible. Therefore, you should make a current flowing line thick and short as much as possible. Fig.5. shows a current loop at step-down converter. Especially, should lay out high priority the loop of CIN-SW-SBD that occurs rapid current change in the switching. It is effective in reducing noise spikes caused by parasitic inductance. NJW4128 Built-in SW V IN CIN NJW4128 Built-in SW L SBD COUT V IN CIN (a) Buck Converter SW ON L SBD COUT (b) Buck Converter SW OFF Fig. 5. Current Loop at Buck Converter Concerning the GND line, it is preferred to separate the power system and the signal system, and use single ground point. The voltage sensing feedback line should be as far away as possible from the inductance. Because this line has high impedance, it is laid out to avoid the influence noise caused by flux leaked from the inductance. Fig. 6. shows example of wiring at buck converter. Fig. 7 shows the PCB layout example. L V IN V OUT SW V+ CIN SBD COUT RL (Bypass Capacitor) NJW4128 CFB INR2 GND Separate Digital(Signal) GND from Pow er GND R1 To avoid the influence of the voltage drop, the output voltage should be detected near the load. Because IN- pin is high impedance, the voltage detection resistance: R1/R2 is put as much as possible near IC(IN-). Fig. 6. Board Layout at Buck Converter Ver.2012-12-04 - 19 - NJW4128 NJW4128Application Manual Technical Information Application Information (Continued) GND OUT VOUT COUT Power GND Area L GND IN SBD C IN VIN Power Good EN/SYNC R1 R2 Signal GND Area RFB CFB Feed back signal Connect Signal GND line and Power GND line on backside pattern Fig. 7. Layout Example (upper view) - 20 - Ver.2012-12-04 NJW4128 Application Manual NJW4128 Technical Information Calculation of Package Power A lot of the power consumption of buck converter occurs from the internal switching element (Power MOSFET). Power consumption of NJW4128 is roughly estimated as follows. Input Power: Output Power: Diode Loss: NJW4128 Power Consumption: Where: VIN VOUT VF OFF duty PIN = VIN × IIN [W] POUT = VOUT × IOUT [W] PDIODE = VF × IL(avg) × OFF duty [W] PLOSS = PIN − POUT − PDIODE [W] : Input Voltage for Converter : Output Voltage of Converter : Diode's Forward Saturation Voltage : Switch OFF Duty IIN IOUT IL(avg) : Input Current for Converter : Output Current of Converter : Inductor Average Current Efficiency (η) is calculated as follows. η = (POUT ÷ PIN) × 100 [%] You should consider temperature derating to the calculated power consumption: PD. You should design power consumption in rated range referring to the power dissipation vs. ambient temperature characteristics (Fig. 8). NJW4128GM1 Power Dissipation vs. Ambient Temperature (Tj=~150°C) 3000 Power Dissipation PD (mW) At on 4 layer PC Board (*4) 2500 2000 1500 At on 2 layer PC Board (*3) 1000 500 0 -50 -25 0 25 50 75 100 Ambient Temperature Ta (°C) 125 150 (*3): Mounted on glass epoxy board. (76.2×114.3×1.6mm:based on EIA/JDEC standard, 2Layers) (*4): Mounted on glass epoxy board. (76.2×114.3×1.6mm:based on EIA/JDEC standard, 4Layers) (For 4Layers: Applying 74.2×74.2mm inner Cu area and a thermal via hall to a board based on JEDEC standard JESD51-5) Fig. 8. Power Dissipation vs. Ambient Temperature Characteristics [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2012-12-04 - 21 -