AD AD8338ACPZ-RL Low power, 18 mhz variable gain amplifier Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
VBAT
VREF
OFFSET NULL
AD8338
FBKP
VGA CORE
INPR
+
INMR
–
OUTP
+
OUTPUT
STAGE
0dB
–
OUTM
0dB TO 80dB
VREF
INPD
COMM
MODE
GAIN
FBKM
AUTOMATIC
GAIN
CONTROL
GAIN INTERFACE
INMD
APPLICATIONS
DETO
VAGC
Figure 1.
Front end for inductive telemetry systems
Ultrasonic signal receivers
RF baseband signal conditioning
100
80
60
The AD8338 is a variable gain amplifier (VGA) for applications
that require a fully differential signal path, low power, low noise,
and a well-defined gain over frequencies from LF to 18 MHz. The
device can also operate using single-ended sources if required.
The basic gain function is linear-in-dB with a nominal gain range
of 0 dB to 80 dB; the nominal gain range corresponds to a control
voltage on the GAIN pin of 0.1 V to 1.1 V. The gain range can be
adjusted up or down via direct access to the internal summing
nodes at the INPD and INMD pins. For example, if a 47 Ω resistor
is applied to the INPD and INMD pins, a gain range of 20 dB to
100 dB is set with an input referred noise level of 1.5 nV√Hz.
The AD8338 includes additional circuits to enable offset correction
and automatic gain control (AGC). DC offset voltages are removed
by the offset correction circuit, which behaves like a high-pass filter.
The high-pass filter corner frequency is set using an external
capacitor. The AGC function varies the gain of the AD8338 to
maintain a constant rms output voltage. A user supplied voltage
controls the target output rms voltage. A user supplied capacitor
to ground at the DETO pin controls the response time of the
AGC circuit.
GAIN (dB)
GENERAL DESCRIPTION
Rev. 0
OFSN
11279-001
Voltage controlled gain range of 0 dB to 80 dB
3 mA supply current at gain of 40 dB
Low frequency (LF) to 18 MHz operation
Supply range: 3.0 V to 5.0 V
Adjustable gain range
Low noise: 4.5 nV/√Hz
Fully differential signal path
Offset correction (offset null) feature
Adjustable bandwidth
Internal 1.5 V reference
16-lead LFCSP
Automatic gain control feature
Wide gain range for high dynamic range signals
40
20
0
VGAIN = 1.1V
VGAIN = 1.0V
VGAIN = 0.9V
VGAIN = 0.8V
VGAIN = 0.7V
VGAIN = 0.6V
VGAIN = 0.5V
VGAIN = 0.4V
VGAIN = 0.3V
VGAIN = 0.2V
VGAIN = 0.1V
–20
–40
10k
100k
1M
10M
FREQUENCY (Hz)
100M
11279-005
Data Sheet
Low Power, 18 MHz Variable Gain Amplifier
AD8338
Figure 2. Gain vs. Frequency
The AD8338 offers additional versatility by allowing user access
to the internal summing nodes. With a few discrete components,
users can customize the gain, bandwidth, input impedance, and
noise profile of the part to fit their application.
The AD8338 uses a single supply voltage of 3.0 V to 5.0 V and is
very power efficient, consuming as little as 3 mA quiescent current.
The AD8338 is available in a 3 mm × 3 mm, RoHS compliant,
16-lead LFCSP. It is specified over the industrial temperature range
of −40°C to +85°C.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8338
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 12
Applications ....................................................................................... 1
Getting Started with the AD8338............................................. 12
General Description ......................................................................... 1
Offset Correction Circuit .......................................................... 12
Functional Block Diagram .............................................................. 1
Explanation of the Gain Function............................................ 12
Revision History ............................................................................... 2
AGC Circuit ................................................................................ 13
Specifications..................................................................................... 3
Adjusting the Output Common-Mode Voltage ..................... 14
AC Specifications.......................................................................... 3
Applications Information .............................................................. 15
Absolute Maximum Ratings............................................................ 4
Simple On-Off Keyed (OOK) Receiver ................................... 15
Thermal Resistance ...................................................................... 4
Interfacing the AD8338 to an ADC ......................................... 15
ESD Caution .................................................................................. 4
Outline Dimensions ....................................................................... 16
Pin Configuration and Function Descriptions ............................. 5
Ordering Guide .......................................................................... 16
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
4/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
AD8338
SPECIFICATIONS
AC SPECIFICATIONS
VBAT = 3.0 V, TA = 25°C, CL = 2 pF on OUTP and OUTM, RL = ∞, MODE pin high, RIN = 2 × 500 Ω, VGAIN = 0.6 V, differential operation,
unless otherwise noted.
Table 1.
Parameter
INPUT INTERFACE
Gain Range
Gain Span
Input Voltage Range
Input 1 dB Compression
−3 dB Bandwidth
Gain Accuracy
Input Resistance
Input Capacitance
OUTPUT INTERFACE
Small Signal Bandwidth
Peak Slew Rate
Peak-to-Peak Output Swing
Common-Mode Voltage
Input-Referred Noise Voltage
Offset Voltage
POWER SUPPLY
VBAT
IVBAT
Test Conditions/Comments
Min
Standard configuration using the INPR
and INMR inputs
0
VREF ACCURACY
DETO OUTPUT CURRENT
AGC CONTROL
Maximum Target Amplitude
−2
+2
0.8
1
1.2
kΩ
2
pF
18
50
2.8
1.5
4.5
MHz
V/μs
V p-p
V
nV/√Hz
1.5
nV/√Hz
−10
−10
−50
−200
6.0
3.0
4.5
0.1
77
MODE = 0 V
Expected rms output value for target =
VAGC − VREF = 1.0 V
Rev. 0 | Page 3 of 16
dB
V p-p
V p-p
V p-p
V p-p
MHz
dB
3.0
VREF = 1.5 V
80
2.2
2
1.6
0.75
18
+0.5
Min gain, VGAIN = 0.1 V
Mid gain, VGAIN = 0.6 V
Max gain, VGAIN = 1.1 V
GAIN CONTROL
Gain Voltage
Gain Slope
Unit
dB
V p-p
OUTP and OUTM pins
VGAIN = 0.6 V
VGAIN = 0.6 V
Differential output
Standard configuration using the INPR
and INMR inputs
Driving external 47 Ω input resistors
connected to INPD and INMD
RTO, VGAIN = 0.1 V, offset null on
RTO, VGAIN = 0.6 V, offset null on
RTO, VGAIN = 0.1 V, offset null off
RTO, VGAIN = 0.6 V, offset null off
Max
80
3
Differential input, VCM = 1.5 V,
gain = 0.1 V/0 dB
f = 400 kHz
f = 1 MHz
f = 4 MHz
f = 10 MHz
Standard configuration using the INPR
and INMR inputs; 0.1 V < VGAIN < 1.1 V
Standard configuration using the INPR
and INMR inputs
Typ
80
12.5
2
±10
1.0
+10
+10
+50
+200
mV
mV
mV
mV
5.0
8.0
3.8
6.0
V
mA
mA
mA
1.1
83
V
dB/V
mV/dB
%
μA
V rms
AD8338
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
VBAT to COMM
INPR, INPD, INMD, INMR, MODE, GAIN,
FBKM, FBKP, OUTM, OUTP, VAGC,
VREF, OFSN
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Rating
−0.3 V to +5.5 V
COMM to VBAT
Table 3. Thermal Resistance
−40°C to +85°C
−65°C to +150°C
150°C
300°C
ESD CAUTION
Package Type
16-Lead LFCSP
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 16
θJA
48.75
Unit
°C/W
Data Sheet
AD8338
13 VAGC
14 OFSN
15 VBAT
16 VREF
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
12 FBKP
INPR 1
INPD 2
AD8338
11 OUTP
INMD 3
TOP VIEW
(Not to Scale)
10 OUTM
INMR 4
FBKM
NOTES
1. THE EXPOSED PAD SHOULD BE TIED
TO A QUIET ANALOG GROUND.
11279-002
DETO 8
GAIN 7
MODE 6
COMM 5
9
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
0
1
2
3
4
5
6
Mnemonic
EPAD
INPR
INPD
INMD
INMR
COMM
MODE
7
8
9
10
11
12
13
GAIN
DETO
FBKM
OUTM
OUTP
FBKP
VAGC
14
15
16
OFSN
VBAT
VREF
Description
Exposed Pad. The exposed pad should be tied to a quiet analog ground.
Positive 500 Ω Resistor Input for Voltage Input Applications.
Positive Input for Current Input Applications.
Negative Input for Current Input Applications.
Negative 500 Ω Resistor Input for Voltage Input Applications.
Ground.
Gain Mode. This pin selects positive or negative gain slope for gain control. When this pin is tied to VBAT, the
gain of the AD8338 increases proportionally with an increase of the voltage on the GAIN pin. When this pin is
tied to COMM, the gain decreases with an increase of the voltage on the GAIN pin.
Gain Control Input, 12.5 mV/dB or 80 dB/V.
Detector Output Terminal, ±10 µA. If the AGC feature is not used, tie this pin to COMM.
Negative Feedback Node. For more information, see the Adjusting the Output Common-Mode Voltage section.
Negative Output.
Positive Output.
Positive Feedback Node. For more information, see the Adjusting the Output Common-Mode Voltage section.
Voltage for Automatic Gain Control Circuit. This pin controls the target rms output voltage for the AGC circuit.
For more information, see the AGC Circuit section.
Offset Null Terminal. For more information, see the Offset Correction Circuit section.
Positive Supply Voltage.
Internal 1.5 V Voltage Reference.
Rev. 0 | Page 5 of 16
AD8338
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
80
80
70
MODE PIN LOW
60
MODE PIN HIGH
60
40
GAIN (dB)
GAIN (dB)
50
40
VGAIN = 600mV
VGAIN = 350mV
VGAIN = 100mV
20
0
30
–20
20
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VGAIN (V)
–60
100k
1M
Figure 7. Gain vs. Frequency, RIN = 50 Ω
80
70
60
60
40
50
20
GAIN (dB)
80
40
0
30
–20
20
–40
10
–60
0
78.3
78.6
78.9
79.2
79.5
79.8
80.1
80.4
GAIN SLOPE (dB/V)
11279-105
NUMBER OF HITS
Figure 4. Gain vs. VGAIN
78.0
VGAIN = 1100mV
VGAIN = 850mV
VGAIN = 600mV
VGAIN = 350mV
VGAIN = 100mV
–80
100k
1M
5
0
VGAIN = 1.1V
VGAIN = 1.0V
3
VGAIN = 0.9V
VGAIN = 0.8V
GAIN ERROR (dB)
20
VS = 3V
f = 1MHz
4
VGAIN = 0.7V
VGAIN = 0.6V
VGAIN = 0.5V
VGAIN = 0.4V
VGAIN = 0.3V
VGAIN = 0.2V
VGAIN = 0.1V
2
1
–40°C
0
+25°C
–1
–2
–3
+85°C
–20
+105°C
–4
–40
10k
100k
1M
10M
FREQUENCY (Hz)
100M
11279-106
GAIN (dB)
40
100M
Figure 8. Gain vs. Frequency, RIN = 5 kΩ
100
60
10M
FREQUENCY (Hz)
Figure 5. Gain Slope Histogram
80
100M
10M
FREQUENCY (Hz)
11279-107
0.3
Figure 6. Gain vs. Frequency
–5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VGAIN (V)
Figure 9. Gain Error vs. VGAIN over Temperature
Rev. 0 | Page 6 of 16
1.1
11279-006
0.2
11279-003
0
0.1
11279-109
–40
10
Data Sheet
AD8338
1.0
5
0.5
4
3
OFFSET VOLTAGE (mV)
REFERRED TO OUTPUT
–1.0
–1.5
10kHz
100kHz
1MHz
2MHz
4MHz
8MHz
10MHz
12MHz
14MHz
–2.0
–2.5
–3.0
0.2
2
1
0
–1
–2
–3
–4
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VGAIN (V)
–5
0.1
–40°C
+25°C
+85°C
+105°C
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
11279-012
–0.5
11279-007
GAIN ERROR (dB)
0
–3.5
0.1
VS = 3V
1.1
VGAIN (V)
Figure 13. Differential Offset Voltage vs. VGAIN, Offset Null On
Figure 10. Gain Error vs. VGAIN over Frequency
350
30
300
25
250
IMPEDANCE (Ω)
DELAY (ns)
20
15
10
DIFFERENTIAL
200
150
100
5
50
10M
100M
FREQUENCY (Hz)
11279-110
1M
0
100k
100M
Figure 14. Output Impedance vs. Frequency
20
OFFSET NULL ON
RELATIVE TO OUTPUT
VGAIN = 0.6V
0
BALANCE ERROR (dB)
50
40
30
20
10
–20
–40
GAIN = 1000
GAIN = 100
GAIN = 10
–60
GAIN = 1
–80
0
–3
–2
–1
0
1
DIFFERENTIAL OFFSET VOLTAGE (mV)
2
–120
100k
1M
10M
FREQUENCY (Hz)
Figure 12. Differential Offset Voltage Histogram
Figure 15. Output Balance Error vs. Frequency
Rev. 0 | Page 7 of 16
100M
11279-015
–100
11279-111
NUMBER OF HITS
10M
FREQUENCY (Hz)
Figure 11. Group Delay vs. Frequency
60
1M
11279-112
SINGLE-ENDED
0
100k
AD8338
Data Sheet
0
1000
–10
–20
100
NOISE (nV/ Hz)
CMRR (dB)
–30
–40
–50
–60
10
–70
–100
10k
100k
1M
0.1
10k
11279-115
–90
1
10M
FREQUENCY (Hz)
1M
10M
100M
Figure 19. Input Referred Noise vs. Frequency, VBAT = 3 V
0
+85°C
+25°C
–40°C
HD2,
HD3,
HD2,
HD3,
–10
HARMONIC DISTORTION (dBc)
NOISE (nV/ Hz)
100k
FREQUENCY (Hz)
Figure 16. CMRR vs. Frequency over Gain, Offset Null On,
Referred to Input
100k
GAIN = 1, OFFSET NULL OFF
GAIN = 10, OFFSET NULL OFF
GAIN = 100, OFFSET NULL OFF
GAIN = 1000, OFFSET NULL ON
GAIN = 10000, OFFSET NULL ON
11279-117
0dB
20dB
40dB
60dB
80dB
–80
10k
1k
–20
1kΩ
1kΩ
10kΩ
10kΩ
VOUT = 0.5V p-p
–30
–40
–50
–60
–70
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
VGAIN (V)
–90
50k
11279-017
100
Figure 20. Harmonic Distortion vs. Frequency
0
+85°C
+25°C
–40°C
HARMONIC DISTORTION (dBc)
–10
100
10
–20
–30
–40
–50
–60
–70
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VGAIN (V)
1.1
1.2
–80
0.5
1.0
1.5
2.0
2.5
VOUT (V p-p)
Figure 21. Harmonic Distortion vs. Output Amplitude
Figure 18. Input Referred Noise vs. VGAIN
Rev. 0 | Page 8 of 16
3.0
11279-120
HD2
HD3
1
11279-119
NOISE (nV/ Hz)
5M
FREQUENCY (Hz)
Figure 17. Output Referred Noise vs. VGAIN
1k
500k
11279-118
–80
Data Sheet
AD8338
0
HD2,
HD3,
HD2,
HD3,
VOUT = 0.5V p-p
–10
–20
IMD3 DISTORTION (dBc)
–30
–40
–50
–60
–70
–20
–30
–40
–50
–60
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VGAIN (V)
–80
20k
11279-123
–80
0.1
2M
20M
FREQUENCY (Hz)
Figure 22. Harmonic Distortion vs. VGAIN
Figure 25. IMD3 Distortion vs. Frequency
20
2.0
VOUT = 2V p-p
f = 1MHz
GAIN = 0dB
OUTPUT
10
1.5
0
1.0
–10
0.5
VOUT (V)
P1dB COMPRESSION (dBm)
200k
11279-124
–70
–20
–30
0
–0.5
–40
INPUT
–1.0
–50
–1.5
–60
0.3
0.5
0.7
0.9
1.1
VGAIN (V)
–2.0
11279-122
–70
0.1
0
100
200
300
400
500
600
700
800
TIME (ns)
Figure 23. Input and Output 1 dB Compression vs. VGAIN
11279-027
HARMONIC DISTORTION (dBc)
–10
0
MODE PIN HIGH
MODE PIN HIGH
MODE PIN LOW
MODE PIN LOW
Figure 26. Large Signal Pulse Response vs. Time, VGAIN = 0 V
2.0
25
VOUT = 2V p-p
f = 1MHz
GAIN = 80dB
1.5
20
1.0
0.5
VOUT (V)
15
10
0
–0.5
1MHz
–1.0
5
0
0.1
0.3
0.5
0.7
VGAIN (V)
0.9
1.1
Figure 24. OIP3 vs. VGAIN
–2.0
0
0.2
0.4
0.6
0.8
TIME (µs)
Figure 27. Large Signal Pulse Response vs. Time, VGAIN = 1.0 V
Rev. 0 | Page 9 of 16
11279-028
–1.5
11279-125
OIP3 (dBm)
100kHz
AD8338
Data Sheet
1.5
2.0
f = 100kHz
VIN LOW = 2mV
VIN HIGH = 20mV
1.0 GAIN = 40dB
VOUT = 2V p-p
f = 1MHz
GAIN = 40dB
1.5
OUTPUT VOLTAGE (V)
1.0
VOUT (V)
0.5
0
–0.5
0.5
0
–0.5
–1.0
–1.0
0
0.2
0.4
0.6
0.8
TIME (µs)
–1.5
11279-030
–2.0
0
20
60
100
120
140
160
180
200
12
–40°C, MODE PIN HIGH
+25°C, MODE PIN HIGH
+85°C, MODE PIN HIGH
–40°C, MODE PIN LOW
+25°C, MODE PIN LOW
+85°C, MODE PIN LOW
10
40
8
20
IDD (mA)
0
6
–20
4
–40
–60
2
VOUT = 100mV p-p
f = 1.5MHz
GAIN = 1
–100
0
0.2
0.4
0.6
0.8
TIME (µs)
0
11279-031
–80
0
0.2
0.1
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
VGAIN (V)
Figure 29. Small Signal Pulse Response vs. Time (Varying Capacitive Loads)
11279-131
VOUT (mV)
80
Figure 31. Overdrive Recovery vs. Time
CL = 0pF
CL = 10pF
CL = 20pF
CL = 47pF
80
60
TIME (µs)
Figure 28. Large Signal Pulse Response vs. Time, VGAIN = 0.6 V
100
40
11279-018
–1.5
Figure 32. Supply Current vs. VGAIN
50
OFFSET NULL OFF
40
VGAIN
0.6
30
10µF
GAIN (dB)
0.1
VOUT
1.0
0.1µF
10
0.01µF
0
–10
0
–20
–1.0
–30
1
2
3
4
5
6
7
8
TIME (µs)
9
10
–40
20
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 33. Offset Null Bandwidth vs. Offset Null Capacitor
Figure 30. Gain Step Response vs. Time
Rev. 0 | Page 10 of 16
11279-134
GAIN = 100
0
11279-127
GAIN STEP (V)
1µF
20
Data Sheet
AD8338
0
3.0
PSRR (dB)
–30
–40
–50
–60
–70
–80
–100
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
2.0
1.5
VS = 3V
1.0
VS = 5V
0.5
0
20k
11279-133
–90
2.5
100k
RESISTANCE (Ω)
Figure 34. PSRR vs. Frequency
11279-135
OUTPUT COMMON-MODE VOLTAGE (V)
–10
–20
Figure 37. Output Common-Mode Voltage vs. RCM to VBAT
3.0
0.1
OUTPUT VOLTAGE
1.0
0
0
5
10
15
20
25
30
35
40
TIME (µs)
11279-019
–1.0
Figure 35. AGC Response vs. Time, No Load
OUTPUT VOLTAGE
0
–1.0
0
1
2
3
4
5
6
7
8
TIME (ms)
9
10
11279-020
VOLTAGE (V)
0.1
1.0
VS = 3V
2.0
1.5
1.0
0.5
0
10k
100k
RESISTANCE (Ω)
Figure 38. Output Common-Mode Voltage vs. RCM to COMM
AGC VOLTAGE
0.6
2.5
Figure 36. AGC Response vs. Time, CL = 0.01 µF
Rev. 0 | Page 11 of 16
11279-136
VOLTAGE (V)
0.6
OUTPUT COMMON-MODE VOLTAGE (V)
AGC VOLTAGE
AD8338
Data Sheet
THEORY OF OPERATION
GETTING STARTED WITH THE AD8338
OFFSET CORRECTION CIRCUIT
The AD8338 is a variable gain amplifier (VGA) that provides a
variable gain range of 80 dB. With a constant −3 dB bandwidth
of 18 MHz across all gains, a gain bandwidth product of 180 GHz
is achieved at the highest gain using only 4.5 mA of supply current.
The differential output allows the AD8338 to directly drive an
ADC input, simplifying board design and saving space and power.
The AD8338 provides an offset correction circuit to cancel out
any dc offsets that may be present. Connecting a 0.2 µF capacitor
from the OFSN pin to VREF allows frequencies above 400 Hz to
pass through, but eliminates dc offsets. For dc-coupled operation,
disable the offset correction circuit by connecting the OFSN pin
directly to the COMM pin. When the part is operated without
offset correction, exercise caution with large gains because any
offsets present large errors on the outputs.
In addition to its gain, bandwidth, and power performance, the
AD8338 includes a range of features that increase its versatility.
•
•
•
Single-supply operation ranging from 3.0 V to 5.0 V
Built-in offset correction circuit to cancel out dc offsets
Automatic gain control (AGC) circuit to control the gain
and keep the output at a steady rms level
Access to internal nodes at both the input and output allows the
user to adjust the gain range, adjust the output common-mode
voltage, and tune the bandwidth.
INPR and INMR Pins in the Standard Configuration
The gain is controlled by a user supplied voltage input applied to
the GAIN pin. The gain can be varied from 0 dB to 80 dB when
the default internal resistors are used; the voltage at the GAIN pin
can be varied from 0.1 V to 1.1 V. The default internal resistors
are used by applying the input voltage to the INPR and INMR
pins (Pin 1 and Pin 4; see Figure 39).
INPR
500Ω
OUTP
+VOUT/2 + VREF
INPD
Unlike a high-pass filter, the offset correction circuit allows signals
below the corner frequency to pass through with high levels of
crossover distortion. If a frequency below the band of interest may
present itself to the inputs, apply a filter in front of the VGA for
best performance.
For lower frequency operation, a larger value of COFSN gives
unpredictable results. If the part is operated at frequencies below
400 Hz, disable the offset correction circuit and compensate the
offset externally.
The corner frequency can be approximately calculated as follows:
fC =
I IN =
500Ω
–VOUT/2 + VREF
0dB TO 80dB
11279-043
OUTM
Figure 39. Input Voltage Applied to the INPR and INMR Pins
In the standard configuration, a differential input voltage applied
across INPR and INMR is amplified, with the output voltage
appearing differentially across OUTP and OUTM. The outputs
have a default common-mode voltage of VREF, which is equal
to 1.5 V.
GAIN and MODE Pins
The gain of the AD8338 is controlled by the GAIN and MODE
pins. Adjusting the voltage at the GAIN pin from 0.1 V to 1.1 V
adjusts the gain from its lowest to highest value.
(1)
From a designer’s standpoint, the gain of the AD8338 can be
modeled as three cascaded gain stages. The first stage can be
thought of as a differential input transconductance stage, where
the input current is proportional to the differential input voltage
that is applied to the input resistors, as follows:
INMD
INMR
2π × 600 × COFSN
EXPLANATION OF THE GAIN FUNCTION
IIN
VIN
1
INPx − INMx
RP + RN
(2)
This current is then fed into the conceptual second stage, a
current input-current output VGA, which has a gain range
of −26 dB to +54 dB. The conceptual output current is given
by Equation 3.
IOUT_VGA = IIN × 10−26 + 80 × ((VGAIN − 0.1)/20)
(3)
When VGAIN = 0.1 V, the output current is −26 dB less than the
input current; when VGAIN = 1.1 V, the output current is +54 dB
greater than the input current.
The third and final stage can be modeled as a transimpedance
stage, expressed as follows:
The MODE pin controls the polarity of the gain adjustment. When
MODE is tied to VBAT, the gain of the AD8338 increases proportionally with an increase of the voltage on the GAIN pin. When
MODE is tied to COMM, the gain decreases with an increase of
the voltage on the GAIN pin.
Rev. 0 | Page 12 of 16
VOP = IOUT_VGA × RFEEDBACK
(4a)
VON = −IOUT_VGA × RFEEDBACK
(4b)
VOUT = VOP − VON = 2 × IOUT_VGA × RFEEDBACK
(4c)
Data Sheet
AD8338
For example, if the 500 Ω input resistors and 9.5 kΩ feedback
resistors are used and a 1 V p-p signal is applied with VGAIN set
to 0.1 V, the output value is as follows:
Similarly, if the user requires a minimum gain of −10 dB,
applying a 1.5 kΩ resistor to both the INPD and INMD pins
sets a gain range of −10 dB to +70 dB.
IIN = 1/(500 + 500) = 1 mA
(5a)
Effects of Using External Resistors
IOUT_VGA = 1 mA × 10
(5b)
When the gain is modified through the use of external resistors,
several trade-offs must be considered. For example, with the application of 47 Ω resistors at the inputs, the input noise decreases
to approximately 1.5 nV/√Hz, less than the 4.5 nV/√Hz obtained
when using the internal 500 Ω resistors. However, the −3 dB
bandwidth is reduced from 18 MHz to approximately 3 MHz.
−26/20
= 50 µA
VOUT = 2 × 50 µA × 9.5 kΩ = 0.95 V p-p
(5c)
The calculation in Equation 5 results in a total gain of approximately −0.4 dB under the specified conditions. Compressing
Equation 2 through Equation 4 produces the following simplified
gain equation:
Gain (dB) = (VGAIN − 0.1) × 80 + 20log(RFEEDBACK/RIN) − 26
(6)
where RFEEDBACK and RIN are the resistor values from a single
input to a single output.
VBAT
OFSN
VREF
AD8338
OFFSET NULL
INPR
FBKP
9.5kΩ
500Ω
OUTP
INPD
IOUT
VREF
INMD
OUTM
–26dB TO +54dB
9.5kΩ
500Ω
FBKM
GAIN INTERFACE
COMM
MODE
GAIN
AUTOMATIC
GAIN
CONTROL
DETO
VAGC
To set the target rms output voltage, apply a voltage to VAGC.
The target output voltage is lowest when VAGC is set to 1.5 V
and increases when the applied voltage diverges from the 1.5 V
reference voltage. To enable an increasing voltage at the VAGC
pin to increase the rms output voltage, use Equation 7.
11279-200
INMR
Figure 40. Functional Block Diagram
For example, if a design requires a minimum gain of 20 dB using
a few additional components, Equation 6 shows that applying a
47 Ω resistor to both the INPD and INMD pins (overriding the
value of RIN) sets a gain range of 20 dB to 100 dB (see Figure 41).
INPR
500Ω
OUTP
The automatic gain control (AGC) circuit compares the rms
output of the part with the desired rms output at the VAGC pin.
Based on this comparison, the DETO pin either sources or sinks
current. By connecting the DETO and GAIN pins together and
by connecting the MODE pin to ground, the AGC circuit can
be used to keep the output rms voltage constant.
To ensure that the AGC circuit reacts fast enough to adjust the
gain, but slow enough to allow signals through, place a capacitor
from DETO to ground. For example, in an on-off keying (OOK)
application with a carrier frequency of 6.795 MHz and a bit rate
of 10 kb/sec, a capacitor value of 0.01 µF is recommended. This
value ensures that the gain reacts to the bit energy but does not
react to the carrier signal.
VGA CORE
IIN
AGC CIRCUIT
VORMS = 1.7 × VAGC − 2.264
To enable a decreasing voltage at the VAGC pin to increase
the rms output voltage, use Equation 8.
VORMS = −1.7 × VAGC + 2.864
If the AGC feature is not used, tie the DETO pin to COMM.
+VOUT/2 + VREF
INPD
47Ω
INMD
47Ω
INMR
IIN
500Ω
OUTM
–VOUT/2 + VREF
20dB TO 100dB
11279-044
VIN
(7)
Figure 41. Using External Resistors at the INPD and INMD Pins
Rev. 0 | Page 13 of 16
(8)
AD8338
Data Sheet
ADJUSTING THE OUTPUT COMMON-MODE
VOLTAGE
Table 6. Resistor Values for Increasing the Output
Common-Mode Voltage (Resistor Tied to COMM)
As with any differential output, the output of the AD8338 is
a differential voltage that is centered about a common-mode
voltage. The output common-mode voltage (VOCM) of the
AD8338 is nominally set to 1.5 V using an internal reference
(see Figure 42).
VBAT (V)
Any
Any
Any
9.5kΩ
Target VOCM (V)
1.8
2.0
2.5
R1
OUTP = 1.5V –
OUTP = 1.5V + VOUT/2
IOUT
VREF = 1.5V
VREF = 1.5V
FBKM
9.5kΩ
11279-045
9.5kΩ
The output common-mode voltage of the AD8338 can be
adjusted to directly drive ADCs with various input commonmode requirements. To adjust the output common-mode voltage,
add a resistor from each feedback node (FBKP and FBKM) to
either COMM or VBAT. Adding a resistor from each feedback
node to VBAT decreases the output common-mode voltage; adding a resistor from each feedback node to COMM increases the
output common-mode voltage (see Figure 43 and Figure 44).
Figure 43. Decreasing the Output Common-Mode Voltage (Resistors
Connected Between the FBKP and FBKM Pins to the VBAT Pin)
FBKP
9.5kΩ
COMM
R1
OUTP = 1.5V –
IOUT
(0 – 1.5V) × 9.5kΩ
+ VOUT/2
R1
VREF = 1.5V
OUTM = 1.5V –
Table 5 and Table 6 provide examples of resistor values for
decreasing or increasing the output common-mode voltage.
9.5kΩ
FBKM
COMM
R2
(0 – 1.5V) × 9.5kΩ
+ VOUT/2
R2
Figure 44. Increasing the Output Common-Mode Voltage (Resistors
Connected Between the FBKP and FBKM Pins to the COMM Pin)
Table 5. Resistor Values for Decreasing the Output
Common-Mode Voltage (Resistor Tied to VBAT)
Resistor Value (Ω)
55,417
28,500
23,750
VBAT
FBKM
R2
Figure 42. Output Common-Mode Voltage Set to 1.5 V (Default Setting)
Target VOCM (V)
0.9
0.9
0.9
(VBAT – 1.5V) × 9.5kΩ
+ VOUT/2
R2
11279-046
OUTM = 1.5V –
OUTM = 1.5V – VOUT/2
VBAT (V)
5.0
3.3
3.0
(VBAT – 1.5V) × 9.5kΩ
+ VOUT/2
R1
11279-047
IOUT
Tied to
COMM
COMM
COMM
VBAT
FBKP
9.5kΩ
FBKP
Resistor Value (Ω)
47,500
28,500
14,250
Tied to
VBAT
VBAT
VBAT
The AD8338 uses its internal reference for all signal processing.
Therefore, although the output common-mode voltage can be
changed through the application of external resistors, the VREF
signal cannot be changed. For applications that require dc coupling
to an ADC, a differential amplifier must be used.
Rev. 0 | Page 14 of 16
Data Sheet
AD8338
APPLICATIONS INFORMATION
Table 7 provides typical values for these components at two data
rates. Note that Capacitors C1 through C4 are all of equal value,
and Inductor L2 has the same value as L1.
The excellent performance of the AD8338 results in a flat response
over various gains with rail-to-rail output signal swing, high drive
capability, and a very high dynamic range at a low 12 mW. These
features make the AD8338 an exceptional choice for use in batteryoperated equipment, low frequency and baseband applications,
and many other applications.
Table 7. Typical Values for Components in Reactive Filter
Data Rate
19,200 bps
57,600 bps
SIMPLE ON-OFF KEYED (OOK) RECEIVER
For low complexity, low power data communications, a simple
link built using a modulating carrier tone in an on/off state
provides a fast and cost-effective solution to the designer. Such
designs are used in a variety of applications, including near-field
communications among noninterference mechanical systems,
low data rate sensors, RFID tags, and so on.
The AD8338 is well suited to drive a high speed analog-to-digital
converter (ADC) and is compatible with many ADCs from Analog
Devices, Inc. This example illustrates the interfacing of the AD8338
to the AD7451. The AD7451 is a low power, 3.0 V ADC, which
is also competitively priced for a low cost total solution.
Figure 46 shows the basic connections between the AD8338
and the AD7451. The common-mode voltage provided by the
AD8338 is within the specifications of the AD7451.
The AD8338 amplifies the signal (the gain is set by an external
controller) and drives a full-wave rectifier bridge. The output of
this bridge is then low-pass filtered into 100 Ω terminations. This
design provides excellent rejection of RF and excellent baseband
information recovery for the decision stage that follows.
The AD8338 can be coupled directly to the AD7451 for full
dc-to-18 MHz operation at the highest level of performance with
low operating power (160 mW typical). The glueless interface
enables a physically small, high performance data acquisition
system that is ideal for many field instruments. A filter before
the VGA provides the antialiasing function and noise limiting.
The reactive filter components—Capacitors C1 through C4 and
Inductors L1 and L2—set the baseband recovery performance. A
design trade-off exchanges baseband response for RF attenuation.
In applications where the modulated information is not encoded
in the signal amplitude, use the AGC feature of the AD8338 to
reduce any bit errors in the sampled signal.
VREF
L1
OOK_P
MODE
U1
R2
100Ω
L2
D3
OOK_M
C4
C3
C5
0.1µF
11279-048
OFSN
OUTM
D4
COMM
DETO
GAIN
R1
100Ω
OUTP
AD8338
INMR
C6
0.01µF
C2
C1
D2
D1
INPR
CTUNE
VREF
Figure 45. Complete, Low Power OOK Receiver
3.0V
R1
49.9Ω
3.0V
VREF
MODE
C1
0.1µF
C2
0.1µF
VDD
INPR
U1
FILTER
OUTPUT
AD8338
INMR
OUTP
OUTM
VIN+
VREF
SCLK
AD7451 SDATA
VIN–
CS
TO
MICROCONTROLLER
C3
0.1µF
VREF
11279-049
OFSN
COMM
GND
DETO
ANTENNA
CRYSTAL
Carrier Attenuation,
f = 6.78 MHz
−101 dB
−73 dB
L1 and L2
240 µH
82 µH
INTERFACING THE AD8338 TO AN ADC
The schematic shown in Figure 45 demonstrates a complete
inductive telemetry on-off keyed (OOK) front end. The crystal
is cut for the target receive frequency of interest, creating a very
narrow-band filter, typically around the 6.78 MHz ISM band.
3.0V
C1 to C4
12 nF
3.9 nF
Figure 46. Basic Connections to the AD7451 ADC
Rev. 0 | Page 15 of 16
AD8338
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.30
0.23
0.18
0.50
BSC
13
PIN 1
INDICATOR
16
1
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
4
8
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
08-16-2010-E
3.10
3.00 SQ
2.90
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD8338ACPZ-R7
AD8338ACPZ-RL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Z = RoHS Compliant Part.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11279-0-4/13(0)
Rev. 0 | Page 16 of 16
Package Option
CP-16-22
CP-16-22
Branding
Y4K
Y4K
Similar pages