APL1581 DUAL INPUT LOW DROPOUT REGULATOR Features General Description • • The APL1581 series of high performance positive voltage regulators are designed for use in applications re- Adjustable or Fixed Output 520mV typ. Dropout at 5A in Dual Power quiring very low dropout voltage at 5Amp. The superior dropout characteristics result in reducing Voltage Mode • • • • • Remote Sense Pin Available heat dissipation compared to regular LDOs. The APL1581 also provides excellent regulation over line, load, and tem- 2% Accuracy Over Temperature Range Built-In Over-Temperature Protection perature variations. Current limit is trimmed to ensure specified output cur- Built-In Current Limit 5 Pin TO-263 and TO-252, SOP-8P, TO-252-4 rent and controlled short-circuit current. On-chip thermal limiting provides protection against any combination of Packages • overload tha t would create excessi ve junction temperature. Lead Free and Green Devices Available (RoHS Compliant) The APL1581 is available in both the through-hole and surface mount versions of the industry standard 5-Pin Applications • • • • TO-263 and TO-252, SOP-8P, TO-252-4 power packages. Microprocessor Supplies Chip Set Supplies VGA Card Power LCD Monitor Power Ordering and Marking Information Package Code G5 : TO-263-5 U5 :TO-252-5 KA : SOP-8P U4 : TO-252-4 Temperature Range C : 0 to 70 oC Handling Code TR : Tape & Reel Voltage Code : 15 : 1.5V 18 : 1.8V 25 : 2.5V Blank : Adjustable Version Assembly Material G : Halogen and Lead Free Device APL1581 Assembly Material Handling Code Temperature Range Package Code Voltage Code APL1581-15 G5/U5/U4 : 15 APL1581 XXXXX XXXXX - Date Code APL1581-15 KA : APL1581 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 1 www.anpec.com.tw APL1581 Pin Configuration TAB is VOUT 5 VIN 4 VCNTL 3 2 VOUT ADJ (or GND) 1 VSENSE TAB is VOUT Front View of TO-263-5 TAB is VOUT 4 3 VIN VCNTL 2 1 ADJ VSENSE Front View of TO-252-4 5 VIN 4 VCNTL 3 VOUT 2 ADJ(or GND) 1 VSENSE Front View of TO-252-5 VSENSE 1 8 VOUT ADJ (or GND) 2 7 VOUT VCNTL 3 6 VOUT VIN 4 5 VOUT SOP-8P (Top View) NC = No internal connection = Thermal Pad (connected to VOUT plane for better heat dissipation) Pin 5~8 must be connected together by a shortest wide track or plane. Absolute Maximum Ratings Symbol VIN VCNTL (Note 1, 2) Parameter Rating Unit Input Voltage 7 V Control Voltage 7 V Internally Limited W 150 °C -65 to +150 °C 260 °C PD Power Dissipation TJ Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2 : The maximum allowable power dissipation at any TA (ambient temperature) is calculated using: PD (max) = (TJ – TA) / θJA; TJ = 125°C. Exceeding the maximum allowable power dissipation will result in excessive die temperature. Thermal Characteristics Symbol Parameter Typical Value θJA Junction-to-Ambient Resistance in free air (Note 3) TO-263-5 (Toplayer plane size : 15mm x 15 mm) TO-252-4/TO-252-5 (Toplayer plane size : 10mm x 10 mm) SOP-8P (Toplayer plane size : 10mm x 10 mm) 28 42 68 Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 2 Unit o C/W www.anpec.com.tw APL1581 Thermal Characteristics (Cont.) Symbol θJC Parameter Junction-to-Case Resistance Typical Value Unit (Note 4) TO-263-5 TO-252-4/TO-252-5 o 4 5 C/W Note 3 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The sizes of the rectangular plane, where the devices are mounted, are shown in the table. Note 4: The case temperature is measured on the TAB of the device mounted on the test board described in Note 3 except the package TO-220-5. The case temperature of the TO-220-5 is measured on the bottom of the case directly below the die. Electrical Characteristics Unless otherwise noted , these specifications apply over CIN=10µF, CCNTL=1µF, COUT=10µF, and TA=0 to 70°C. Typical values refer to TA=25°C. VOUT=VSENSE. Symbol VREF Parameter Reference Voltage APL1581 Output Voltage APL1581-15 APL1581-18 APL1581-25 VOUT Line Regulation APL1581 REGLINE APL1581-15 APL1581-18 APL1581-25 Load Regulation (Note 5) APL1581 REGLOAD APL1581-15 APL1581-18 APL1581-25 Dropout Voltage (Note 6) APL1581 APL1581-15 APL1581-18 APL1581-25 VCNTL-VOUT Dropout Voltage (Note 6) APL1581 APL1581-15 APL1581-18 APL1581-25 VIN-VOUT ILIMIT ILMIN Current Limit Minimum Load Current VCNTL=2.75~5.5V, VIN=2.05~5.5V, IO =10mA~5A, VADJ=0V (IO =0~5A for fixed versions) VCNTL=3~5.5V , VIN=2.3~5.5V VCNTL=3.3~5.5V , VIN=2.6~5.5V VCNTL=4~5.5V , VIN=3.3~5.5V (IO =0A for fixed versions) VCNTL=2.75~5.5V, VIN=1.75~5.5V, IO =10mA, VADJ=0V VCNTL=3~5.5V, VIN=2.3~5.5V VCNTL=3.3~5.5V, VIN=2.6~5.5V VCNTL=4~5.5V, VIN=3~5.5V (IO =0~5A for fixed versions) VCNTL=2.75V, VIN=2.1V, VADJ =0V, IO =10mA~5A VCNTL=3V, VIN=2.35V VCNTL=3.3V, VIN=2.65V VCNTL=4V, VIN=3.35V IO =5A for all versions VIN=2.05V, VADJ =0V VIN=2.3V VIN=2.6V VIN=3.3V IO =5A for all versions VCNTL=2.75V, VADJ =0V VCNTL=3V VCNTL=3.3V VCNTL=4V VCNTL-VOUT=1.5V, VIN-VOUT=0.6V Unit Min. Typ. Max. 1.225 1.250 1.275 1.470 1.764 2.450 1.500 1.800 2.500 1.530 1.836 2.550 - - 3 mV - - 5 mV - 1.20 1.35 V - 0.52 0.75 V 5 - - A - 0.8 10 mA - 0.01 - %/W 60 70 - dB V V (Note7) APL1581 REGTHERMAL Thermal Regulation PSRR APL1581 Test Conditions Power Supply Ripple Rejection APL1581 APL1581-15 APL1581-18 APL1581-25 Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 VCNTL=5V, VIN=3.3V, VADJ =0V 30ms Pulse VRIPPLE=1VPP at 120Hz, IO=5A VCNTL=5V, VIN=5V, VADJ =0V VCNTL=5.25V, VIN=5.25V VCNTL=5.55V, VIN=5.55V VCNTL=6.25V, VIN=6.25V 3 www.anpec.com.tw APL1581 Electrical Characteristics (Cont.) Unless otherwise noted , these specifications apply over CIN = 10µF, CCNTL = 1µF, COUT = 10µF, and TA = 0 to 70°C. Typical values refer to TA = 25°C. VOUT = VSENSE. Symbol ICNTL Parameter APL1581 Test Conditions VCNTL-VOUT=1.5V, VIN-VOUT=0.8V, IO =5A CNTL Pin Current Unit Min. Typ. Max. - 45 120 mA - 8 13 mA - 50 120 µA Ground Pin Current APL1581-15 APL1581-18 APL1581-25 IGND IADJ VCNTL =3V, VIN =2.3V VCNTL =3.3V, VIN =2.6V VCNTL =4V, VIN =3.3V Adjust Pin Current APL1581 VCNTL=2.75V, VIN=2.05V , VADJ =0V Note 5 : Low duty cycle pulse test with Kelvin connections are required to maintain data accuracy . Note 6 : Dropout voltage is defined as the minimum difference between VIN and VOUT required to maintain 1% VOUT regulation. Note 7 : Minimum load current is defined as the minimum current required at the output to maintain VOUT regulation. Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 4 www.anpec.com.tw APL1581 Typical Operating Characteristics Adjust Pin Current vs. Junction Temperature 1.275 80 1.270 70 1.265 Adjust Pin Current (µA) Reference Voltage (V) Reference Voltage vs. Junction Temperature 1.260 1.255 1.250 1.245 1.240 1.235 60 50 40 30 20 10 1.230 1.225 0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 Minimum Load Current vs. Junction Temperature 75 100 125 150 VIN-VOUT Dropout Voltage vs. Output Current 1.0 VIN-VOUT Dropout Voltage (mV) Minimum Load Current (mA) 50 700 1.2 VCNTL-VOUT=10.75V 0.8 VCNTL-VOUT=1.45V 0.6 0.4 0.2 0.0 -50 -25 TJ=125oC 600 500 TJ=25oC 400 300 TJ=-50oC 200 100 0 0 25 50 75 100 125 150 Junction Temperature (°C) 0 0.5 Short-Circuit Current vs. Junction Temperature 1 1.5 2 2.5 3 3.5 Output Current (A) 4 4.5 5 VCONTROL-VOUT Dropout Voltage vs. Output Current 1.4 14 VCNTL-VOUT Dropout Voltage (V) VIN=5.0V 12 Short-Circuit Current (A) 25 Junction Temperature (°C) Junction Temperature (°C) 10 VIN=3.3V 8 6 4 2 0 TJ=0oC 1.3 TJ=-50oC 1.2 1.1 TJ=25oC 1.0 0.9 TJ=125oC 0.8 0.7 -50 -25 0 25 50 75 100 125 150 0 0.5 Junction Temperature (°C) Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 5 1 1.5 2 2.5 3 3.5 Output Current (A) 4 4.5 5 www.anpec.com.tw APL1581 Typical Operating Characteristics (Cont.) Control Pin Current vs. Output Current Control Pin Current vs. Output Current VIN-V OUT=0.6V VIN-V OUT=0.8V 80 160 TJ=125oC 120 100 TJ=25oC 80 TJ=0oC 60 40 TJ=-50oC 20 TJ=0oC 60 TJ=25oC 50 TJ=75oC 40 30 20 TJ=125oC 10 TJ=75oC 0 0 0 0.5 1 1.5 2 2.5 3 3.5 Output Current (A) 4 4.5 0 5 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Output Current (A) Control Pin Current vs. Output Current Control Pin Current vs. Output Current VIN-V OUT=1.0V VIN-V OUT=4.25V 80 70 TJ=-50oC 70 TJ=0oC 60 TJ=25oC 50 TJ=75oC 40 30 20 TJ=125oC 10 TJ=-50oC 60 VCNTL Pin Current (mA) VCNTL Pin Current (mA) TJ=-50oC 70 VCNTL Pin Current (mA) VCNTL Pin Current (mA) 140 0 TJ=0oC 50 TJ=25oC 40 TJ=75oC 30 20 TJ=125oC 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 Output Current (A) Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Output Current (A) 6 www.anpec.com.tw APL1581 Pin Description PIN FUNCTION NAME I/O VSENSE I Positive side of the reference voltage, which allows remote sensing to obtain excellent load regulation. ADJ O Negative side of the reference voltage, which allows to use resistor divider to set an expect output voltage. A small bypass capacitor can be connected from this pin to ground to improve PSRR performance. GND O For fixed voltage devices, this is the bottom of the resistor divider that sets the output voltage. VOUT O Output pin of the regulator, which connects to the TAB. A minimum of 10µF capacitor must be connected from this pin to ground to ensure the stability. VCNTL I Supply pin of the control circuitry, which must be always higher than VOUT for the device to regulate. (See electrical characteristics) VIN I Power input pin of the regulator, which must be always higher than VOUT for the device to regulate. (See electrical characteristics) Block Diagram VOUT VIN VCNTL Thermal Protection Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 7 Current Limit VSENSE Voltage Regulation ADJ/GND www.anpec.com.tw APL1581 Typical Application Circuit (1) Adjustable Output Voltage Device VIN VIN +3.3V VOUT VOUT +2.5V/5A APL1581 (Adj.) VCNTL VCNTL +5V VSENSE ADJ VREF R1 120 CIN 100µF CCNTL 10µF COUT 470µF R2 120 GND GND * VOUT = VREF ( 1+ R2 / R1 ) + IADJ x R2 where VREF =1.25V (typical) IADJ=50µA (typical) * R1 is typically in range of 100Ω to 125Ω to satisfy the minimum load current requirement. (2) Fixed Output Voltage Device VIN VIN VOUT VOUT +3.3V +2.5V/5A APL1581-25 VCNTL VCNTL +5V CCNTL 10µF VSENSE GND COUT 470µF CIN 100µF GND GND (3) With Enable Control Application VIN VIN +3.3V VCNTL +5V Q1 VCNTL 10k Q2 Enable VOUT VOUT +2.5V/5A APL1581 (Adj.) CCNTL 10µF VSENSE ADJ VREF R1 120 CIN 100µF COUT 470µF R2 120 10k GND GND Q1 : APM2301A Q2 : APM2300A Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 8 www.anpec.com.tw APL1581 Application Information General The recommended R1 is in range of 100Ω to125Ω to satisfy the minimum load current requirement. Proper The APL1581 (adjustable or fixed) regulator is a 5 terminal device designed specifically to provide extremely low sizes of R2 and R1 are also concerned for power dissipation. dropout voltages comparable to the PNP type without the disadvantage of the extra power dissipation due to the VIN base current associated with PNP regulators. This is done by bringing out the control pin of the regulator that pro- VIN VOUT APL1581 vides the base current to the power NPN and connecting it to a voltage that is greater than the voltage present at VCNTL VCNTL VSENSE ADJ VREF the VIN pin. This flexibility makes APL1581 ideal for applications where dual inputs are available, such as a comIADJ=50µA puter motherboard with an ATX power supply that provides 5V and 3.3V to the board. APL1581 is equipped with a 1.25V reference, precision and fast voltage regulations, on-chip current and thermal R1 R2 Figure 1. Setting Output Voltage limits, and remote sensing capability to reduce system total cost. Grounding and Output Sensing APL1581 is available in SOP-8P, TO-252-5, and TO-2635 packages to meet different power dissipation The APL1581 allows true Kelvin sensing for both the high and low side of the load. Figure 2 shows the device connected to take advantage of the remote sense feature. applications. The SENSE pin and the top of the resistor divider are connected to the top of the load; the bottom of the resistor Output Voltage Setting See Figure 1 Adjustable APL1581 develops a 1.25V ref- divider is connected to the bottom of the load. Typically, the load is a microprocessor and parasitic resistance RP erence voltage between the VSENSE pin and the ADJ pin. Placing a resistor between these two terminals causes a is made up of the PC traces and /or connector resistance between the regulator and the processor. RP is now con- constant current to flow through R1 and down through R2 to set the overall output voltage. In general, R1 is chosen nected inside the regulation loop of the APL1581 and for reasonable values of RP the load regulation at the load so that this current is the specified minimum load current of 10mA. The current out of the ADJ pin is small, typically will be negligible. Voltage drops due to RP are not eliminated; they will add to the dropout voltage of the regu- 50µA and itadds to the current from R1. Because IADJ is very small, it needs to be considered only when very pre- lator regardless of whether they are inside or outside the regulation loop. cise output voltage setting is required. For best regulation, the top of the resistor divider should be connected directly to the SENSE pin. The adjustable APL1581 can be programmable to any voltages in the range of 1.25V to VIN 5.5V according to the following formula: VOUT = VREF x (1+ VOUT VIN VOUT VOUT APL1581 VCNTL R2 ) + IADJ x R2 R1 VCNTL VSENSE ADJ Adjustable Device where VREF = 1.25V (typical) Load R1 R2 IADJ = 50µA (typical) RP Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 9 www.anpec.com.tw APL1581 Application Information (Cont.) Grounding and Output Sensing (Cont.) VIN VIN The output capacitors are also used to reduce the slew rate of load current and help the APL1581 to minimize variations of the output voltage, improving transient response. For this purpose, the low-ESR capacitors are VOUT VOUT APL1581 recommended. VCNTL VSENSE GND VCNTL Load Input Capacitors The input capacitors of VCNTL and VIN pins are not required for stability but for supplying surge currents during Fixed Voltage Device large load transients, and this will prevent the input rail from drooping and improve the performance of the RP APL1581. Because parasitic inductors from voltage sources or other bulk capacitors to the VCNTL and VIN Figure 2. Remote Voltage Sensing Stability and Output Capacitors pins will limit the slew rate of the surge currents during large load transients, resulting in voltage drop at VIN and The circuit design of using the APL1581 series requires an output capacitor as part of the device frequency VCNTL pins. A capacitor of 1µF (ceramic chip capacitor) or greater compensation. The following chart shows a stable region to select output capacitor for APL1581. This region (aluminum electrolytic capacitor) is recommended and connected near VCNTL pin. For VIN pin, an aluminum above the curve indicates minimum required ESR and capacitance to maintain stability. However, the output ca- electrolytic capacitor (>33µF) is recommended. It is not necessary to use low-ESR capacitors. More capacitance pacitor should have an ESR less than 1Ω. reduces the variations of the input voltage at VIN pin. Layout and Thermal Consideration 100 The APL1581 series have internal power and thermal 80 ESR (mΩ) limiting (TJ=150oC typical) circuitry designed to protect the device under overload conditions. However, maximum Stable Region 60 junction temperature ratings should not be exceeded under continuous normal load conditions. Careful con- 40 sideration must be given to all sources of thermal resistance from junction to ambient, including junction-to-case, 20 case-to-heat sink interface, and heat sink resistance itself. See Figure 3, the SOP-8P is a cost-effective package 0 1 10 100 1000 featuring a small size as a standard SOP-8 and a bottom thermal pad to minimize the thermal resistance of the Capacitance(µF) A low-ESR solid tantalum and aluminum electrolytic ca- package, being applicable to high current applications. The thermal pad is soldered to the top VOUT plane which pacitor (ESR<1Ω) works extremely well and provides good transient response and stability over temperature. Ultra- may be connected to internal or bottom VOUT plane by vias to reduce the heat sink thermal resistance. Therefore, low-ESR capacitors, such as ceramic chip capacitors, may promote unstable or under-damped transient response, the printed circuit board (PCB) forms a heat sink and dissipates heat into ambient air. but proper ceramic chip capacitors placed near loads can be used as decoupling capacitors. Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 10 www.anpec.com.tw APL1581 Application Information (Cont.) Layout and Thermal Consideration (Cont.) Top layer VOUT plane for Heat Dissipation (Larger area is better) COUT 8 7 6 5 Load Vias Vias 1 Soldering area (140mil x 110mil) for bottom pad 2 3 CCNTL 4 CIN Figure 3. Recommended SOP-8P Layout Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 11 www.anpec.com.tw APL1581 Package Information TO-263-5 A c2 E1 H D D1 L1 E b e c SEE VIEW A 0 SEATING PLANE L VIEW A A1 0.25 GAUGE PLANE TO-263-5 S Y M B O L MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 A1 0.00 0.25 0.000 0.010 b 0.51 0.99 0.020 0.039 c 0.38 0.74 0.015 0.029 c2 1.14 1.65 0.045 0.065 D 8.38 9.65 0.330 0.380 D1 6.00 9.00 0.236 0.354 E 9.65 11.43 0.380 0.450 E1 6.22 9.00 0.245 0.354 H 14.61 15.88 0.575 0.625 L 1.78 2.79 0.070 0.110 MILLIMETERS e 1.70 BSC L1 0 INCHES 0.067 BSC 0.066 1.68 0o 8 o 0o 8o Note : Follow JEDEC TO-263 BB. Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 12 www.anpec.com.tw APL1581 Package Information TO-252-5 E A c2 E1 H D D1 L3 b3 c b e SEE VIEW A 0 SEATING PLANE L A1 0.25 GAUGE PLANE VIEW A TO-252-5 S Y M B O L MIN. MAX. MIN. MAX. A 2.18 2.39 0.086 0.094 MILLIMETERS INCHES 0.005 0.13 A1 b 0.50 0.89 0.020 0.035 b3 4.32 5.46 0.170 0.215 0.018 0.024 c 0.46 0.61 c2 0.46 0.89 0.018 0.035 6.22 0.210 0.245 D 5.33 D1 4.57 6.00 0.180 0.236 E 6.35 6.73 0.250 0.265 E1 3.81 6.00 0.150 0.236 10.41 0.370 0.410 0.070 0.080 e H 1.27 BSC 9.40 0.050 BSC L 1.40 1.78 0.055 L3 0.89 2.03 0.035 0 0° 8° Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 0° 13 8° www.anpec.com.tw APL1581 Package Information TO-252-4 E A c2 E1 L4 H D D1 L3 b3 c e SEE VIEW A 0 GAUGE PLANE 0.25 S Y M B O L A VIEW A TO-252-4 MILLIMETERS INCHES MIN. MAX. MIN. MAX. 2.18 2.39 0.086 0.094 0.005 0.13 A1 b SEATING PLANE L A1 b 0.50 0.71 0.020 0.028 0.215 b3 4.32 5.46 0.170 c 0.46 0.61 0.018 0.024 c2 0.46 0.89 0.018 0.035 D 5.33 6.22 0.210 0.245 D1 4.57 6.00 0.180 0.236 E 6.35 6.73 0.250 0.265 E1 3.81 6.00 0.150 0.236 10.41 0.370 0.410 0.070 0.080 e H 1.27 BSC 9.40 0.050 BSC L 1.40 1.78 0.055 L3 0.89 2.03 0.035 L4 0 0.040 1.02 0° Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 8° 0° 14 8° www.anpec.com.tw APL1581 Package Information SOP-8P -T- SEATING PLANE < 4 mils D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE θ L VIEW A S Y M B O L A SOP-8P INCHES MILLIMETERS MAX. MIN. MIN. MAX. 1.60 A1 0.00 0.063 0.15 0.000 0.006 0.049 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 D1 2.50 3.50 0.098 0.138 E 5.80 6.20 0.228 0.244 0.157 0.118 E1 3.80 4.00 0.150 E2 2.00 3.00 0.079 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0o C 8o C θ 0oC 8o C Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 15 www.anpec.com.tw APL1581 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TO-252-4 Application TO-252-5 Application TO-263-5 Application SOP-8P A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.80±0.20 10.40±0.20 2.50±0.20 4.0±0.10 8.0±0.10 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.80±0.20 10.40±0.20 2.50±0.20 4.0±0.10 8.0±0.10 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 24.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 24.0±0.30 1.75±0.10 11.5±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 10.8±0.20 16.1±0.20 5.2±0.20 4.0±0.10 16.0±0.10 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 (mm) Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 16 www.anpec.com.tw APL1581 Devices Per Unit Package Type TO-252-4 TO-252-5 TO-263-5 SOP-8P Unit Type & Reel Type & Reel Type & Reel Type & Reel Devices Per Reel 2500 2500 800 2500 Taping Direction Information TO-252-4 USER DIRECTION OF FEED TO-252-5 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 17 www.anpec.com.tw APL1581 Taping Direction Information TO-263-5 USER DIRECTION OF FEED SOP-8P USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 18 www.anpec.com.tw APL1581 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 19 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APL1581 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 20 www.anpec.com.tw