INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4534B LSI Real time 5-decade counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4534B LSI Real time 5-decade counter scanner is triggered by a LOW to HIGH transition on the scanner clock (CPS) and is reset (select ten thousand counter) by a HIGH level on the scanner reset (MRsc). DESCRIPTION The HEF4534B is a 5-decade ripple counter. The binary outputs of the decade counters are time-multiplexed by an internal scanner on four BCD outputs (O0 to O3). The selected decade is indicated by a logic HIGH on the appropriate digit select output (OS0: units, 1; OS1: tens, 10; OS2: hundreds, 102; OS3: thousands, 103; OS4: ten thousands, 104). The counter can operate in four modes depending on the state of the mode select inputs (SA, SB). The error detector will detect an error when a positive edge on CPA is not accompanied by a negative edge on the error detector clock CPE or vice versa, within time limits adjusted by external capacitors connected to Cext 1 and Cext 2. Three or more detected errors result in a HIGH level on the error output (OER). The error detector is reset by a HIGH level on MR. The binary outputs (O0 to O3) and the select outputs (OS0 to OS4) are 3-state controlled via enable inputs EO and EOS respectively, allowing interface with other bus orientated devices. Cascading may be accomplished by using the carry out (TC). The counter is triggered by a LOW to HIGH transition on the decade clock (CPA) and is reset by a HIGH level on the master reset (MR). The Schmitt-trigger action in the clock inputs makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Pinning diagram. PINNING HEF4534BP(N): 24-lead DIL; plastic (SOT101-1) O1 to O3 HEF4534BD(F): 24-lead DIL; ceramic (cerdip) (SOT94) OS0 to OS3 digit select outputs HEF4534BT(D): 24-lead SO; plastic (SOT137-1) OER error output CPA decade clock input CPS scanner clock input CPE error detector clock input SA, SB mode select inputs MR master reset input MRsc scanner reset input TC carry out ( ): Package Designator North America BCD outputs FAMILY DATA, IDD LIMITS category LSI See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4534B LSI Real time 5-decade counter Fig.2 Functional block diagram. January 1995 3 Philips Semiconductors Product specification HEF4534B LSI Real time 5-decade counter MODE CONTROL FUNCTION TABLE SELECT INPUTS SA SB L L L H 1ST DECADE OUTPUT CARRY TO 2ND STAGE CARRY TO 4TH STAGE MODE normal count at 9 to 0 transition at 9 to 0 transition 5-decade and display of the 1st decade of the 3rd decade counter inhibited input clock input clock test purposes: clock directly into stages 1, 2 and 4 4-decade counter H H inhibited at 4 to 5 transition of the 1st decade at 9 to 0 transition of the 3rd decade with ÷ 10 and roundoff at front end display counts: H L 3, 4, 5, 6, 7 = 5 at 7 to 8 transition of the 1st decade at 9 to 0 transition of the 3rd decade 8, 9, 0, 1, 2 = 0 4-decade counter; 2-pence capability 1⁄ Fig.3 Error detection timing diagram. the error detector clock CPE within a skew time tSK1 (adjustable by Cext1 at pin 1). The same holds for a negative edge at CPE succeeded by a positive on CPA within a skew time tSK2 (adjustable by Cext2 at pin 22). If error detection is not needed, CPE must be either HIGH or LOW and no Cext is applied. For further information see Fig.5. The skew time is the time difference between the LOW to HIGH transition of CPA and the HIGH to LOW transition of CPE or vice versa (see Fig.4). The skew time is typically proportional to the external capacitor (Cext) connected from Cext1 and Cext2 (pins 1 and 22) to VSS. The error detector will count an error when a positive edge on the counter clock CPA is not succeeded by a negative edge on Fig.4 Skew times timing diagram; tWCPA > tSK1; tWCPE > tSK2. January 1995 4 Philips Semiconductors Product specification HEF4534B LSI Real time 5-decade counter Note 1: Skew in this area results in counted error. Note 2: Skew in the area between max. and min. curves may or may not result in counted error. Note 3: Skew in this area results in no error counted. Fig.5 Typical clock skew as a function of the supply voltage. This graph is accurate for Cext ≥ 100 pF and Tamb = 25 °C. Fig.6 Carry timing diagram. January 1995 5 Philips Semiconductors Product specification HEF4534B LSI Real time 5-decade counter Note: If SB = H, the 1st decade is inhibited and the cycle will be shortened to four stages (see dotted lines). Fig.7 Scanner timing diagram. Fig.8 Counter timing diagram. January 1995 6 Philips Semiconductors Product specification HEF4534B LSI Real time 5-decade counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays CPA → On 5 D1 selected 10 HIGH to LOW 15 LOW to HIGH 10 tPHL 5 tPLH 15 CPA → On 5 D5 selected 10 HIGH to LOW 15 LOW to HIGH 10 tPHL 5 tPLH 15 CPA → TC LOW to HIGH MR → On HIGH to LOW MR → OER HIGH to LOW CPS → On HIGH to LOW LOW to HIGH CPS → OSn HIGH to LOW CPS → OSn LOW to HIGH 600 ns 283 ns + (0,55 ns/pF) CL 260 ns 119 ns + (0,23 ns/pF) CL 95 190 ns 87 ns + (0,16 ns/pF) CL 240 480 ns 213 ns + (0,55 ns/pF) CL 100 200 ns 89 ns + (0,23 ns/pF) CL 75 150 ns 67 ns + (0,16 ns/pF) CL 550 1100 ns 523 ns + (0,55 ns/pF) CL 230 460 ns 219 ns + (0,23 ns/pF) CL 170 340 ns 162 ns + (0,16 ns/pF) CL 550 1100 ns 523 ns + (0,55 ns/pF) CL 230 460 ns 219 ns + (0,23 ns/pF) CL 170 340 ns 162 ns + (0,16 ns/pF) CL 420 840 ns 393 ns + (0,55 ns/pF) CL 190 380 ns 179 ns + (0,23 ns/pF) CL 15 140 280 ns 132 ns + (0,16 ns/pF) CL 5 200 400 ns 173 ns + (0,55 ns/pF) CL 5 10 tPLH 85 170 ns 74 ns + (0,23 ns/pF) CL 15 60 120 ns 52 ns + (0,16 ns/pF) CL 5 140 280 ns 113 ns + (0,55 ns/pF) CL 10 tPHL 65 130 ns 54 ns + (0,23 ns/pF) CL 15 50 100 ns 42 ns + (0,16 ns/pF) CL 5 225 450 ns 198 ns + (0,55 ns/pF) CL 10 tPHL 95 190 ns 84 ns + (0,23 ns/pF) CL 15 70 140 ns 62 ns + (0,16 ns/pF) CL 5 225 450 ns 198 ns + (0,55 ns/pF) CL 10 tPHL 95 190 ns 84 ns + (0,23 ns/pF) CL 15 70 140 ns 62 ns + (0,16 ns/pF) CL 5 170 340 ns 143 ns + (0,55 ns/pF) CL 10 tPLH 70 140 ns 59 ns + (0,23 ns/pF) CL 15 50 100 ns 42 ns + (0,16 ns/pF) CL 5 170 340 ns 143 ns + (0,55 ns/pF) CL 70 140 ns 59 ns + (0,23 ns/pF) CL 50 100 ns 42 ns + (0,16 ns/pF) CL 10 10 tPHL tPLH 15 January 1995 300 130 7 Philips Semiconductors Product specification HEF4534B LSI Real time 5-decade counter VDD V Output transition times HIGH to LOW LOW to HIGH SYMBOL MIN. TYP. 5 TYPICAL EXTRAPOLATION FORMULA MAX. 60 120 ns 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 tTHL 10 tTLH 15 10 ns + (1,0 ns/pF) CL AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. MAX. 3-state propagation delays Output disable times EO → On; 5 30 60 ns 25 50 ns EOS → OSn 10 HIGH 15 20 40 ns 5 40 80 ns 25 50 ns 15 20 40 ns 5 35 70 ns LOW 10 tPHZ tPLZ Output enable times EO → On; EOS → OSn 10 20 40 ns HIGH 15 15 30 ns 5 50 100 ns 25 50 ns 15 30 ns LOW 10 tPZH tPZL 15 Minimum clock pulse 5 width; CPA, CPS 10 HIGH tWCPH 70 35 ns 40 20 ns 15 30 15 ns Minimum reset pulse 5 90 45 ns width; MR, MRsc 10 60 30 ns 15 40 20 ns 5 120 60 ns 60 30 ns 15 50 25 ns 5 60 30 ns 40 20 ns 30 15 ns HIGH Recovery time for MR Recovery time for MRsc 10 10 15 January 1995 tWMRH tRMR tRMR 8 Philips Semiconductors Product specification HEF4534B LSI Real time 5-decade counter VDD V Maximum clock 5 pulse frequency 10 CPA and CPS 15 Dynamic power SYMBOL MIN. TYP. MAX. 2,5 5 MHz 6 12 MHz 8 16 MHz fmax VDD V TYPICAL FORMULA FOR P (µW) 5 1 100 fi + ∑ (foCL) × VDD2 where fi = input freq. (MHz) dissipation per 10 4 800 fi + ∑ (foCL) × package (P)(1) 15 12 000 fi + ∑ (foCL) × VDD2 VDD2 fo = output freq. (MHz) CL = load cap. (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) Note 1. Cext = 0. January 1995 9 Philips Semiconductors Product specification HEF4534B LSI Real time 5-decade counter APPLICATION INFORMATION Fig.9 Two HEF4534B ICs connected for cascade operation. TC is HIGH for a single clock period when all five BCD decades go to zero. TC also goes HIGH when MR is applied. Fig.10 Forcing a decade to the On outputs. When the On outputs of a given decade are required, this configuration will lock-up the selected decade within four clock cycles. The select line feed back may be hardwired or switched. January 1995 10