High Speed, Dual, 4 A MOSFET Driver ADP3654 FEATURES GENERAL DESCRIPTION Industry-standard-compatible pinout High current drive capability Precise UVLO comparator with hysteresis 3.3 V-compatible inputs 10 ns typical rise time and fall time at 2.2 nF load Matched propagation delays between channels Fast propagation delay 4.5 V to 18 V supply voltage Parallelable dual outputs Rated from −40°C to +125°C junction temperature Thermally enhanced packages, 8-lead SOIC_N_EP and 8-lead MINI_SO_EP The ADP3654 high current and dual high speed driver is capable of driving two independent N-channel power MOSFETs. The driver uses the industry-standard footprint but adds high speed switching performance. APPLICATIONS The driver is available in thermally enhanced SOIC_N_EP and MINI_SO_EP packaging to maximize high frequency and current switching in a small printed circuit board (PCB) area. The wide input voltage range allows the driver to be compatible with both analog and digital PWM controllers. Digital power controllers are powered from a low voltage supply, and the driver is powered from a higher voltage supply. The ADP3654 driver adds UVLO and hysteresis functions, allowing safe startup and shutdown of the higher voltage supply when used with low voltage digital controllers. AC-to-dc switch mode power supplies DC-to-dc power supplies Synchronous rectification Motor drives FUNCTIONAL BLOCK DIAGRAM NC 1 ADP3654 8 NC 7 OUTA 6 VDD 5 OUTB VDD INA 2 PGND 3 UVLO 09054-001 INB 4 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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ADP3654 TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuit .........................................................................................8 Applications....................................................................................... 1 Theory of Operation .........................................................................9 General Description ......................................................................... 1 Input Drive Requirements (INA and INB)................................9 Functional Block Diagram .............................................................. 1 Low-Side Drivers (OUTA, OUTB) .............................................9 Revision History ............................................................................... 2 Supply Capacitor Selection ..........................................................9 Specifications..................................................................................... 3 PCB Layout Considerations.........................................................9 Timing Diagrams.......................................................................... 3 Parallel Operation ...................................................................... 10 Absolute Maximum Ratings............................................................ 4 Thermal Considerations............................................................ 10 ESD Caution.................................................................................. 4 Outline Dimensions ....................................................................... 12 Pin Configuration and Function Descriptions............................. 5 Ordering Guide .......................................................................... 12 Typical Performance Characteristics ............................................. 6 REVISION HISTORY 8/10—Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADP3654 SPECIFICATIONS VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted. 1 Table 1. Parameter SUPPLY Supply Voltage Range Supply Current UVLO Turn-On Threshold Voltage Turn-Off Threshold Voltage Hysteresis DIGITAL INPUTS (INA, INB) Input Voltage High Input Voltage Low Input Current Internal Pull-Up/Pull-Down Current OUTPUTS (OUTA, OUTB) Output Resistance, Unbiased Peak Source Current Peak Sink Current SWITCHING TIME OUTA and OUTB Rise Time OUTA and OUTB Fall Time OUTA and OUTB Rising Propagation Delay OUTA and OUTB Falling Propagation Delay Delay Matching Between Channels 1 Symbol Test Conditions/Comments VDD IDD No switching VUVLO_ON VUVLO_OFF VDD rising, TJ = 25°C, see Figure 3 VDD falling, TJ = 25°C, see Figure 3 3.8 3.5 VIH VIL IIN See Figure 2 See Figure 2 0 V < VIN < VDD 2.0 tRISE tFALL tD1 tD2 Min 18 3 V mA 4.5 4.3 V V V 6 VDD = PGND See Figure 14 See Figure 14 80 4 −4 kΩ A A CLOAD = 2.2 nF, see Figure 2 CLOAD = 2.2 nF, see Figure 2 CLOAD = 2.2 nF, see Figure 2 CLOAD = 2.2 nF, see Figure 2 10 10 14 22 2 0.8 +20 −20 VIL tRISE tD2 tFALL 90% 90% 09054-002 10% 10% Figure 2. Output Timing Diagram VUVLO_ON VUVLO_OFF NORMAL OPERATION OUTPUTS DISABLED UVLO MODE OUTPUTS DISABLED Figure 3. UVLO Function Rev. 0 | Page 3 of 12 09054-003 VDD UVLO MODE 1.2 V V μA μA VIH OUTA, OUTB Unit 4.2 3.9 0.3 TIMING DIAGRAMS tD1 Max 4.5 All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods. INA, INB Typ 25 25 30 35 ns ns ns ns ns ADP3654 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD OUTA, OUTB DC <200 ns INA, INB ESD Human Body Model (HBM) Field Induced Charged Device Model (FICDM) SOIC_N_EP MINI_SO_EP θJA, JEDEC 4-Layer Board SOIC_N_EP1 MINI_SO_EP1 Junction Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to +20 V −0.3 V to VDD + 0.3 V −2 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V 3.5 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 1.5 kV 1.0 kV 59°C/W 43°C/W −40°C to +150°C −65°C to +150°C 300°C 215°C 260°C θJA is measured per JEDEC standards, JESD51-2, JESD51-5, and JESD51-7, as appropriate with the exposed pad soldered to the PCB. Rev. 0 | Page 4 of 12 ADP3654 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 8 ADP3654 NC OUTA TOP VIEW PGND 3 (Not to Scale) 6 VDD INB 4 5 OUTB 7 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE. IT IS RECOMMENDED TO HAVE THE EXPOSED PAD AND THE PGND PIN CONNECTED ON THE PCB. 09054-004 INA 2 Figure 4. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic NC INA PGND INB OUTB VDD OUTA NC EPAD Description No Connect. Input Pin for Channel A Gate Driver. Ground. This pin should be closely connected to the source of the power MOSFET. Input Pin for Channel B Gate Driver. Output Pin for Channel B Gate Driver. Power Supply Voltage. Bypass this pin to PGND with a ~1 μF to 5 μF ceramic capacitor. Output Pin for Channel A Gate Driver. No Connect. Exposed Pad. The exposed pad of the package is not directly connected to any pin of the package, but it is electrically and thermally connected to the die substrate, which is the ground of the device. It is recommended to have the exposed pad and the PGND pin connected on the PCB. Rev. 0 | Page 5 of 12 ADP3654 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 12 V, TJ = 25°C, unless otherwise noted. 25 9 V UVLO_ON 8 20 V UVLO_OFF TIME (ns) 6 15 tFALL 10 tRISE 5 5 4 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 0 09054-005 3 –50 0 Figure 5. UVLO vs. Temperature 5 10 VDD (V) 15 20 09054-008 UVLO (V) 7 Figure 8. Rise and Fall Times vs. VDD 70 14 60 12 tFALL 50 10 TIME (ns) TIME (ns) tRISE 8 6 40 30 tD2 20 4 tD1 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 0 09054-006 0 –50 0 Figure 6. Rise and Fall Times vs. Temperature 5 10 VDD (V) 15 20 Figure 9. Propagation Delay vs. VDD 60 VDD = 12V 50 OUTA/OUTB 30 tD2 2 20 tD1 INA/INB 0 –50 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 1 Figure 7. Propagation Delay vs. Temperature VDD = 12V TIME = 20ns/DIV Figure 10. Typical Rise Propagation Delay Rev. 0 | Page 6 of 12 09054-010 10 09054-007 TIME (ns) 40 09054-009 10 2 ADP3654 OUTA/OUTB OUTA/OUTB 2 INA/INB INA/INB 1 Figure 11. Typical Fall Propagation Delay Figure 13. Typical Fall Time OUTA/OUTB 2 VDD = 12V TIME = 20ns/DIV 09054-012 INA/INB 1 VDD = 12V TIME = 20ns/DIV Figure 12. Typical Rise Time Rev. 0 | Page 7 of 12 09054-013 VDD = 12V TIME = 20ns/DIV 09054-011 1 2 ADP3654 TEST CIRCUIT 1 2 NC INA NC 8 SCOPE PROBE ADP3654 A OUTA 7 VDD 3 PGND VDD 6 4.7µF CERAMIC INB B OUTB CLOAD 5 09054-014 4 100nF CERAMIC Figure 14. Test Circuit Rev. 0 | Page 8 of 12 ADP3654 THEORY OF OPERATION The ADP3654 dual driver is optimized for driving two independent enhancement N-channel MOSFETs or insulated gate bipolar transistors (IGBTs) in high switching frequency applications. LOW-SIDE DRIVERS (OUTA, OUTB) These applications require high speed, fast rise and fall times, as well as short propagation delays. The capacitive nature of the aforementioned gated devices requires high peak current capability as well. When ADP3654 is disabled, both low-side gates are held low. Internal impedance is present between the OUTA pin and GND and between the OUTB pin and GND; this feature ensures that the power MOSFET is normally off when bias voltage is not present. 1 2 NC INA NC 8 ADP3654 A VDS OUTA When interfacing ADP3654 to external MOSFETs, the designer should consider ways to make a robust design that minimizes stresses on both the driver and the MOSFETs. These stresses include exceeding the short time duration voltage ratings on the OUTA and OUTB pins, as well as the external MOSFET. 7 VDD 3 PGND VDD 6 VDS INB B OUTB Power MOSFETs are usually selected to have a low on resistance to minimize conduction losses, which usually implies a large input gate capacitance and gate charge. 5 SUPPLY CAPACITOR SELECTION 09054-015 4 The ADP3654 dual drivers are designed to drive ground referenced N-channel MOSFETs. The bias is internally connected to the VDD supply and PGND. INPUT DRIVE REQUIREMENTS (INA AND INB) For the supply input (VDD) of the ADP3654, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents that are drawn. The ADP3654 is designed to meet the requirements of modern digital power controllers; the signals are compatible with 3.3 V logic levels. At the same time, the input structure allows for input voltages as high as VDD. An improper decoupling can dramatically increase the rise times because excessive resonance on the OUTA and OUTB pins can, in some extreme cases, damage the device, due to inductive overvoltage on the VDD, OUTA, or OUTB pin. An internal pull-down resistor is present at the input, which guarantees that the power device is off in the event that the input is left floating. The minimum capacitance required is determined by the size of the gate capacitances being driven, but as a general rule, a 4.7 μF, low ESR capacitor should be used. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Use a smaller ceramic capacitor (100 nF) with a better high frequency characteristic in parallel to the main capacitor to further reduce noise. Figure 15. Typical Application Circuit Keep the ceramic capacitor as close as possible to the ADP3654 device and minimize the length of the traces going from the capacitor to the power pins of the device. PCB LAYOUT CONSIDERATIONS Use the following general guidelines when designing PCBs: • • • • • Rev. 0 | Page 9 of 12 Trace out the high current paths and use short, wide (>40 mil) traces to make these connections. Minimize trace inductance between the OUTA and OUTB outputs and MOSFET gates. Connect the PGND pin of the ADP3654 device as closely as possible to the source of the MOSFETs. Place the VDD bypass capacitor as close as possible to the VDD and PGND pins. Use vias to other layers, when possible, to maximize thermal conduction away from the IC. ADP3654 Figure 16 shows an example of the typical layout based on the preceding guidelines. THERMAL CONSIDERATIONS When designing a power MOSFET gate drive, the maximum power dissipation in the driver must be considered to avoid exceeding maximum junction temperature. Data on package thermal resistance is provided in Table 2 to help the designer with this task. 09054-016 There are several equally important aspects that must be considered, such as the following: Figure 16. External Component Placement Example Note that the exposed pad of the package is not directly connected to any pin of the package, but it is electrically and thermally connected to the die substrate, which is the ground of the device. PARALLEL OPERATION The two driver channels present in the ADP3654 device can be combined to operate in parallel to increase drive capability and minimize power dissipation in the driver. The connection scheme is shown in Figure 17. In this configuration, INA and INB are connected together, and OUTA and OUTB are connected together. Particular attention must be paid to the layout in this case to optimize load sharing between the two drivers. 1 NC NC • • • • • • All of these factors influence and limit the maximum allowable power dissipated in the driver. The gate of a power MOSFET has a nonlinear capacitance characteristic. For this reason, although the input capacitance is usually reported in the MOSFET data sheet as CISS, it is not useful to calculate power losses. The total gate charge necessary to turn on a power MOSFET device is usually reported on the device data sheet under QG. This parameter varies from a few nanocoulombs (nC) to several hundred nC, and is specified at a specific VGS value (10 V or 4.5 V). The power necessary to charge and then discharge the gate of a power MOSFET can be calculated as: 8 PGATE = VGS × QG × fSW ADP3654 2 INA A OUTA where: VGS is the bias voltage powering the driver (VDD). QG is the total gate charge. fSW is the maximum switching frequency. 7 VDD 3 PGND VDD 6 VDS INB B OUTB 5 09054-017 4 Figure 17. Parallel Operation Gate charge of the power MOSFET being driven Bias voltage value used to power the driver Maximum switching frequency of operation Value of external gate resistance Maximum ambient (and PCB) temperature Type of package The power dissipated for each gate (PGATE) still needs to be multiplied by the number of drivers (in this case, 1 or 2) being used in each package, and it represents the total power dissipated in charging and discharging the gates of the power MOSFETs. Not all of this power is dissipated in the gate driver because part of it is actually dissipated in the external gate resistor, RG. The larger the external gate resistor is, the smaller the amount of power that is dissipated in the gate driver. In modern switching power applications, the value of the gate resistor is kept at a minimum to increase switching speed and minimize switching losses. In all practical applications where the external resistor is in the order of a few ohms, the contribution of the external resistor can be neglected, and the extra loss is assumed in the driver, providing a good guard band to the power loss calculations. Rev. 0 | Page 10 of 12 ADP3654 The SOIC_N_EP thermal resistance is 59°C/W. In addition to the gate charge losses, there are also dc bias losses, due to the bias current of the driver. This current is present regardless of the switching. ΔTJ = 878.4 mW × 59°C/W = 51.8°C TJ = TA + ΔTJ = 136.8°C ≤ TJMAX PDC = VDD × IDD This estimated junction temperature does not factor in the power dissipated in the external gate resistor and, therefore, provides a certain guard band. The total estimated loss is the sum of PDC and PGATE. PLOSS = PDC + (n × PGATE) If a lower junction temperature is required by the design, the MINI_SO_EP package can be used, which provides a thermal resistance of 43°C/W, so that the maximum junction temperature is where n is the number of gates driven. When the total power loss is calculated, the temperature increase can be calculated as ΔTJ = PLOSS × θJA ΔTJ = 878.4 mW × 43°C/W = 37.7°C Design Example For example, consider driving two IRFS4310Z MOSFETs with a VDD of 12 V at a switching frequency of 300 kHz, using an ADP3654 in the SOIC_N_EP package. The maximum PCB temperature considered for this design is 85°C. TJ = TA + ΔTJ = 122.7°C ≤ TJMAX Other options to reduce power dissipation in the driver include reducing the value of the VDD bias voltage, reducing switching frequency, and choosing a power MOSFET with smaller gate charge. From the MOSFET data sheet, the total gate charge is QG = 120 nC. PGATE = 12 V × 120 nC × 300 kHz = 432 mW PDC = 12 V × 1.2 mA = 14.4 mW PLOSS = 14.4 mW + (2 × 432 mW) = 878.4 mW Rev. 0 | Page 11 of 12 ADP3654 OUTLINE DIMENSIONS 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 8 2.29 (0.090) 5 2.29 (0.090) 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) TOP VIEW 1 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 4 BOTTOM VIEW 1.27 (0.05) BSC (PINS UP) 1.75 (0.069) 1.35 (0.053) 1.65 (0.065) 1.25 (0.049) 0.10 (0.004) MAX COPLANARITY 0.10 SEATING PLANE 0.51 (0.020) 0.31 (0.012) 0.50 (0.020) 0.25 (0.010) 0.25 (0.0098) 0.17 (0.0067) 45° 1.27 (0.050) 0.40 (0.016) 8° 0° COMPLIANT TO JEDEC STANDARDS MS-012-A A 072808-A CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 18. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters and (inches) 3.10 3.00 2.90 5 8 TOP VIEW 1 EXPOSED PAD 4 PIN 1 INDICATOR 0.525 BSC 0.65 BSC 0.94 0.86 0.78 0.15 0.10 0.05 COPLANARITY 0.10 5.05 4.90 4.75 1.10 MAX SEATING PLANE 0.40 0.33 0.25 BOTTOM VIEW 1.83 1.73 1.63 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.23 0.18 0.13 8° 0° 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-AA-T 071008-A 3.10 3.00 2.90 2.26 2.16 2.06 Figure 19. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP] (RH-8-1) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP3654ARDZ-RL UVLO Option 4.5 V Temperature Range −40°C to +125°C ADP3654ARHZ-RL 4.5 V −40°C to +125°C 1 Package Description 8-Lead Standard Small Outline Package (SOIC_N_EP), 13“ Tape and Reel 8-Lead Mini Small Outline Package (MINI_SO_EP), 13” Tape and Reel Z = RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09054-0-8/10(0) Rev. 0 | Page 12 of 12 Package Option RD-8-1 Ordering Quantity 2,500 Branding RH-8-1 3,000 78