ON MMFT3055V Power mosfet Datasheet

MMFT3055V
Power MOSFET
1 Amp, 60 Volts
N−Channel SOT−223
These Power MOSFETs are designed for low voltage, high speed
switching applications in power supplies, converters and power motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
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1 AMPERE, 60 VOLTS
RDS(on) = 130 mW
N−Channel
Features
D
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Pb−Free Package is Available
G
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
S
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MW)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 25
Vdc
Vpk
ID
ID
Adc
IDM
1.7
1.4
6.0
Total PD @ TA = 25°C mounted on 1″ sq.
Drain pad on FR−4 bd material
Total PD @ TA = 25°C mounted on
0.70″ sq. Drain pad on FR−4 bd material
Total PD @ TA = 25°C mounted on min.
Drain pad on FR−4 bd material
Derate above 25°C
PD
2.1
W
Operating and Storage Temperature Range
TJ, Tstg
Rating
Drain Current − Continuous
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp ≤ 10 ms)
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 3.4 Apk, L = 10 mH, RG = 25 W )
Thermal Resistance
− Junction to Ambient on 1″ sq.
Drain padon FR−4 bd material
− Junction to Ambient on 0.70″ sq.
Drain pad on FR−4 bd material
− Junction to Ambient on min.
Drain pad on FR−4 bd material
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 s
1
Apk
August, 2006 − Rev. 4
2
MARKING DIAGRAM AND
PIN ASSIGNMENT
4 Drain
AYW
V3055 G
G
0.94
6.3
mW/°C
−55 to
175
°C
EAS
1
Gate
2
Drain
3
Source
mJ
58
RqJA
70
RqJA
88
RqJA
159
TL
TO−261AA
CASE 318E
STYLE 3
3
1.7
°C/W
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
V3055 = Device Code
(Note: Microdot may be in either location)
ORDERING INFORMATION
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
© Semiconductor Components Industries, LLC, 2006
4
1
Shipping†
Device
Package
MMFT3055VT1
SOT−223
1000 Tape & Reel
MMFT3055VT1G
SOT−223
(Pb−Free)
1000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
MMFT3055V/D
MMFT3055V
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
60
−
−
63
−
−
Vdc
mV/°C
−
−
−
−
10
100
−
−
100
nAdc
2.0
−
2.8
5.6
4.0
−
Vdc
mV/°C
−
0.115
0.13
−
−
−
−
0.27
0.25
gFS
1.0
2.7
−
mhos
Ciss
−
360
500
pF
Coss
−
110
150
Crss
−
25
50
td(on)
−
8.0
20
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (Note 3)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
mAdc
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
(Cpk ≥ 2.0) (Note 3)
VGS(th)
Static Drain−to−Source On−Resistance
(VGS = 10 Vdc, ID = 0.85 Adc)
(Cpk ≥ 2.0) (Note 3)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 1.7 Adc)
(VGS = 10 Vdc, ID = 0.85 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (VDS = 8.0 Vdc, ID = 1.7 Adc)
W
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 30 Vdc, ID = 1.7 Adc,
VGS = 10 Vdc, RG = 9.1 W)
Fall Time
Gate Charge
(VDS = 48 Vdc, ID = 1.7 Adc,
VGS = 10 Vdc)
tr
−
9.0
20
td(off)
−
32
60
tf
−
18
40
QT
−
13
20
Q1
−
2.0
−
Q2
−
5.0
−
Q3
−
4.0
−
−
−
0.85
0.7
1.6
−
trr
−
40
−
ta
−
34
−
tb
−
6.0
−
QRR
−
0.089
−
−
4.5
−
−
7.5
−
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 1)
(IS = 1.7 Adc, VGS = 0 Vdc)
(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 1.7 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
VSD
Vdc
ns
mC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
Max limit − Typ
3. Reflects typical values.
Cpk =
3 x SIGMA
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2
nH
nH
MMFT3055V
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
7V
6V
I D , DRAIN CURRENT (AMPS)
3.5
3
4
TJ = 25°C
5V
5.5 V
2.5
2
4.5 V
1.5
1
0
3
2.5
2
1.5
0.5
3.5 V
0
6
7
8
3
4
5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
9
2
100°C
25°C
1
4V
0.5
VDS ≥ 10 V
3.5
I D , DRAIN CURRENT (AMPS)
4
0
10
TJ = −55°C
2
3
2.5
0.2
0.15
25°C
0.1
7
7.5
0.125
VGS = 10 V
0.110
15 V
0.065
0.025
0
0.5
1
1.5
3
2.5
2
ID, DRAIN CURRENT (AMPS)
0.050
4
3.5
0
Figure 3. On−Resistance versus Drain Current
and Temperature
2.0
1.8
1
0.5
1.5
3
2
2.5
ID, DRAIN CURRENT (AMPS)
3.5
4
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
VGS = 10 V
ID = 0.85 A
VGS = 0 V
1.6
1.4
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
6.5
0.080
0.05
0
6
0.095
−55°C
0.075
5.5
0.140
TJ = 100°C
0.125
5
TJ = 25°C
0.155
0.175
4.5
0.170
VGS = 10 V
0.225
4
Figure 2. Transfer Characteristics
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 1. On−Region Characteristics
0.25
3.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1.2
1.0
0.8
0.6
TJ = 125°C
100
100°C
0.4
0.2
0
−50
−25
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
150
10
175
0
Figure 5. On−Resistance Variation with
Temperature
5
10 15 20 25 30 35 40 45 50
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
55
60
MMFT3055V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
1100
TJ = 25°C
Ciss
900
C, CAPACITANCE (pF)
VGS = 0 V
VDS = 0 V
1000
800
700
Crss
600
500
Ciss
400
300
Coss
200
Crss
100
0
10
5
0
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
30
9
27
QT
8
24
7
21
VGS
6
Q1
18
Q2
5
15
4
12
3
9
ID = 1.7 A
TJ = 25°C
2
1
0
Q3
0
2
VDS
4
6
10
8
12
6
3
0
14
1000
t, TIME (ns)
10
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MMFT3055V
VDD = 30 V
ID = 1.7 A
VGS = 10 V
TJ = 25°C
100
td(off)
tf
tr
10
1
td(on)
1
10
100
RG, GATE RESISTANCE (OHMS)
QT, TOTAL CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
2
VGS = 0 V
TJ = 25°C
I S , SOURCE CURRENT (AMPS)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.5
0.55
0.6
0.7
0.65
0.75
0.8
0.85
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
MMFT3055V
SAFE OPERATING AREA
60
VGS = 20 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
10
10 ms
1
100 ms
500 ms
0.1
1s
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1.0
10
40
30
20
10
0
100
25
50
75
100
125
150
175
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
dc
ID = 1.7 A
50
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.001
SINGLE PULSE
0.0001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
1.0E+01
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
1.0E+02
1.0E+03
MMFT3055V
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
D
b1
4
HE
1
2
3
E
b
e1
e
C
q
A
0.08 (0003)
DIM
A
A1
b
b1
c
D
E
e
e1
L1
HE
A1
L1
MIN
1.50
0.02
0.60
2.90
0.24
6.30
3.30
2.20
0.85
1.50
6.70
0°
q
STYLE 3:
PIN 1.
2.
3.
4.
MILLIMETERS
NOM
MAX
1.63
1.75
0.06
0.10
0.75
0.89
3.06
3.20
0.29
0.35
6.50
6.70
3.50
3.70
2.30
2.40
0.94
1.05
1.75
2.00
7.00
7.30
10°
−
MIN
0.060
0.001
0.024
0.115
0.009
0.249
0.130
0.087
0.033
0.060
0.264
0°
INCHES
NOM
0.064
0.002
0.030
0.121
0.012
0.256
0.138
0.091
0.037
0.069
0.276
−
MAX
0.068
0.004
0.035
0.126
0.014
0.263
0.145
0.094
0.041
0.078
0.287
10°
GATE
DRAIN
SOURCE
DRAIN
SOLDERING FOOTPRINT*
3.8
0.15
2.0
0.079
2.3
0.091
2.3
0.091
6.3
0.248
2.0
0.079
1.5
0.059
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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