AD AD7091R-4BRUZ-RL7 2-/4-/8-channel, 1 msps, ultralow power, 12-bit sar adc Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
Ultralow system power
Flexible power/throughput rate management
Normal mode
1.4 mW at 1 MSPS
Power-down mode
550 nA typical at VDD = 5.25 V
435 nA typical at VDD = 3 V
Programmable ALERT interrupt pin (4-/8-channel models)
High performance
1 MSPS throughput with no latency/pipeline delay
SNR: 70 dB typical at 10 kHz input frequency
THD: −80 dB typical at 10 kHz input frequency
INL: ±0.7 LSB typical, ±1.0 LSB maximum
Small system footprint
On-chip accurate 2.5 V reference, 5 ppm/°C typical drift
MUXOUT/ADCIN to allow single buffer amplifier
Daisy-chain mode
16-lead, 20-lead, and 24-lead 4 mm × 4 mm LFCSP packages
16-lead, 20-lead, and 24-lead TSSOP packages
Easy to use
SPI/QSPI™/MICROWIRE™/DSP compatible digital interface
Integrated programmable channel sequencer
BUSY indication available (4-/8-channel models)
Built in features for control and monitoring applications
GPOx pins available (4-/8-channel models)
Wide operating range
Temperature range: −40°C to +125°C
Specified for VDD of 2.7 V to 5.25 V
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
Diagnostic/monitoring functions
Rev. C
MUXOUT
ADCIN
VDD
REFIN/
REFOUT
2.5V
VREF
VIN0
VIN1
T/H
VIN2
REGCAP
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
VDRIVE
VIN3
VIN4
I/P
MUX
RESET
VIN5
CONVST
ON-CHIP
OSC
VIN6
VIN7
SDO
CONTROL LOGIC
AND REGISTERS
SDI
SCLK
CS
CHANNEL
SEQUENCER
AD7091R-8
GND
ALERT/
BUSY/
GPO0
GPO1
GND
10891-001
Data Sheet
2-/4-/8-Channel, 1 MSPS,
Ultralow Power, 12-Bit SAR ADC
AD7091R-2/AD7091R-4/AD7091R-8
Figure 1.
GENERAL DESCRIPTION
The AD7091R-2/AD7091R-4/AD7091R-8 family is a multichannel
12-bit, ultralow power, successive approximation analog-todigital converter (ADC) that is available in two, four, or eight
analog input channel options. The AD7091R-2/AD7091R-4/
AD7091R-8 operate from a single 2.7 V to 5.25 V power supply
and are capable of achieving a sampling rate of 1 MSPS.
The AD7091R-2/AD7091R-4/AD7091R-8 family offers up to eight
single-ended analog input channels with a channel sequencer
that allows a preprogrammed selection of channels to be converted
sequentially. The AD7091R-2/AD7091R-4/ AD7091R-8 also
feature an on-chip conversion clock, an on-chip accurate 2.5 V
reference, and a high speed serial interface.
The AD7091R-2/AD7091R-4/AD7091R-8 have a serial port
interface (SPI) that allows data to be read after the conversion
while achieving a 1 MSPS throughput rate. The conversion process
and data acquisition are controlled using the CONVST pin.
The AD7091R-2/AD7091R-4/AD7091R-8 use advanced design
techniques to achieve ultralow power dissipation at high
throughput rates. They also feature flexible power management
options. An on-chip configuration register allows the user to set up
different operating conditions. These include power management,
alert functionality, busy indication, channel sequencing, and
general-purpose output pins. The MUXOUT and ADCIN pins
allow signal conditioning of the multiplexer output prior to
acquisition by the ADC.
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AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Addressing Registers .................................................................. 23
Applications ....................................................................................... 1
Conversion Result Register ....................................................... 24
Functional Block Diagram .............................................................. 1
Channel Register ........................................................................ 25
General Description ......................................................................... 1
Configuration Register .............................................................. 26
Revision History ............................................................................... 2
Alert Indication Register ........................................................... 28
Specifications..................................................................................... 3
Channel x Low Limit Register .................................................. 30
Timing Specifications .................................................................. 5
Channel x High Limit Register ................................................. 30
Absolute Maximum Ratings ............................................................ 7
Channel x Hysteresis Register .................................................. 30
Thermal Resistance ...................................................................... 7
Serial Port Interface ........................................................................ 31
ESD Caution .................................................................................. 7
Reading Conversion Result ....................................................... 31
Pin Configurations and Function Descriptions ........................... 8
Writing Data to the Registers ................................................... 31
Typical Performance Characteristics ........................................... 13
Reading Data from the Registers.............................................. 31
Terminology .................................................................................... 18
Power-On Device Initialization................................................ 33
Theory of Operation ...................................................................... 19
Modes of Operation ....................................................................... 34
Circuit Information .................................................................... 19
Normal Mode .............................................................................. 34
Converter Operation .................................................................. 19
Power-Down Mode .................................................................... 34
ADC Transfer Function ............................................................. 19
ALERT (AD7091R-4 and AD7091R-8 Only) .......................... 35
Reference ..................................................................................... 19
BUSY (AD7091R-4 and AD7091R-8 Only) ............................. 35
Power Supply ............................................................................... 20
Channel Sequencer .................................................................... 36
Device Reset ................................................................................ 20
Daisy Chain ................................................................................. 37
Typical Connection Diagram.................................................... 20
Outline Dimensions ....................................................................... 39
Analog Input ............................................................................... 20
Ordering Guide .......................................................................... 42
Driver Amplifier Choice ............................................................ 21
Registers ........................................................................................... 23
REVISION HISTORY
12/15—Rev. B to Rev. C
Change to the Reference Section .................................................. 19
11/14—Rev. A to Rev. B
Added Endnote 1 .............................................................................. 3
Added Total Power Dissipation (Normal Mode) of 0.080 mW ... 4
Changes to Table 2 ............................................................................ 5
Added Device Reset Section and Figure 43; Renumbered
Sequentially ..................................................................................... 20
Added Power-On Device Initialization Section and Figure 53.. 33
7/14—Rev. 0 to Rev. A
Added 16-Lead LFCSP, 20-Lead LFCSP, and
24-Lead LFCSP ................................................................... Universal
Changes to Features Section............................................................ 1
Changes to General Description Section ...................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 4 ............................................................................ 7
Added Figure 6; Renumbered Sequentially .................................. 8
Changes to Table 5.............................................................................8
Added Figure 8 ..................................................................................9
Changes to Table 6.............................................................................9
Added Figure 10 ............................................................................. 11
Changes to Table 7.......................................................................... 11
Added Power Supply Section and Table 8; Renumbered
Sequentially ..................................................................................... 20
Added Driver Amplifier Choice Section and Table 9 ................ 21
Changes to Table 16 ....................................................................... 26
Changed Serial Interface Section to Serial Port Interface
Section .............................................................................................. 31
Changes to Figure 52...................................................................... 33
Updated Outline Dimensions ....................................................... 38
Changes to Ordering Guide .......................................................... 41
12/13—Revision 0: Initial Version
Rev. C | Page 2 of 42
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, VREF = 2.5 V internal reference, fSAMPLE = 1 MSPS, fSCLK = 50 MHz, TA = TMIN to TMAX, unless
otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Signal-to-Noise-and-Distortion (SINAD) Ratio
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Channel-to-Channel Isolation
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Offset Error Matching
Offset Error Drift
Gain Error
Gain Error Matching
Gain Error Drift
ANALOG INPUT
Input Voltage Range 1
DC Leakage Current
Input Capacitance 2
Multiplexer On Resistance
VOLTAGE REFERENCE INPUT/OUTPUT
REFOUT 3
REFIN3
Drift
Power-On Time
LOGIC INPUTS
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IIN)
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating State Leakage Current
Output Coding
Test Conditions/Comments
fIN = 10 kHz sine wave
Min
Typ
66.5
65.5
70
69
−80
−81
−95
5
40
1.5
1.2
fIN = 1 kHz sine wave
At −3 dB
At −0.1 dB
VDD ≥ 3.0 V
VDD ≥ 2.7 V
Guaranteed no missing codes to 12 bits
TA = 25°C
TA = 25°C
12
−1
−1.25
−0.9
−1.5
−1.5
TA = 25°C
TA = 25°C
−0.1
−0.1
At ADCIN
0
−1
±0.7
±0.8
±0.3
0.2
0.2
2
0.0
0.0
2
During acquisition phase
Outside acquisition phase
VDD = 5.0 V
VDD = 2.5 V
Internal reference output, TA = 25°C
External reference input
Max
dB
dB
dB
dB
dB
ns
ps
MHz
MHz
+1
+1.25
+0.9
+1.5
+1.5
+0.1
+0.1
2.5
V
µA
pF
pF
Ω
Ω
2.51
VDD
V
V
ppm/°C
ms
5
50
CREF = 2.2 µF
0.7 × VDRIVE
0.3 × VDRIVE
+1
Typically 10 nA, VIN = 0 V or VDRIVE
−1
ISOURCE = 200 µA
ISINK = 200 µA
VDRIVE − 0.2
−1
Rev. C | Page 3 of 42
Bits
LSB
LSB
LSB
mV
mV
ppm/°C
% FS
% FS
ppm/°C
VREF
+1
10
1.5
50
100
2.49
1.0
Unit
0.4
+1
Straight (natural) binary
V
V
µA
V
V
µA
AD7091R-2/AD7091R-4/AD7091R-8
Parameter
CONVERSION RATE
Conversion Time
Transient Response
Throughput Rate
POWER REQUIREMENTS
VDD
VDRIVE
VDRIVE Range 4
IDD
Normal Mode—Static 5
Normal Mode—Operational
Power-Down Mode
IDRIVE
Normal Mode—Static 6
Normal Mode—Operational
Power-Down Mode
Total Power Dissipation 7
Normal Mode—Static
Normal Mode—Operational
Power-Down Mode
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
600
400
1
ns
ns
MSPS
5.25
5.25
5.25
V
V
V
22
21.6
500
450
0.550
0.550
0.435
50
46
570
530
17
6
15
µA
µA
µA
µA
µA
µA
µA
2
1
30
10
4
3.5
70
15
1
1
µA
µA
µA
µA
µA
µA
0.130
0.070
2.8
1.4
0.080
3
3
1.4
0.290
0.149
3.4
1.7
mW
mW
mW
mW
mW
µW
µW
µW
Full-scale step input
Specified performance
Functional
VIN = 0 V
VDD = 5.25 V
VDD = 3 V
VDD = 5.25 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 1 MSPS
VDD = 5.25 V
VDD = 5.25 V, TA = −40°C to +85°C
VDD = 3 V
VIN = 0 V
VDRIVE = 5.25 V
VDRIVE = 3 V
VDRIVE = 5.25 V, fSAMPLE = 1 MSPS
VDRIVE = 3 V, fSAMPLE = 1 MSPS
VDRIVE = 5.25 V
VDRIVE = 3 V
VIN = 0 V
VDD = VDRIVE = 5.25 V
VDD = VDRIVE = 3 V
VDD = VDRIVE = 5.25 V, fSAMPLE = 1 MSPS
VDD = VDRIVE = 3 V, fSAMPLE = 1 MSPS
VDD = VDRIVE = 3 V, fSAMPLE = 100 SPS
VDD = 5.25 V
VDD = 5.25 V, TA = −40°C to +85°C
VDD = VDRIVE = 3 V
2.7
2.7
1.8
95
33
50
Multiplexer input voltage should not exceed VDD.
Sample tested during initial release to ensure compliance.
3
When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configurations and Function Descriptions section.
4
Device is functional and meets dynamic performance/dc accuracy specifications with VDRIVE down to 1.8 V, but the device is not capable of achieving a throughput of
1 MSPS.
5
SCLK operates in burst mode, and CS idles high. With a free running SCLK and CS pulled low, the IDD static current is increased by 30 µA typical at VDD = 5.25 V.
6
SCLK operates in burst mode, and CS idles high. With a free running SCLK and CS pulled low, the IDRIVE static current is increased by 32 µA typical at VDRIVE = 5.25 V.
7
Total power dissipation includes contributions from VDD, VDRIVE, and REFIN (see Note 2).
1
2
Rev. C | Page 4 of 42
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
500µA
Symbol
tCONVERT
tACQ
tCYC
tCNVPW
tSCLK
Min
400
1000
10
ns
ns
20
25
6
6
5
ns
ns
ns
ns
ns
tSCLKL
tSCLKH
tHSDO
tDSDO
12
13
14
20
tEOCCSL
tEN
tDIS
tSSDISCLK
tHSDISCLK
tQUIET
tRESETPW
tRESET_DELAY
tCYC_RESET
5
5
5
5
2
50
10
50
2
10891-138
IOH
tDELAY
VIH2
VIL2
1.4V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
Y% VDRIVE
tDELAY
500µA
500
Unit
ns
ns
ns
ns
16
22
X% VDRIVE
CL
20pF
Max
600
tSCLK
IOL
TO SDO
Typ
VIH2
VIL2
NOTES
1FOR V
DRIVE ≤ 3.0V, X = 90 AND Y = 10; FOR VDRIVE > 3.0V, X = 70 AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE SPECIFICATIONS FOR DIGITAL
INPUTS PARAMETER IN TABLE 2.
Figure 3. Voltage Levels for Timing
Figure 2. Load Circuit for Digital Interface Timing
Rev. C | Page 5 of 42
10891-139
Parameter
Conversion Time: CONVST Falling Edge to Data Available
Acquisition Time
Time Between Conversions (Normal Mode)
CONVST Pulse Width
SCLK Period (Normal Mode)
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
SCLK Period (Chain Mode)
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Remains Valid
SCLK Falling Edge to Data Valid Delay
VDRIVE Above 4.5 V
VDRIVE Above 3.3 V
VDRIVE Above 2.7 V
VDRIVE Above 1.8 V
End of Conversion to CS Falling Edge
CS Low to SDO Enabled
CS High or Last SCLK Falling Edge to SDO High Impedance
SDI Data Setup Time Prior to SCLK Rising Edge
SDI Data Hold Time After SCLK Rising Edge
Last SCLK Falling Edge to Next CONVST Falling Edge
RESET Pulse Width
RESET Pulse Delay Upon Power Up
Time Between Conversions (Power On Software Reset)
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
Timing Diagram
tCYC
EOC
tACQ
tCNVPW
CONVST
tQUIET
tCONVERT
tEOCCSL
CS
1
SCLK
SDO
TRISTATE
tSCLK
2
tSCLKH
4
5
CH_ID2
CH_ID1
CH_ID0
ADD4
ADD3
ADD2
6
7
15
DB10
DB9
DB1
tSCLKL
tDSDO
tEN
tSSDISCLK
SDI
3
ALERT
DB11
16
tDIS
DB0
tHSDISCLK
ADD1
ADD0
RW
DB9
Figure 4. Serial Port Timing
Rev. C | Page 6 of 42
DB1
DB0
TRISTATE
10891-002
tHSDO
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
VDD to GND
VDRIVE to GND
Analog Input Voltage to GND
Digital Input1 Voltage to GND
Digital Output2 Voltage to GND
Input Current to Any Pin Except Supplies3
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VREF + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
±10 mA
−40°C to +125°C
−65°C to +150°C
150°C
Table 4. Thermal Resistance
Package Type
24-Lead LFCSP
24-Lead TSSOP
20-Lead LFCSP
20-Lead TSSOP
16-Lead LFCSP
16-Lead TSSOP
ESD CAUTION
1.5 kV
500 V
The digital input pins include the following: RESET, CONVST, SDI, SCLK, and CS.
The digital output pins include the following: SDO, GPO1, and ALERT/BUSY/GPO0.
3
Transient currents of up to 100 mA do not cause SCR latch-up.
1
2
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 7 of 42
θJA
47.3
73.54
49.05
84.29
50.58
106.03
θJC
27.78
14.94
29.18
18.43
29.64
28.31
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
13 CONVST
14 VDRIVE
16 RESET
15 CS
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
TOP VIEW
(Not to Scale)
GND 6
MUXOUT 7
VIN0 8
13 SDO
MUXOUT 5
AD7091R-2
12 SDI
11 GND
10 ADCIN
9
VIN1
10 SDI
9
GND
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO GND.
10891-008
14 SCLK
10891-007
REGCAP 4
GND 4
TOP VIEW
(Not to Scale)
VIN1 7
VDD 3
REFIN/REFOUT 5
REFIN/REFOUT 3
15 CONVST
11 SDO
ADC IN 8
16 VDRIVE
2
12 SCLK
AD7091R-2
VIN0 6
CS 1
RESET
REGCAP 2
Figure 6. 2-Channel, 16-Lead LFCSP Pin Configuration
Figure 5. 2-Channel, 16-Lead TSSOP Pin Configuration
Table 5. 2-Channel, 16-Lead LFCSP and 16-Lead TSSOP Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
15
2
16
3
1
4
2
Mnemonic
CS
RESET
VDD
REGCAP
5
3
REFIN/REFOUT
6, 11
7
4, 9
5
GND
MUXOUT
8
9
10
6
7
8
VIN0
VIN1
ADCIN
12
10
SDI
13
11
SDO
14
15
12
13
SCLK
CONVST
16
14
VDRIVE
Not
applicable
17
EPAD
Description
Chip Select Input. When CS is held low, the serial bus enables, and CS frames the output data on the SPI.
Reset. Logic input.
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin
separately to GND using a 1.0 μF capacitor.
Voltage Reference Output, 2.5 V. Decouple this pin to GND. Typical recommended decoupling
capacitor value is 2.2 μF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with the voltage applied to this pin. The reference voltage range for an externally
applied reference is 1.0 V to VDD.
Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-2.
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or buffering is
required, tie this pin directly to the MUXOUT pin; otherwise tie the input of the conditioning network
to the MUXOUT pin.
Serial Data Input Bus. This input provides the data written to the on-chip control registers. Data
clocks into the registers on the falling edge of the SCLK input. Provide data MSBs first.
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data stream. The
bits are clocked out on the falling edge of the SCLK input, and 13 SCLKs are required to access the
data. The data is provided MSB first.
Serial Clock. This pin acts as the serial clock input.
Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the trackand-hold mode into hold mode and initiates a conversion.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. Connect decoupling capacitors between VDRIVE and GND. Typical recommended values are 10 μF
and 0.1 μF. The voltage range on this pin is 1.8 V to 5.25 V and may be different to the voltage range
at VDD.
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to GND.
Rev. C | Page 8 of 42
20
19
18
17
16
CONVST
SCLK
AD7091R-2/AD7091R-4/AD7091R-8
RESET
CS
VDRIVE
Data Sheet
VDRIVE
RESET
2
19
CONVST
VDD
3
18
SCLK
REGCAP
4
17
SDO
REFIN/REFOUT
5
16
SDI
GND
6
15
GND
MUXOUT
7
14
ADCIN
VIN0
8
13
VIN1
VIN2
9
12
VIN3
ALERT/BUSY/GPO0 10
11
GPO1
AD7091R-4
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
SDO
SDI
GND
ADC IN
VIN1
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO GND.
Figure 7. 4-Channel, 20-Lead TSSOP Pin Configuration
10891-006
20
AD7091R-4
15
14
13
12
11
VIN0 6
VIN2 7
ALERT/BUSY/GPO0 8
GPO1 9
VIN3 10
1
10891-005
CS
VDD 1
REGCAP 2
REFIN/REFOUT 3
GND 4
MUXOUT 5
Figure 8. 4-Channel, 20-Lead LFCSP Pin Configuration
Table 6. 4-Channel, 20-Lead LFCSP and 20-Lead TSSOP Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
19
Mnemonic
CS
2
3
4
20
1
2
RESET
VDD
REGCAP
5
3
REFIN/REFOUT
6, 15
7
4, 13
5
GND
MUXOUT
8
9
10
6
7
8
VIN0
VIN2
ALERT/BUSY/GPO0
11
12
13
14
9
10
11
12
GPO1
VIN3
VIN1
ADCIN
16
14
SDI
17
15
SDO
Description
Chip Select Input. When CS is held low, the serial bus enables, and CS frames the output data on
the SPI.
Reset. Logic input.
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin
separately to GND using a 1.0 μF capacitor.
Voltage Reference Output, 2.5 V. Decouple this pin to GND. Typical recommended decoupling
capacitor value is 2.2 μF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with the voltage applied to this pin. The reference voltage range for an
externally applied reference is 1.0 V to VDD.
Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-4.
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 2. Single-ended analog input. The analog input range is 0 V to VREF.
Alert Output Pin (ALERT). This is a multifunction pin determined by the configuration register.
When functioning as ALERT, this pin is a logic output indicating that a conversion result has
fallen outside the limit of the register settings.
When the ALERT/BUSY/GPO0 pin is configured as a BUSY output, use this pin to indicate when a
conversion is taking place.
The pin can also function as a general-purpose digital output.
General-Purpose Digital Output.
Analog Input 3. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or
buffering is required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the
conditioning network to the MUXOUT pin.
Serial Data Input Bus. This input provides data written to the on-chip control registers. Data
clocks into the registers on the falling edge of the SCLK input. Provide data MSB first.
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input, and 13 SCLKs are
required to access the data. The data is provided MSB first.
Rev. C | Page 9 of 42
AD7091R-2/AD7091R-4/AD7091R-8
Pin No.
TSSOP
LFCSP
18
16
19
17
Mnemonic
SCLK
CONVST
20
18
VDRIVE
Not
applicable
21
EPAD
Data Sheet
Description
Serial Clock. This pin acts as the serial clock input.
Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the
track-and-hold mode into hold mode and initiates a conversion.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the
interface operates. Connect decoupling capacitors between VDRIVE and GND. Typical recommended
values are 10 µF and 0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and may be different
to the voltage range at VDD.
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to GND.
Rev. C | Page 10 of 42
19 SDO
21 CONVST
20 SCLK
22 VDRIVE
23 CS
AD7091R-2/AD7091R-4/AD7091R-8
24 RESET
18 SDI
VDD 1
22
SCLK
21
SDO
REFIN/REFOUT
5
GND
6
MUXOUT
7
VIN0
VIN2
20
SDI
19
GND
18
ADCIN
8
17
VIN1
9
16
VIN3
ALERT/BUSY/GPO0 10
15
GPO1
VIN4 11
14
VIN5
VIN6 12
13
VIN7
AD7091R-8
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
16 ADC IN
15 VIN1
14 VIN3
13 GPO1
VIN5 12
3
4
AD7091R-8
VIN7 11
VDD
REGCAP
GND 4
MUXOUT 5
VIN0 6
VIN6 10
CONVST
VIN4 9
VDRIVE
23
VIN2 7
24
2
17 GND
ALERT/BUSY/GPO0 8
1
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO GND.
10891-003
CS
RESET
REGCAP 2
REFIN/REFOUT 3
Figure 9. 8-Channel, 24-Lead TSSOP Pin Configuration
10891-004
Data Sheet
Figure 10. 8-Channel, 24-Lead LFCSP Pin Configuration
Table 7. 8-Channel, 24-Lead LFCSP and 24-Lead TSSOP Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
23
Mnemonic
CS
2
3
4
24
1
2
RESET
VDD
REGCAP
5
3
REFIN/REFOUT
6, 19
7
4, 17
5
GND
MUXOUT
8
9
10
6
7
8
VIN0
VIN2
ALERT/BUSY/GPO0
11
12
13
14
15
16
17
18
9
10
11
12
13
14
15
16
VIN4
VIN6
VIN7
VIN5
GPO1
VIN3
VIN1
ADCIN
Description
Chip Select Input. When CS is held low, the serial bus enables, and CS frames the output data
on the SPI.
Reset. Logic input.
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin
separately to GND using a 1.0 μF capacitor.
Voltage Reference Output, 2.5 V. Decouple this pin to GND. Typical recommended decoupling
capacitor value is 2.2 μF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with the voltage applied to this pin. The reference voltage range for an
externally applied reference is 1.0 V to VDD.
Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-8.
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 2. Single-ended analog input. The analog input range is 0 V to VREF.
Alert Output Pin (ALERT). This is a multifunction pin determined by the configuration register.
When functioning as ALERT, this pin is a logic output indicating that a conversion result has
fallen outside the limit of the register settings.
When the ALERT/BUSY/GPO0 pin is configured as a BUSY output, use this pin to indicate when a
conversion is taking place.
The pin can also function as a general-purpose digital output.
Analog Input 4. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 6. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 7. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 5. Single-ended analog input. The analog input range is 0 V to VREF.
General-Purpose Digital Output.
Analog Input 3. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or
buffering is required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the
conditioning network to the MUXOUT pin.
Rev. C | Page 11 of 42
AD7091R-2/AD7091R-4/AD7091R-8
Pin No.
TSSOP
LFCSP
20
18
Mnemonic
SDI
21
19
SDO
22
23
20
21
SCLK
CONVST
24
22
VDRIVE
Not
applicable
25
EPAD
Data Sheet
Description
Serial Data Input Bus. Data to be written to the on-chip control registers is provided on this input.
Data is clocked into the registers on the falling edge of the SCLK input. Provide data MSB first.
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input, and 13 SCLKs are
required to access the data. The data is provided MSB first.
Serial Clock. This pin acts as the serial clock input.
Convert Start Input Signal. Edge triggered logic input. The falling edge of CONVST places the
track-and-hold mode into hold mode and initiates a conversion.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the
interface operates. Connect decoupling capacitors between VDRIVE and GND. Typical
recommended values are 10 µF and 0.1 µF. The voltage range on this pin is 1.8 V to 5.25 V and
may be different to the voltage range at VDD.
Exposed Pad. The exposed pad is not connected internally. It is recommended that the pad be
soldered to GND.
Rev. C | Page 12 of 42
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
1.0
1.0
0.8
0.6
0.4
0.4
0.2
0.2
0
–0.2
VDD = 3.0V
VREF = 2.5V
TA = 25°C
fSAMPLE = 1MSPS
POSITIVE INL = +0.74LSB
NEGATIVE INL = –0.37LSB
–0.4
–0.6
–0.8
–1.0
0
500
1000
1500
2000
0
–0.2
–0.4
VDD = 3.0V
VREF = 2.5V
TA = 25°C
fSAMPLE = 1MSPS
POSITIVE DNL = +0.48LSB
NEGATIVE DNL = –0.50LSB
–0.6
2500
3000
3500
4000
–0.8
–1.0
4500
0
500
1000
1500
2000
CODE
3500
4000
4500
Figure 14. Differential Nonlinearity vs. Code
60000
40000
VDD = VDRIVE = 3.0V
65k SAMPLES
TA = 25°C
35000
NUMBER OF OCCURRENCES
NUMBER OF OCCURRENCES
3000
2500
CODE
Figure 11. Integral Nonlinearity vs. Code
50000
10891-116
DNL (LSB)
0.8
0.6
10891-115
INL (LSB)
TYPICAL PERFORMANCE CHARACTERISTICS
40000
30000
20000
VDD = VDRIVE = 3.0V
65k SAMPLES
TA = 25°C
30000
25000
20000
15000
10000
10000
0
2047
0
2049
2048
10891-120
10891-119
5000
2044
2045
CODE
0
0
VDD = 3.0V
VREF = 2.5V EXTERNAL
TA = 25°C
fIN = 10kHz
fSAMPLE = 1MSPS
SNR = 69.52dB
SINAD = 69.21dB
THD = –84.25dB
SFDR = –85.79dB
–60
–80
–40
–60
–80
–100
–120
–120
–140
–140
10891-117
–100
0
50
100
150
200
250
300
350
400
450
–160
500
FREQUENCY (kHz)
10891-118
–40
VDD = 3.0V
VREF = 2.5V INTERNAL
TA = 25°C
fIN = 10kHz
fSAMPLE = 1MSPS
SNR = 69.44dB
SINAD = 69.19dB
THD = –84.21dB
SFDR = –85.82dB
–20
SNR (dB)
–20
SNR (dB)
2047
Figure 15. Histogram of a DC Input at Code Transition
Figure 12. Histogram of a DC Input at Code Center
–160
2046
CODE
0
50
100
150
200
250
300
350
400
450
FREQUENCY (kHz)
Figure 16. 10 kHz FFT, VDD = 3.0 V, VREF = 2.5 V Internal
Figure 13. 10 kHz Fast Fourier Transform (FFT),
VDD = 3.0 V, VREF = 2.5 V External
Rev. C | Page 13 of 42
500
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
0
72
TA = 25°C
fSAMPLE = 1MSPS
VREF = 2.5V
–10
70
–20
2.7V
3.0V
5.0V
–30
–40
THD (dB)
66
–50
64
–70
TA = 25°C
fSAMPLE = 1MSPS
VREF = 2.5V
–90
10
100
–100
INPUT FREQUENCY (kHz)
69.6
69.5
70
69.4
SNR (dB)
2.7V
3.0V
5.0V
68
66
64
69.3
69.2
69.1
TA = 25°C
fSAMPLE = 1MSPS
VREF = 2.5V
1
VDD = 5.0V
TA = 25°C
fSAMPLE = 1MSPS
fIN = 10kHz
69.0
10
68.9
–10
10891-111
62
100
INPUT FREQUENCY (kHz)
–9
SNR
SINAD
ENOB
11.00
67.0
THD, SFDR (dB)
68.0
10.80
VDD = 5.0V
TA = 25°C
fSAMPLE = 1MSPS
fIN = 10kHz
65.0
2.5
3.0
3.5
4.0
4.5
–82
–84
–86
10.60
10.40
5.0
10.20
10891-121
66.0
0
–80
11.40
11.20
–1
–2
–3
THD
SFDR
ENOB (Bits)
SNR, SINAD (dB)
–4
–78
11.60
69.0
2.0
–5
11.80
70.0
1.5
–6
–88
–90
1.0
REFERENCE VOLTAGE (V)
VDD = 5.0V
TA = 25°C
fSAMPLE = 1MSPS
fIN = 10kHz
10891-128
71.0
–7
Figure 21. SNR vs. Input Level
12.00
72.0
–8
INPUT LEVEL (dB)
Figure 18. SINAD vs. Analog Input Frequency for Various Supply Voltages
64.0
1.0
100
Figure 20. THD vs. Analog Input Frequency for Various Supply Voltages
72
SINAD (dB)
10
INPUT FREQUENCY (kHz)
Figure 17. SNR vs. Analog Input Frequency for Various Supply Voltages
60
1
10891-109
1
–80
10891-108
62
60
2.7V
3.0V
5.0V
–60
10891-123
SNR (dB)
68
1.5
2.0
2.5
3.0
3.5
4.0
4.5
REFERENCE VOLTAGE (V)
Figure 19. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 22. THD and SFDR vs. Reference Voltage
Rev. C | Page 14 of 42
5.0
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
–80
600
–81
550
–82
500
–84
–85
–86
–87
450
CURRENT (µA)
THD (dB)
–83
VDD = 5.0V
fSAMPLE = 1MSPS
fIN = 10kHz
400
fSAMPLE = 1MSPS
300
–88
–35
–15
5
25
45
65
85
105
200
125
10891-125
–90
–55
250
10891-129
–89
–40
25
TEMPERATURE (°C)
70
70.6
60
VDD = 3.0V
VREF = 2.5V
fIN = 10kHz
fSAMPLE = 1MSPS
5.25V
5.0V
3.3V
2.7V
50
CURRENT (µA)
SNR (dB)
125
Figure 26. Operational IDD Supply Current vs. Temperature
for Various VDD Supply Voltages
70.8
70.2
85
TEMPERATURE (°C)
Figure 23. THD vs. Temperature
70.4
5.25V
5.0V
3.3V
2.7V
350
70.0
69.8
40
30
69.6
20
69.4
–35
–15
5
25
45
65
85
105
0
125
10891-126
69.0
–55
10
10891-122
69.2
–40
25
500
8
400
TOTAL POWER-DOWN CURRENT (µA)
IDD (µA) AT VDD = VDRIVE = 3.00V
IDRIVE (µA) AT VDD = VDRIVE = 3.00V
IDD (µA) AT VDD = VDRIVE = 5.00V
IDRIVE (µA) AT VDD = VDRIVE = 5.00V
350
300
250
200
150
10891-137
100
50
200
300
400
500
600
700
800
900
5.25V
5.0V
3.3V
2.7V
6
5
4
3
2
1
0
1000
THROUGHPUT (kSPS)
Figure 25. Operating Current vs. Throughput
7
10891-127
450
CURRENT (µA)
125
Figure 27. Operational IDRIVE Supply Current vs. Temperature for
Various VDRIVE Supply Voltages
Figure 24. SNR vs. Temperature
0
100
85
TEMPERATURE (°C)
TEMPERATURE (°C)
–40
25
85
125
TEMPERATURE (°C)
Figure 28. Total Power-Down Current vs. Temperature for Various Supplies
Rev. C | Page 15 of 42
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
12
100
VDRIVE = 1.8V, +25°C
VDRIVE = 1.8V, +125°C
95
90
8
VDRIVE = 1.8V, –40°C
PSRR (dB)
VDRIVE = 3V, +125°C
6
85
TA = 25°C
fSAMPLE = 1MSPS
VREF = 2.5V EXTERNAL
80
4
VDRIVE = 3V, +25°C
VDD = VDRIVE = 5.00V
VDD = VDRIVE = 3.00V
VDRIVE = 3V, –40°C
10
20
30
40
70
10891-113
0
50
SDO CAPACITANCE LOAD (pF)
1
10
Figure 32. PSRR vs. Ripple Frequency
1.5
0.10
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
0.5
0.08
0.06
GAIN ERROR (%FS)
1.0
OFFSET ERROR (mV)
1000
RIPPLE FREQUENCY (kHz)
Figure 29. tDSDO Delay vs. SDO Capacitance Load and Supply
0
–0.5
0.04
0.02
0
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
–0.02
–0.04
–0.06
10891-130
–1.0
–1.5
–55
100
10891-136
75
2
–35
–15
5
25
45
65
85
105
–0.08
–0.10
–55
125
–35
–15
TEMPERATURE (°C)
5
25
45
10891-133
tDSDO DELAY (ns)
10
85
105
125
85
105
125
65
TEMPERATURE (°C)
Figure 30. Offset Error vs. Temperature
Figure 33. Gain Error vs. Temperature
0.10
1.5
0.08
GAIN ERROR MATCH (%FS)
0.5
0
–0.5
0.04
0.02
0
–0.02
–0.04
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
10891-134
–1.5
–55
0.06
–0.06
–1.0
10891-131
OFFSET ERROR MATCH (mV)
1.0
–0.08
–0.10
–55
–35
–15
5
25
45
65
TEMPERATURE (°C)
Figure 34. Gain Error Match vs. Temperature
Figure 31. Offset Error Match vs. Temperature
Rev. C | Page 16 of 42
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
–50
VDD = 5.0V
TA = 25°C
fSAMPLE = 1MSPS
–70
TA = 25°C
VDD = 3V
fIN = 10kHz
fSAMPLE = 1MSPS
–55
–60
THD (dB)
–80
–90
–65
–70
–100
–75
–110
–85
100
10
INPUT FREQUENCY (kHz)
10
INTERNAL REFERENCE VOLTAGE (V)
–89
–91
–93
–95
–97
VDD = 5.0V
fSAMPLE = 1MSPS
fIN = 10kHz
10891-132
CHANNEL-TO-CHANNEL ISOLATION (dB)
2.510
–87
–103
–105
–55
–35
–15
5
25
45
65
85
105
VDD = VDRIVE = 3V
2.500
2.498
2.494
2.492
2.490
+25°C
–40°C
+85°C
+125°C
2.484
40
60
80
100
CURRENT LOAD (µA)
10891-114
VREF (V)
2.496
20
2.495
–35
–15
5
25
45
65
85
105
Figure 39. Internal Reference Voltage vs. Temperature
2.502
0
2.500
TEMPERATURE (°C)
Figure 36. Channel-to-Channel Isolation vs. Temperature
2.486
2.505
2.490
–55
125
TEMPERATURE (°C)
2.488
10k
Figure 38. THD vs. Source Impedance
–85
–101
1k
SOURCE IMPEDANCE (Ω)
Figure 35. Channel-to-Channel Isolation vs. Input Frequency
–99
100
10891-110
1
10891-135
–120
–80
10891-124
CHANNEL-TO-CHANNEL ISOLATION (dB)
–60
Figure 37. Reference Voltage Output (VREF) vs. Current Load
for Various Temperatures
Rev. C | Page 17 of 42
125
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. For the
AD7091R-2/AD7091R-4/AD7091R-8, the endpoints of the
transfer function are zero scale, a point ½ LSB below the first
code transition, and full scale, a point ½ LSB above the last code
transition.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Signal-to-Noise-and-Distortion (SINAD) Ratio
SINAD is the measured ratio of signal-to-noise-and-distortion
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical SINAD ratio for an ideal N-bit converter
with a sine wave input is given by
SINAD = (6.02N + 1.76) dB
Offset Error
The offset error is the deviation of the first code transition
(00 … 000 to 00 … 001) from the ideal (such as GND + 0.5 LSB).
Offset Error Match
Offset error match is the difference in offset error between any
two input channels.
Gain Error
For the AD7091R-2/AD7091R-4/AD7091R-8, the gain error is
the deviation of the last code transition (111 … 110 to 111 …
111) from the ideal (such as VREF − 1.5 LSB) after the offset
error has been adjusted out.
Gain Error Match
Gain error match is the difference in gain error between any two
input channels.
Transient Response Time
The track-and-hold amplifier returns to track mode after the
end of conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±0.5 LSB, after the end of conversion.
See the Serial Port Interface section for more details.
Thus, for a 12-bit converter, the SINAD ratio is 74 dB.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between the selected channel and all of the other
channels. It is measured by applying a full-scale, 10 kHz sine
wave signal to all unselected input channels and determining
the degree to which the signal attenuates in the selected channel
that has a dc signal applied to it. Figure 35 shows the worst case
across all channels for the AD7091R-2/AD7091R-4/AD7091R-8.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental.
For the AD7091R-2/AD7091R-4/AD7091R-8, it is defined as
THD (dB ) = 20 log
V22 + V32 + V4 2 + V52 + V62
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonic.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Rev. C | Page 18 of 42
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
THEORY OF OPERATION
The AD7091R-2/AD7091R-4/AD7091R-8 are 12-bit, fast
(1 MSPS), ultralow power, single-supply ADCs. The devices
operate from a 2.7 V to 5.25 V supply. The AD7091R-2/
AD7091R-4/AD7091R-8 are capable of throughput rates
of 1 MSPS.
The AD7091R-2/AD7091R-4/AD7091R-8 provide an on-chip,
track-and-hold ADC and a serial interface housed in a 16-lead,
20-lead, or 24-lead TSSOP or LFCSP package, which offers
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the device. The clock
for the successive approximation ADC is generated internally.
The reference voltage for the AD7091R-2/AD7091R-4/AD7091R-8
is provided externally, or it is generated internally by an
accurate on-chip reference source. The analog input range for
the AD7091R-2/AD7091R-4/AD7091R-8 is 0 V to VREF.
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced (see
Figure 41). Using the control logic, the charge redistribution DAC
adds and subtracts fixed amounts of charge from the sampling
capacitor to bring the comparator back into a balanced condition.
When the SAR decisions are made, the comparator inputs are
rebalanced. From these SAR decisions, the control logic
generates the ADC output code.
ADC TRANSFER FUNCTION
The output coding of the AD7091R-2/AD7091R-4/AD7091R-8
is straight binary. The designed code transitions occur midway
between successive integer LSB values, such as ½ LSB, 1½ LSB, and
so on. The LSB size for the AD7091R-2/AD7091R-4/AD7091R-8
is VREF/4096. The ideal transfer characteristic for the AD7091R-2/
AD7091R-4/AD7091R-8 is shown in Figure 42.
The AD7091R-2/AD7091R-4/AD7091R-8 also feature a powerdown option to save power between conversions. The power-down
feature is implemented across the standard serial interface as
described in the Modes of Operation section.
ADC CODE
111...111
111...110
CONVERTER OPERATION
The AD7091R-2/AD7091R-4/AD7091R-8 are successive
approximation ADCs based on a charge redistribution digitalto-analog converter (DAC). Figure 40 and Figure 41 show
simplified schematics of the ADC. Figure 40 shows the ADC
during its acquisition phase. When SW2 is closed and SW1 is in
Position A, the comparator is held in a balanced condition, and
the sampling capacitor acquires the signal on VIN.
CHARGE
REDISTRIBUTION
DAC
SW1
B
ACQUISITION
PHASE
CONTROL
LOGIC
SW2
COMPARATOR
AGND
10891-015
VIN
SAMPLING
CAPACITOR
A
VDD/2
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
SW1
B
CONVERSION
PHASE
CONTROL
LOGIC
SW2
COMPARATOR
AGND
VDD/2
10891-016
VIN
1LSB = VREF/4096
011...111
000...010
000...001
000...000
0V 1LSB
ANALOG INPUT
+VREF – 1LSB
Figure 42. AD7091R-2/AD7091R-4/AD7091R-8 Transfer Characteristic
REFERENCE
The AD7091R-2/AD7091R-4/AD7091R-8 can operate with
either the internal 2.5 V on-chip reference or an externally
applied reference. The logic state of the P_DOWN LSB bit in
the configuration register determines whether the internal
reference is used. The internal reference is selected for the
ADCs when the P_DOWN LSB bit is set to 1.
When the P_DOWN LSB bit is set to 0, supply an external
reference in the range of 1.0 V to VDD through the REFIN/REFOUT
pin. At power-up, the internal reference disables by default.
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7091R-2/
AD7091R-4/AD7091R-8 in internal reference mode, the 2.5 V
internal reference is available at the REFIN/REFOUT pin, which
is typically decoupled to GND using a 2.2 μF capacitor. It is
recommended to buffer the internal reference before applying
it elsewhere in the system.
Figure 40. ADC Acquisition Phase
A
111...000
10891-017
CIRCUIT INFORMATION
The reference buffer requires 50 ms to power up and charge the
2.2 μF decoupling capacitor during the power-up time.
Figure 41. ADC Conversion Phase
Rev. C | Page 19 of 42
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
The AD7091R-2/AD7091R-4/AD7091R-8 use two power supply
pins: a core supply (VDD) and a digital input/output interface
supply (VDRIVE). VDRIVE allows direct interface with any logic
between 1.8 V and 5.25 V. To reduce the number of supplies
needed, VDRIVE and VDD can be tied together depending upon
the logic levels of the system. Additionally, the AD7091R-2/
AD7091R-4/AD7091R-8 are insensitive to power supply variation
over a wide frequency range, as shown in Figure 32. AD7091R-2/
AD7091R-4/AD7091R-8 operation is independent of power
supply sequencing between VDRIVE and VDD.
The AD7091R-2/AD7091R-4/AD7091R-8 power down
automatically at the end of each conversion phase; therefore,
the power scales linearly with the sampling rate. The automatic
power-down feature makes the AD7091R-2/AD7091R-4/
AD7091R-8 devices ideal for low sampling rates (of even a few
hertz) and battery-powered applications.
Table 8. Recommended Power Management Devices1
Product
ADP7102
ADM7160
ADP162
1
Description
20 V, 300 mA, low noise, CMOS LDO
Ultralow noise, 200 mA linear regulator
Ultralow quiescent current, CMOS linear regulator
The typical value for the regulator bypass (REGCAP) decoupling
capacitor is 1.0 μF. The voltage applied to the VDRIVE input
controls the voltage of the serial interface; therefore, connect
this pin to the supply voltage of the microprocessor. Set VDRIVE
in the 1.8 V to 5.25 V range. Typical values for the VDRIVE
decoupling capacitors are 0.1 μF and 10 μF. The conversion
result is output in a 16-bit word with the MSBs first.
When an externally applied reference is required, disable the
internal reference using the configuration register. Choose the
externally applied reference voltage in the 1.0 V to 5.25 V VDD
range and connect it to the REFIN/REFOUT pin.
For applications where power consumption is a concern, use the
power-down mode of the ADC to improve power performance.
See the Modes of Operation section for additional details.
ANALOG INPUT
Figure 44 shows an equivalent circuit of the analog input structure
of the AD7091R-2/AD7091R-4/AD7091R-8. The two diodes, D1
and D2, provide ESD protection for the analog input. Take care
to ensure that the analog input signal never exceeds the supply
rails by more than 300 mV because this causes these diodes to
become forward-biased and start conducting current into the
substrate. These diodes can conduct a maximum of 10 mA
without causing irreversible damage to the device.
For the latest recommended power management devices, see the AD7091R-2/
AD7091R-4/AD7091R-8 product pages.
VDD VREF
DEVICE RESET
D1
Upon power up, a reset pulse of at least 10 ns in width must be
provided on the RESET pin to ensure proper initialization of
the device. Failure to apply the reset pulse may result in a device
malfunction. See Figure 43 for reset pulse timing relative to
power supply establishment. If the system has a limited number
of digital pins and one cannot be allocated to the reset pin of the
ADC, a software reset may be issued in place of the hardware
reset signal (see the Power-On Device Initialization section).
tRESET_DELAY
VDD
tRESETPW
RESET
10891-141
VDRIVE
Figure 43. RESET Pin Power Up Timing
TYPICAL CONNECTION DIAGRAM
Figure 45 shows a typical connection diagram for the AD7091R-2/
AD7091R-4/AD7091R-8.
Connect a positive power supply in the 2.7 V to 5.25 V range to
the VDD pin. Typical values for these decoupling capacitors are
0.1 μF and 10 μF. Place these capacitors near the device pins.
Take care to decouple the REFIN/REFOUT pin to achieve specified
performance. The typical value for the REFIN/REFOUT capacitor
is 2.2 μF, which provides an analog input range of 0 V to VREF.
D3
R1
VIN
C1
400fF
C2
3.6pF
D2
CONVERSION PHASE–SWITCH OPEN
TRACK PHASE–SWITCH CLOSED
10891-019
POWER SUPPLY
Figure 44. Equivalent Analog Input Circuit
The C1 capacitor in Figure 44 is typically about 400 fF and can
primarily be attributed to pin capacitance. The R1 resistor is a
lumped component composed of the on resistance of a switch.
This resistor is typically about 500 Ω. The C2 capacitor is the
ADC sampling capacitor and typically has a capacitance of 3.6 pF.
In applications where harmonic distortion and signal-to-noise
ratio are critical, drive the analog inputs from low impedance
sources. Large source impedances significantly affect the ac
performance of the ADC that can necessitate using input buffer
amplifiers, as shown in Figure 45. The choice of the op amp is a
function of the particular application.
When no amplifiers are used to drive the analog input, limit the
source impedance to low values. The maximum source impedance
depends on the amount of THD that can be tolerated. The THD
increases as the source impedance increases and performance
degrades.
Rev. C | Page 20 of 42
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
Use an external filter on the analog input signal paths to the
AD7091R-2/AD7091R-4/AD7091R-8 VINx pins to achieve the
specified performance. This filter can be a one-pole low-pass
RC filter, or similar.
•
•
Connect the MUXOUT pin directly to the ADCIN pin. Insert a
buffer amplifier in the path, if desired. When sequencing
channels, do not place a filter between MUXOUT and the input to
any buffering because doing so leads to crosstalk. If buffering is
not employed, do not place a filter between MUXOUT and ADCIN
when sequencing channels because doing so leads to crosstalk.
DRIVER AMPLIFIER CHOICE
Although the AD7091R-2/AD7091R-4/AD7091R-8 are easy to
drive, a driver amplifier must meet the following requirements:
•
The noise generated by the driver amplifier must be kept as
low as possible to preserve the SNR and transition noise
performance of the AD7091R-2/AD7091R-4/AD7091R-8.
The noise from the driver is filtered by the one-pole, lowpass filter of the AD7091R-2/AD7091R-4/AD7091R-8
analog input circuit, made by R1 and C2, or by the external
filter, if one is used. Because the typical noise of the
AD7091R-2/AD7091R-4/AD7091R-8 is 280 µV rms,
the SNR degradation due to the amplifier is
SNRLOSS


280
= 20 log 

π
2
2
 280 + f − 3dB (NeN )
2

For ac applications, the driver must have a THD
performance that is commensurate with the AD7091R-2/
AD7091R-4/AD7091R-8.
If the buffer is placed between MUXOUT and ADCIN, the driver
amplifier and the AD7091R-2/AD7091R-4/AD7091R-8
analog input circuit must settle for a full-scale step onto
the capacitor array at a 12-bit level (0.0244%, 244 ppm).
In an amplifier data sheet, settling at 0.1% to 0.01% is more
commonly specified and may differ significantly from the
settling time at a 12-bit level. Be sure to verify the amplifier
settling time prior to driver selection.
Table 9. Recommended Driver Amplifiers1
Product
ADA4805-1
AD8031
AD8032
AD8615
1
Description
Low noise, ultralow power, wide bandwidth amplifier
Low voltage, low power, single channel amplifier
Low voltage, low power, dual channel amplifier
Low frequency, low voltage amplifier
For the latest recommended ADC driver products, see the AD7091R-2/
AD7091R-4/AD7091R-8 product pages.






where:
f−3dB is the input bandwidth, in megahertz, of the AD7091R-2/
AD7091R-4/AD7091R-8 (1.5 MHz), or the cutoff frequency
of the input filter, if one is used.
N is the noise gain of the amplifier (for example, gain = 1
in buffer configuration; see Figure 45).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
Rev. C | Page 21 of 42
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
WITH BUSY
INDICATION
VDRIVE
47kΩ
10µF
100nF
10µF
VDD
100nF
VDRIVE
MICROCONTROLLER/
MICROPROCESSOR/
DSP
SDO
REGCAP
SCLK
1µF
CS
ANALOG
INPUT
CONVST
VIN0
SDI
ALERT1
AD7091R-2/
AD7091R-4/
AD7091R-8
ANALOG
INPUT
ADCIN
VINX
REFIN/
REFOUT
GND
MUXOUT
2.2µF
33Ω
OPTIONAL
BUFFER
560pF
10891-018
NOTES
1THIS PIN IS FOR THE AD7091R-4/AD7091R-8.
Figure 45. Typical Connection Diagram with Optional Buffer
WITH BUSY
INDICATION
VDRIVE
47kΩ
100nF
10µF
VDD
100nF
VDRIVE
SDO
REGCAP
SCLK
1µF
33Ω
ANALOG
INPUT
CS
CONVST
VIN0
SDI
560pF
AD7091R-2/
AD7091R-4/
AD7091R-8
33Ω
ANALOG
INPUT
560pF
MICROCONTROLLER/
MICROPROCESSOR/
DSP
ALERT1
ADC IN
VINX
GND
REFIN/
REFOUT
MUXOUT
2.2µF
NOTES
1THIS PIN IS FOR THE AD7091R-4/AD7091R-8.
Figure 46. Typical Connection Diagram Without Optional Buffer
Rev. C | Page 22 of 42
10891-140
10µF
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
REGISTERS
ADDRESSING REGISTERS
The AD7091R-2/AD7091R-4/AD7091R-8 have user
programmable registers. Table 10 contains the complete list
of registers.
The registers are either read/write (R/W) or read only (R). Data
is written to or read back from the read/write registers. Read
only registers is only read. Any write to a read only register or
unimplemented register address is considered no operation
(NOP). A NOP command is an SPI command that is ignored by
the AD7091R-2/AD7091R-4/AD7091R-8. After a write to a read
only register, the output on the subsequent SPI frame is all zeros
if there was no conversion before the next SPI frame. Similarly,
any read of an unimplemented register outputs zeros.
A serial transfer on the AD7091R-2/AD7091R-4/AD7091R-8
consists of 16 SCLK cycles. The six MSBs on the SDI line during
the 16 SCLK transfer are decoded to determine which register is
addressed. The six MSBs consist of the register address (ADDx),
Bits[4:0], and the read/write bit. The register address bits
determine which of the on-chip registers are selected. The
read/write bit determines if the data on the SDI line following
the read/write bit loads into the addressed register. If the
read/write bit is 1, the bits load into the register addressed by
the register select bits. Data loads into the register on the rising
edge of CS. If the read/write bit is 0, the command is seen as a
read request. The requested register data is available on the
subsequent message on the SDO line.
Table 10. Register Description
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
…
0x1F
Register Name
Conversion result
Channel
Configuration
Alert indication
Channel 0 low limit
Channel 0 high limit
Channel 0 hysteresis
Channel 1 low limit
Channel 1 high limit
Channel 1 hysteresis
Channel 2 low limit
Channel 2 high limit
Channel 2 hysteresis
Channel 3 low limit
Channel 3 high limit
Channel 3 hysteresis
Channel 4 low limit
Channel 4 high limit
Channel 4 hysteresis
Channel 5 low limit
Channel 5 high limit
Channel 5 hysteresis
Channel 6 low limit
Channel 6 high limit
Channel 6 hysteresis
Channel 7 low limit
Channel 7 high limit
Channel 7 hysteresis
Reserved
…
Reserved
Default
0x0000
0x0000
0x00C0
0x0000
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
0x01FF
0x01FF
0x0000
…
0x0000
Rev. C | Page 23 of 42
AD7091R-8
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NOP
…
NOP
Access
AD7091R-4
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
…
NOP
AD7091R-2
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
…
NOP
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
CONVERSION RESULT REGISTER
The conversion result register is a 16-bit, read only register that stores the results from the most recent ADC conversion in straight binary
format. The channel ID of the converted channel and the alert status are also included in the register.
Figure 47. Conversion Result Register
Table 11. Conversion Result Register Map
MSB
B15
B14
CH_ID
B13
B12
ALERT
B11
B10
B9
B8
B7
B6
B5
CONV_RESULT
B4
B3
B2
LSB
B0
B1
Table 12. Bit Descriptions for the Conversion Result Register
Bit(s)
[15:13]
Name
CH_ID
12
ALERT
[11:0]
CONV_RESULT
1
2
Description
3-bit channel ID of channel converted
B15 1, 2
B142
B13
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ALERT flag
0: No ALERT occurred
1: ALERT occurred
12-bit conversion result
Reset
0x0
Access
R
0
R
0x000
R
Analog Input Channel
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
Always zero on the AD7091R-4.
Always zero on the AD7091R-2.
Rev. C | Page 24 of 42
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
CHANNEL REGISTER
The channel register on the AD7091R-2/AD7091R-4/AD7091R-8 is an 8-bit, read/write register. Each of the eight analog input channels has
one corresponding bit in the channel register. To select a channel for inclusion in the channel conversion sequence, set the corresponding
channel bit to 1 in the channel register. There is a latency of one conversion before the channel conversion sequence is updated. If the channel
register is programmed with a new value, the conversion sequence is reset to the lowest numbered channel in the new value.
Figure 48. Channel Registers
Table 13. Channel Register Map
MSB
B15
B14
B13
B12
B11
Reserved
B10
B9
B8
B7
CH7
B6
CH6
B5
CH5
B4
CH4
B3
CH3
B2
CH2
B1
CH1
Table 14. Bit Descriptions for the Channel Register
Bit(s)
[15:8]
7
Name
Reserved
CH7
6
CH6
5
CH5
4
CH4
3
CH3
2
CH2
1
CH1
0
CH0
Description
Reserved
Convert on Channel 7
0: Disable Channel 7
1: Enable Channel 7
Convert on Channel 6
0: Disable Channel 6
1: Enable Channel 6
Convert on Channel 5
0: Disable Channel 5
1: Enable Channel 5
Convert on Channel 4
0: Disable Channel 4
1: Enable Channel 4
Convert on Channel 3
0: Disable Channel 3
1: Enable Channel 3
Convert on Channel 2
0: Disable Channel 2
1: Enable Channel 2
Convert on Channel 1
0: Disable Channel 1
1: Enable Channel 1
Convert on Channel 0
0: Disable Channel 0
1: Enable Channel 0
Rev. C | Page 25 of 42
Reset
0x00
0x0
Access
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
LSB
B0
CH0
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
CONFIGURATION REGISTER
The configuration register is a 16-bit, read/write register that is used to set the operating modes of the AD7091R-2/AD7091R-4/AD7091R-8.
Figure 49. Configuration Register
Table 15. Configuration Register Map
MSB
B15
B14
B13
B12
B11
Reserved
B10
B9
B8
SRST
Reserved
B7
ALERT_
STICKY
B6
ALERT_
DRIVE_TYPE
B5
BUSY
B4
ALERT_EN_
OR_GPO0
B3
ALERT_POL_
OR_GPO0
B2
GPO1
LSB
B1 B0
P_DOWN
Table 16. Bit Descriptions for the Configuration Register
Bit(s)
[15:10]
9
Name
Reserved
SRST
8
7
Reserved
ALERT_STICKY
6
ALERT_DRIVE_TYPE
5
BUSY
Description
Reserved
Software reset bit. Setting this bit resets the internal digital control logic and
the result and alert registers, but it does not reset the other memory map
registers. This bit automatically clears in the next clock cycle. Note that it
loads random access memory (RAM) from fuses.
0: Soft reset not active.
1: Activate soft reset.
Reserved
ALERT bit is sticky. It is not cleared on a valid hysteresis condition.
0: Clear ALERT 1 if the result falls beyond hysteresis.
1: Clear ALERT1 only on a read or soft reset.
Drive type of ALERT1 pin.
0: ALERT1 pin is of open-drain drive type.
1: ALERT1 pin is of CMOS drive type.
ALERT1 pin indicates if the part is busy converting.
0: ALERT1 pin is not used for BUSY status.
1: ALERT1 pin is used for BUSY status, provided ALERT_EN_OR_GPO0) is 1.
Else, this bit is always read back as 0.
Rev. C | Page 26 of 42
Reset
0x00
0x0
Access
R
RWAC
0x0
0x1
R
R/W
0x1
R/W
0x0
R/W
Data Sheet
Bit(s)
4
Name
ALERT_EN_OR_GPO0
3
ALERT_POL_OR_GPO0
2
GPO1
[1:0]
P_DOWN
1
AD7091R-2/AD7091R-4/AD7091R-8
Description
Enable ALERT pin or GPO01.
0: ALERT1 pin used as GPO01.
1: ALERT1 pin is used for ALERT1/BUSY1 status.
Polarity of ALERT1 pin (if ALERT_EN_OR_GPO0 is 1) or value at GPO01.
0: Active low ALERT1 polarity (if ALERT_EN_OR_GPO0 = 1) or GPO01 = 0.
1: Active high ALERT1 polarity (if ALERT_EN_OR_GPO0 = 1) or GPO01 = 1.
Value at GPO11.
0: Drive 0 on GPO11 pin.
1: Drive 1 on GPO11 pin.
Power-down mode.
Setting Mode
Sleep Mode/Bias Generator Internal Reference
00
Mode 0 Off
Off
01
Mode 1 Off
On
10
Mode 2 On
Off
11
Mode 3 On
On
Reset
0x0
Access
R/W
0x0
R/W
0x0
R/W
0x0
R/W
When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configurations and Function Descriptions section.
Rev. C | Page 27 of 42
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
ALERT INDICATION REGISTER
The 16-bit, alert indication register is a read only register that
provides information on an alert event. If a conversion result
activates the ALERT function of the ALERT/BUSY/GPO0 pin,
as described in the Channel x Low Limit Register section and
the Channel x High Limit Register section, the alert register can
be read to determine the source of the alert. The register contains
two status bits per channel, one corresponding to the high limit,
and the other to the low limit. The bit with a status equal to 1
shows where the violation occurred, that is, on which channel,
and whether the violation occurred on the upper or lower limit.
If a second alert event occurs on another channel between
receiving the first alert and interrogating the alert register, the
corresponding bit for that alert event is also set.
The contents of the alert indication register are reset by reading
it. The alert indication register is reset on the second SCLK
cycle of the SPI frame where the ALERT data is read out. If a
conversion happens in the meantime, the conversion result is
sent instead of the alert indication register contents. The alert
indication register is not reset in this case.
The alert bits for any unimplemented channels on the 2-channel
and 4-channel devices always return zeros.
Figure 50. Alert Indication Register (Figure Shows Default Register Value of 0, Indicating No Alert Has Occurred)
Table 17. Alert Indication Register Map
MSB
B15
LO_7
B14
HI_7
B13
LO_6
B12
HI_6
B11
LO_5
B10
HI_5
B9
LO_4
B8
HI_4
B7
LO_3
B6
HI_3
B5
LO_2
B4
HI_2
B3
LO_1
B2
HI_1
B1
LO_0
Table 18. Bit Descriptions for the Alert Indication Register
Bit(s)
15
Bit Name
LO_7
14
HI_7
Description
Channel 7 low alert status
0: No alert on Channel 7
1: Low alert occurred on Channel 7
Channel 7 high alert status
0: No alert on Channel 7
1: High alert occurred on Channel 7
Rev. C | Page 28 of 42
Reset
0x0
Access
R
0x0
R
LSB
B0
HI_0
Data Sheet
Bit(s)
13
Bit Name
LO_6
12
HI_6
11
LO_5
10
HI_5
9
LO_4
8
HI_4
7
LO_3
6
HI_3
5
LO_2
4
HI_2
3
LO_1
2
HI_1
1
LO_0
0
HI_0
AD7091R-2/AD7091R-4/AD7091R-8
Description
Channel 6 low alert status
0: No alert on Channel 6
1: Low alert occurred on Channel 6
Channel 6 high alert status
0: No alert on Channel 6
1: High alert occurred on Channel 6
Channel 5 low alert status
0: No alert on Channel 5
1: Low alert occurred on Channel 5
Channel 5 high alert status
0: No alert on Channel 5
1: High alert occurred on Channel 5
Channel 4 low alert status
0: No alert on Channel 4
1: Low alert occurred on Channel 4
Channel 4 high alert status
0: No alert on Channel 4
1: High alert occurred on Channel 4
Channel 3 low alert status
0: No alert on Channel 3
1: Low alert occurred on Channel 3
Channel 3 high alert status
0: No alert on Channel 3
1: High alert occurred on Channel 3
Channel 2 low alert status
0: No alert on Channel 2
1: Low alert occurred on Channel 2
Channel 2 high alert status
0: No alert on Channel 2
1: High alert occurred on Channel 2
Channel 1 low alert status
0: No alert on Channel 1
1: Low alert occurred on Channel 1
Channel 1 high alert status
0: No alert on Channel 1
1: High alert occurred on Channel 1
Channel 0 low alert status
0: No alert on Channel 0
1: Low alert occurred on Channel 0
Channel 0 high alert status
0: No alert on Channel 0
1: High alert occurred on Channel 0
Rev. C | Page 29 of 42
Reset
0x0
Access
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
CHANNEL x LOW LIMIT REGISTER
Of the 16 bits, B15 to B9 are not used. Only the nine LSBs, B8 to
B0, are used. These 9 bits, which are programmed by the user,
are used as the MSBs of the internal 12-bit register. The 3 LSBs
in the internal 12-bit registers are set to 111.
Each analog input channel of the AD7091R-2/AD7091R-4/
AD7091R-8 has its own low limit register. The low limit
registers are 16-bit read/write registers. See Table 10 for the
register addresses. The low limit registers store the lower limit
of the conversion value that activates the ALERT output.
CHANNEL x HYSTERESIS REGISTER
Each analog input channel of the AD7091R-2/AD7091R-4/
AD7091R-8 has its own hysteresis register, which are 16-bit
read/write registers. See Table 10 for the register addresses. The
hysteresis register stores the hysteresis value (N) when using the
limit registers. The hysteresis value determines the reset point
for the ALERT/BUSY/GPO0 pin if a violation of the limits has
occurred.
Of the 16 bits, B15 to B9 are not used. Only the nine LSBs, B8 to
B0, are used. These 9 bits, which are programmed by the user,
are used as the MSBs of the internal 12-bit register. The 3 LSBs
in the internal 12-bit registers are set to 000.
CHANNEL x HIGH LIMIT REGISTER
Each analog input channel of the AD7091R-2/AD7091R-4/
AD7091R-8 has its own high limit register. The high limit
registers are 16-bit read/write registers. See Table 10 for the
register addresses. The high limit registers store the upper limit
of the conversion value that activates the ALERT output.
Of the 16 bits, B15 to B9 are not used. Only the nine LSBs, B8 to
B0, are used. These 9 bits, which are programmed by the user,
are used as the MSBs of the internal 12-bit register. The 3 LSBs
in the internal 12-bit registers are set to 000.
Table 19. Channel x Low Limit Register Map
MSB
B15
B14
B13
B12
B11
Reserved
B10
B9
B8
B7
B6
B5
B4
B3
CHx LOW LIMIT
B2
B1
LSB
B0
Table 20. Bit Descriptions for the Channel x Low Limit Register
Bit(s)
[15:9]
[8:0]
Bit Name
Reserved
CHx LOW LIMIT
Description
Reserved
Low limit value for Channel x
Reset
0x00
0x000
Access
R
R/W
Table 21. Channel x High Limit Register Map
MSB
B15
B14
B13
B12
B11
Reserved
B10
B9
B8
B7
B6
B5
B4
B3
CHx HIGH LIMIT
B2
B1
LSB
B0
Table 22. Bit Descriptions for the Channel x High Limit Register
Bits
[15:9]
[8:0]
Bit Name
Reserved
CHx HIGH LIMIT
Description
Reserved
High limit value for Channel x
Reset
0x00
0x1FF
Access
R
R/W
Table 23. Channel x Hysteresis Register Map
MSB
B15
B14
B13
B12
B11
Reserved
B10
B9
B8
B7
B6
B5
B4
B3
CHx HYSTERESIS
B2
B1
LSB
B0
Table 24. Bit Descriptions for the Channel x Hysteresis Register
Bit(s)
[15:9]
[8:0]
Bit Name
Reserved
CHx HYSTERESIS
Description
Reserved
Hysteresis value for Channel x
Rev. C | Page 30 of 42
Reset
0x00
0x1FF
Access
R
R/W
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
SERIAL PORT INTERFACE
The SPI is a 4-wire interface (three inputs and one output) for
serial data communication. It has a chip select (CS) line, a serial
clock (SCLK), a serial data input (SDI), and a serial data output
(SDO). Data transfers on SDI and SDO take place with respect
to SCLK. CS is used to frame the data and is active low. When
CS is high, SDO is kept in high impedance. The falling edge of
CS takes the SDO line out of the high impedance state. A rising
edge on CS returns the SDO to a high impedance state.
on the 16th rising edge and the 16th falling edge, having
clocked out on the previous (15th) falling edge. After the 16th
falling edge, take CS high again to return the SDO to a high
impedance state. If another conversion is required, take the
CONVST pin low again (after at least 1 μs), and repeat the read
cycle. The timing diagram for this operation is shown in Figure 52.
WRITING DATA TO THE REGISTERS
The SPI implemented on the AD7091R-2/AD7091R-4/AD7091R-8
can support both of the following: CPHA and CPOL = 0, and
CPHA and CPOL = 1. This support ensures that the device can
interface to microcontrollers and DSPs that keep either SCLK
high or SCLK low when CS is not asserted. The device ignores
SCLK toggling when CS is not asserted.
All the read/write registers in the device can be written over the
SPI. A register write command is performed by a single 16-bit SPI
access. The format for a write command is shown in Table 25.
Bits[B15:B11] contain the register address. See Table 10 for the
complete list of register addresses. Setting Bit B10 to 1 selects a
write command. The subsequent 10 bits (Bits[B9:B0]) contain
the data to be written to the selected register.
READING CONVERSION RESULT
READING DATA FROM THE REGISTERS
The CONVST signal is used to initiate the conversion process.
A high-to-low transition on the CONVST signal puts the trackand-hold into hold mode and samples the analog input at this
point. A conversion is initiated and requires 600 ns to complete.
Before the end of the conversion, take the CONVST signal high
again. When the conversion process is finished, the track-andhold mode goes back into track mode. Then, take the CS pin
low, and the conversion result clocks out on the SDO pin. The
data is shifted out of the device as a 16-bit word under the
control of the serial clock (SCLK) input. The data is shifted out
on the falling edge of SCLK, and the data bits are valid on both
the rising edge and the falling edge. The MSB is shifted out on
the falling edge of CS. The final bit in the data transfer is valid
All the registers in the device can be read over the SPI. A register
read is performed by issuing a register read command followed
by an additional SPI command that can be either a valid command
or NOP. The format for a read command is shown in Table 26.
Bits[B15:B11] contain the register address. See Table 10 for the
complete list of register addresses. Setting Bit B10 to 0 selects
a read command. The device ignores the subsequent bits
(Bits[B9:B0]).
Any conversion event is treated as a special case and overrides
a previous read command. The AD7091R-2/AD7091R-4/
AD7091R-8 always drive out the conversion result register
on SDO after a conversion even though a register read was
initiated in the previous SPI frame.
Table 25. Write Command Message Configuration
B14
B13
B12
Register Address[4:0]
B11
B10
1
B9
B8
B7
B6
B5
B4
Data[9:0]
B3
B2
LSB
B0
B1
CONVST
CS
SDI
WRITE REG 1
WRITE REG 2
WRITE REG 3
SDO
CONV RESULT
INVALID DATA
INVALID DATA
Figure 51. Serial Interface Register Write
Rev. C | Page 31 of 42
10891-024
MSB
B15
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
Table 26. Read Command Message Configuration
B14
B13
B12
Register Address[4:0]
B11
B10
0
B9
B8
B7
B6
B5
B4
Don’t Care
B3
B2
LSB
B0
B1
CONVST
CS
SDI
READ REG 1
READ REG 2
READ REG 3
SDO
CONV RES
REG 1 DATA
REG 2 DATA
Figure 52. Serial Interface Register Read
Rev. C | Page 32 of 42
10891-025
MSB
B15
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
POWER-ON DEVICE INITIALIZATION
In lieu of applying a pulse to the RESET pin from the digital
host at initial power up, it is possible to replicate the behavior
of the hardware reset function through the application of an
alternative stimulus to the CONVST pin. Once the internal
regulator voltage has been established by VDD reaching a voltage
of 2.1 V, a series of CONVST pulses must be sent to the ADC.
Following the subsequent procedure will reset the device,
allowing for proper and expected operation.
4.
5.
To issue a software initialization,
2.
3.
Establish the VDD and VDRIVE supplies for the AD7091R-2/
AD7091R-4/ AD7091R-8. The power-on time will depend
upon the supply pin decoupling load and drive strength of
the supply resource.
Provide 66 pulses on the CONVST pin that are spaced a
minimum of 2 μs apart. The pulse width on the CONVST
pin must adhere to the tCNVPW timing specification.
At the end of the 66th pulse, the ADC is initialized and in a
ready state. The device can now be configured by the user.
If using the on-chip internal reference, to meet specified
performance, the user should wait until the reference capacitor
is fully charged. The reference buffer requires 50 ms to power
up and charge the 2.2 μF decoupling capacitor during the
power-up time.
In digital pin limited applications, the RESET pin of the
AD7091R-2/AD7091R-4/AD7091R-8 should be tied to the
VDRIVE supply either directly or via a pull-up resistor.
Figure 53 shows the timing diagram for this operation.
tRESET_DELAY
VDD
VDRIVE
tCYC_RESET
CONVST
1
2
66
CS
SDI
WRITE REG 1
Figure 53. Power On Software Reset Timing
Rev. C | Page 33 of 42
WRITE REG 2
10891-142
1.
At this point, all internal registers will be in an unknown
state. Write the desired device configuration as described
in the Writing Data to the Registers section. To place all
write enabled internal registers in a known state, writing to
all device registers is required.
Reset the read-only registers by activating the software
reset bit of the Configuration Register when performing
the write actions described in Step 4. See details in the
Configuration Register section.
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
MODES OF OPERATION
NORMAL MODE
The user controls whether the device remains in normal mode
or enters power-down mode. These modes of operation provide
flexible power management options, allowing optimization of
the power dissipation and throughput rate ratio for different
application requirements.
To achieve the fastest throughput rate performance, use normal
mode. Power-up times are not an issue for the AD7091R-2/
AD7091R-4/AD7091R-8 because they remain fully powered at
all times. Figure 54 shows the general diagram of the AD7091R-2/
AD7091R-4/AD7091R-8 in normal mode. The conversion
initiates on the falling edge of CONVST, as described in the
Serial Port Interface section. To ensure that the device remains
fully powered up at all times, return CONVST high before
tCONVERT and keep it high until the conversion has finished. The
end of conversion (EOC) point shown in Figure 54 indicates the
end of EOC and the moment when the logic level of CONVST
is tested.
To read back data stored in the conversion result register, wait
until the conversion is completed. Then, take CS low, and the
conversion data clocks out on the SDO pin. The output shift
register is 16 bits wide. Data is shifted out of the device as a
16-bit word under the control of the serial clock (SCLK) input.
The full timing diagram for this operation is shown in Figure 4.
When the conversion read is completed, pull CONVST low
again to start another conversion.
POWER-DOWN MODE
When slower throughput rates and lower power consumption
are required, use power-down mode by either powering down
the ADC between each conversion or by performing a series of
conversions at a high throughput rate and then powering down
the ADC for a relatively long duration between these burst
conversions. When the AD7091R-2/AD7091R-4/AD7091R-8
are in power-down mode, all analog circuitry power down;
however, the serial interface is active.
To enter power-down mode, write to the power-down
configuration bits in the configuration register, as seen in Table 15.
To enter full power-down mode, set the sleep mode/bias
generator bit to 1, and set the internal reference bit to 0, which
ensures that all analog circuitry and the internal reference
power down. When the internal reference is enabled, it
consumes power anytime Bit 0 of the configuration register
is set to 1.
The serial interface of the AD7091R-2/AD7091R-4/AD7091R-8
is functional in power-down; therefore, the user can read back
the results of the conversion after the device enters power-down
mode.
To exit this mode of operation and to power up the AD7091R-2/
AD7091R-4/AD7091R-8 again, write to the power-down
configuration bits in the configuration register (see Table 15).
On the rising edge of CONVST, the device begins to power up.
The power-up time of the AD7091R-2/AD7091R-4/AD7091R-8
is typically 1 μs. After power-up is complete, the ADC is fully
powered up, and the input signal is properly acquired. To start
the next conversion, operate the interface as described in the
Normal Mode section. When using the internal reference, and
the device is in full power-down mode, the user must wait to
perform conversions until the internal reference has had time
to power up and settle. The reference buffer requires 50 ms to
power up and charge the 2.2 μF decoupling capacitor during the
power-up time.
By using the power-down mode on the AD7091R-2/AD7091R-4/
AD7091R-8 when this device is not converting, the average
power consumption of the ADC decreases at lower throughput
rates. Use power-down mode with lower throughput rates.
When there is not a significant time interval between bursts of
conversions, use normal mode (see the Normal Mode section).
EOC
tCNVPW
CONVST
tCONVERT
tEOCCSL
CS
SDO
CONVERSION DATA
Figure 54. Serial Interface Read Timing in Normal Mode
Rev. C | Page 34 of 42
tDIS
10891-026
tEN
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
ALERT (AD7091R-4 AND AD7091R-8 ONLY)
The alert functionality is used as an out-of-range indicator. An
alert event is triggered when the value in the conversion result
register exceeds the CHx HIGH LIMIT value in the channel high
limit register or falls below the CHx LOW LIMIT value in the
channel low limit register for a selected channel.
The ALERT/BUSY/GPO0 pin has an open-drain configuration
that allows the alert outputs of several AD7091R-4/AD7091R-8
devices to be wired together when the ALERT function of the
ALERT/BUSY/GPO0 pin is active low. The ALERT_DRIVE_TYPE
bit (Bit 6) of the configuration register controls the ALERT/
BUSY/GPO0 pin configuration.
Detailed alert information is accessible in the alert register. The
register contains two status bits per channel, one corresponding
to the high limit, and the other to the low limit. A logical OR of
alert signals for all channels creates a common alert value. This
value can be accessed by the alert bit in the conversion result
register and configured to drive out on the ALERT function of
the ALERT/BUSY/GPO0 pin. The ALERT/BUSY/GPO0 pin is
configured as ALERT by configuring the following bits in the
configuration register:
When using the ALERT function of the ALERT/BUSY/GPO0
pin and the open-drain configuration, an external pull-up
resistor is required. Connect the external pull-up resistor to
VDRIVE. The resistor value is application dependent; however, it
must be large enough to avoid excessive sink currents when the
ALERT function of the ALERT/BUSY/GPO0 pin is triggered.
•
•
•
Use the ALERT_POL_OR_GPO0 bit (Bit 3) of the configuration
register to set the active polarity of the alert output. The power-up
default is active low.
BUSY (AD7091R-4 AND AD7091R-8 ONLY)
Set the ALERT_EN_OR_GPO0 bit, Bit 4, to 1.
Set the BUSY bit, Bit 5, to 0.
Set the ALERT_POL_OR_GPO0 bit, Bit 3, to 0 for the
ALERT function of the ALERT/BUSY/GPO0 pin to be
active low, and set it to 1 for the ALERT function of the
ALERT/BUSY/GPO0 pin to be active high.
When configuring the ALERT/BUSY/GPO0 pin as a BUSY output,
use the pin to indicate when a conversion is taking place. To
configure the ALERT/BUSY/GPO0 pin as BUSY, use the
following bits in the configuration register:
The alert register, alert bit, and the ALERT function of the
ALERT/BUSY/GPO0 pin are cleared by reading the alert register
contents. Additionally, if the conversion result goes beyond the
hysteresis value for a selected channel, the alert bit corresponding
to that channel is reset automatically. The automatic clearing of
the alert status can be disabled by setting the ALERT_STICKY
bit in the configuration register to 1. If the ALERT_STICKY bit
is set when an alert occurs, it can only be reset by a read of the
alert register. Issuing a software reset also clears the alert status.
•
•
•
Set the ALERT_EN_OR_GPO0 bit, Bit 4, to 1.
Set the BUSY bit, Bit 5, to 1.
Set the ALERT_POL_OR_GPO0 bit, Bit 3, to 0 for the
BUSY pin to be active low, and set it to 1 for the BUSY pin
to be active high.
When using the BUSY function of the ALERT/BUSY/GPO0 pin,
an external pull-up resistor is required because the output is an
open-drain configuration. Connect the external pull-up resistor
to VDRIVE. The resistor value is application dependent; however,
it must be large enough to avoid excessive sink currents when the
BUSY function of the ALERT/BUSY/GPO0 pin is triggered.
Rev. C | Page 35 of 42
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
CHANNEL SEQUENCER
The AD7091R-2/AD7091R-4/AD7091R-8 include a channel
sequencer that is useful for scanning channels in a repeated
fashion. Channels included in the sequence are configured in
the channel register. If all the bits in the channel register are 0,
Channel 0 is selected by default, and all conversions happen on
this channel. If the channel register is nonzero, the conversion
sequence starts from the lowest numbered channel enabled in
the channel register. The sequence cycles through all the
enabled channels in ascending order. After all the channels
in the sequence are converted, the sequence starts again.
There is a latency of one conversion before the channel conversion
sequence is updated. If the channel register is programmed with
a new value, the conversion sequence is reset to the lowest
numbered channel in the new value.
CONVST
SDI
WRITE 0x00F0
CHANNEL REG
NOP
NOP
NOP
SDO
RESULT
CHANNEL 0
RESULT
CHANNEL 0
RESULT
CHANNEL 4
RESULT
CHANNEL 5
10891-028
CS
Figure 55. Channel Sequencer
CONVST
SDI
WRITE 0x001
CHANNEL REG
WRITE 0x002
CHANNEL REG
WRITE 0x004
CHANNEL REG
WRITE 0x008
CHANNEL REG
WRITE 0x0010
CHANNEL REG
SDO
RESULT
CHANNEL 0
RESULT
CHANNEL 0
RESULT
CHANNEL 0
RESULT
CHANNEL 1
RESULT
CHANNEL 2
Figure 56. Channel Sequencer Multiple Channel Write
Rev. C | Page 36 of 42
10891-029
CS
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
DAISY CHAIN
Each AD7091R-2/AD7091R-4/AD7091R-8 slave in the chain
requires a 16-bit SPI command. If there are N slaves, each SPI
frame must have N × 16 bits of data. In the AD7091R-2/
AD7091R-4/AD7091R-8, when the bit counter crosses 16 bits,
all of the received bits are sent out over the SDO. The output
from the first slave is the input of the second slave. Effectively,
each slave ignores all the incoming 16-bit SPI commands except
the last one. The SPI command received just before the CS
rising edge is the only valid SPI command for a given device in
the daisy chain. The output on the next SPI frame is determined
by the valid SPI command or any conversion event.
Daisy-chain mode is intended for applications where multiple
AD7091R-2/AD7091R-4/AD7091R-8 devices are used. This
feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity.
All ADC slaves are addressed by the same CS, CONVST, and
SCLK signals. The SDI of the first AD7091R-2/AD7091R-4/
AD7091R-8 slave in the chain is driven directly by the master
output, slave input (MOSI) pin of the SPI master. The SDO of
the first slave is connected to the SDI of the second slave. All the
subsequent slaves are connected in this fashion, and the SDO of
the last slave drives the master input, slave output (MISO) pin
of the master. A connection diagram example using two
AD7091R-2/AD7091R-4/AD7091R-8 devices is shown in
Figure 57.
The methods for reading a conversion result to configuring the
slave registers are outlined in Figure 58 to Figure 62 for a twoslave example. Additional slave devices can be added to the
chain by following the same principles defined for the twodevice configuration.
MOSI
SS
CS
CS
AD7091R-x
AD7091R-x
SLAVE A
CONVST
SDI
SDO
MISO
SDO
SLAVE B
SCLK
CONVST
SCLK
SCLK
CONVERT
10891-030
SDI
DIGITAL HOST
SPI MASTER
Figure 57. Daisy-Chain Configuration
CONVST
CS
1
16 17
32
1
16 17
32
NOP
NOP
NOP
NOP
SDO A/
SDI B
CONV_RESULT A
NOP
CONV_RESULT A
NOP
SDO B
CONV_RESULT B
CONV_RESULT A
CONV_RESULT B
CONV_RESULT A
SDI A
Figure 58. Conversion in a Two-Slave Daisy-Chain Mode Configuration
Rev. C | Page 37 of 42
10891-031
SCLK
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
CONVST
CS
1
16 17
32
SDI A
WRITE REG1 B
WRITE REG2 A
SDO A/
SDI B
INVALID DATA
WRITE REG1 B
SDO B
INVALID DATA
INVALID DATA
10891-032
SCLK
Figure 59. Single Register Write in a Two-Slave Daisy-Chain Mode Configuration
CONVST
CS
1
16 17
1
32
16 17
32
READ REG1 B
READ REG2 A
NOP
NOP
SDO A/
SDI B
CONV_RESULT A
READ REG1 B
DATA REG2 A
NOP
SDO B
CONV_RESULT B
CONV_RESULT A
DATA REG1 B
DATA REG2 A
SDI A
10891-033
SCLK
Figure 60. Single Register Read in a Two-Slave Daisy-Chain Mode Configuration
CONVST
CS
1
16 17
32
1
16 17
32
1
16 17
32
READ REG1 B
READ REG2 A
READ REG3 B
READ REG4 A
NOP
NOP
SDO A/
SDI B
CONV_RESULT A
READ REG1 B
DATA REG2 A
READ REG3 B
DATA REG4 A
NOP
SDO B
CONV_RESULT B
CONV_RESULT A
DATA REG1 B
DATA REG2 A
DATA REG3 B
DATA REG4 A
SDI A
10891-034
SCLK
Figure 61. Multiple Register Read in a Two-Slave Daisy-Chain Mode Configuration
CONVST
CS
1
16 17
32
1
16 17
32
1
16 17
32
WRITE REG1 B
WRITE REG2 A
WRITE REG3 B
WRITE REG4 A
NOP
NOP
SDO A/
SDI B
CONV_RESULT A
WRITE REG1 B
INVALID DATA
WRITE REG3 B
INVALID DATA
NOP
SDO B
CONV_RESULT B
CONV_RESULT A
INVALID DATA
INVALID DATA
INVALID DATA
INVALID DATA
SDI A
Figure 62. Multiple Register Write in a Two-Slave Daisy-Chain Mode Configuration
Rev. C | Page 38 of 42
10891-035
SCLK
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.35
0.30
0.25
16
13
0.65
BSC
PIN 1
INDICATOR
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.20 MIN
08-16-2010-C
0.80
0.75
0.70
5
8
0.45
0.40
0.35
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 63. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.65
BSC
0.30
0.19
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 64. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. C | Page 39 of 42
0.75
0.60
0.45
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.30
0.25
0.20
20
16
15
0.50
BSC
PIN 1
INDICATOR
1
EXPOSED
PAD
2.65
2.50 SQ
2.35
5
11
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
061609-B
0.80
0.75
0.70
6
10
0.50
0.40
0.30
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 65. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-10)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
1
10
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 66. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Rev. C | Page 40 of 42
0.75
0.60
0.45
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.30
0.25
0.18
PIN 1
INDICATOR
24
19
0.50
BSC
18
1
2.65
2.50 SQ
2.45
EXPOSED
PAD
13
0.50
0.40
0.30
TOP VIEW
0.80
0.75
0.70
6
7
12
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
03-11-2013-A
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 67. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-7)
Dimensions shown in millimeters
7.90
7.80
7.70
24
13
4.50
4.40
4.30
1
6.40 BSC
12
PIN 1
0.65
BSC
0.15
0.05
0.30
0.19
0.10 COPLANARITY
1.20
MAX
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 68. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
Rev. C | Page 41 of 42
AD7091R-2/AD7091R-4/AD7091R-8
Data Sheet
ORDERING GUIDE
Model 1
AD7091R-2BCPZ
AD7091R-2BCPZ-RL7
AD7091R-2BRUZ
AD7091R-2BRUZ-RL7
EVAL-AD7091R-2SDZ
AD7091R-4BCPZ
AD7091R-4BCPZ-RL7
AD7091R-4BRUZ
AD7091R-4BRUZ-RL7
EVAL-AD7091R-4SDZ
AD7091R-8BCPZ
AD7091R-8BCPZ-RL7
AD7091R-8BRUZ
AD7091R-8BRUZ-RL7
EVAL-AD7091R-8SDZ
EVAL-SDP-CB1Z
1
Channels
2
2
2
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
4
4
4
4
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8
8
8
8
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
Evaluation Board
Evaluation Controller Board
Z = RoHS Compliant Part.
©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10891-0-12/15(C)
Rev. C | Page 42 of 42
Package Option
CP-16-17
CP-16-17
RU-16
RU-16
CP-20-10
CP-20-10
RU-20
RU-20
CP-24-7
CP-24-7
RU-24
RU-24